Module Name: src
Committed By: martin
Date: Thu Nov 8 12:11:28 UTC 2018
Modified Files:
src/doc [netbsd-8]: CHANGES-8.1
Log Message:
Ticket #1084 and #1085
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.50 -r1.1.2.51 src/doc/CHANGES-8.1
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/doc/CHANGES-8.1
diff -u src/doc/CHANGES-8.1:1.1.2.50 src/doc/CHANGES-8.1:1.1.2.51
--- src/doc/CHANGES-8.1:1.1.2.50 Wed Nov 7 09:13:44 2018
+++ src/doc/CHANGES-8.1 Thu Nov 8 12:11:27 2018
@@ -1,4 +1,4 @@
-# $NetBSD: CHANGES-8.1,v 1.1.2.50 2018/11/07 09:13:44 martin Exp $
+# $NetBSD: CHANGES-8.1,v 1.1.2.51 2018/11/08 12:11:27 martin Exp $
A complete list of changes from the NetBSD 8.0 release to the NetBSD 8.1
release:
@@ -1618,3 +1618,31 @@ external/gpl2/groff/dist/configure 1.2
the cross-compile from FreeBSD.
[sevan, ticket #1083]
+sys/dev/pci/ixgbe/ixgbe.c 1.167
+sys/dev/pci/ixgbe/ixv.c 1.107
+
+ Don't set LRO capability flag because we don't support it yet.
+ [msaitoh, ticket #1084]
+
+sys/dev/mii/inbmphyreg.h 1.11
+sys/dev/pci/if_wmreg.h 1.108
+sys/dev/pci/if_wm.c 1.590-1.596 via patch
+
+ - 82574 and newer document says the status field has neither EC
+ (Excessive Collision) bit nor LC (Late Collision) bit (reserved), so
+ don't check the bit.
+ - Add workaround for DMA hang problem which result in TX device timeout
+ on PCH_LPT with I218. Same as FreeBSD and Linux. This workaround is
+ only for device ID 0x155a, 0x15a2, 0x1559 and 0x15a3.
+ - Fix a PCH2 specific bug that wrong PHY register value can be read
+ when boot. Same as FreeBSD and Linux.
+ - After writing MDIC register, don't read quickly the same register but
+ do delay(50). Same as other OSes.
+ - Add missing wm_gate_hw_phy_config_ich8lan(false) in
+ wm_phy_post_reset() on PCH2. wm_gate_hw_phy_config_ich8lan(true) is
+ called in wm_reset(), so wm_gate_hw_phy_config_ich8lan(false) should
+ be called after reset in wm_phy_post_reset().
+ - On PCH2, set the phy config counter to 50msec after (PHY) reset.
+ - KNF & Use macro.
+ [msaitoh, ticket #1085]
+
