Module Name: src Committed By: jdolecek Date: Mon Nov 19 22:05:23 UTC 2018
Modified Files: src/sys/dev/ic: ahcisata_core.c Log Message: during SRST (softreset), make a short delay between the RST set and clear; SATA specifies minimum 5 usec for the toggle period, and some controllers (seems usually on AMD motherboards) actually require it this fixes the 'clearing WDCTL_RST failed' error in PR kern/53307 and PR kern/53524 confirmed working on a ASUS Prime A320M-K mainboard by me, and by Patrick Welche on another Ryzen system XXX pullup-8 To generate a diff of this commit: cvs rdiff -u -r1.68 -r1.69 src/sys/dev/ic/ahcisata_core.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/dev/ic/ahcisata_core.c diff -u src/sys/dev/ic/ahcisata_core.c:1.68 src/sys/dev/ic/ahcisata_core.c:1.69 --- src/sys/dev/ic/ahcisata_core.c:1.68 Mon Nov 19 21:52:24 2018 +++ src/sys/dev/ic/ahcisata_core.c Mon Nov 19 22:05:22 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: ahcisata_core.c,v 1.68 2018/11/19 21:52:24 jdolecek Exp $ */ +/* $NetBSD: ahcisata_core.c,v 1.69 2018/11/19 22:05:22 jdolecek Exp $ */ /* * Copyright (c) 2006 Manuel Bouyer. @@ -26,7 +26,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.68 2018/11/19 21:52:24 jdolecek Exp $"); +__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.69 2018/11/19 22:05:22 jdolecek Exp $"); #include <sys/types.h> #include <sys/malloc.h> @@ -841,6 +841,13 @@ ahci_do_reset_drive(struct ata_channel * break; } + /* + * SATA specification has toggle period for SRST bit of 5 usec. Some + * controllers fail to process the SRST clear operation unless + * we wait for at least this period between the set and clear commands. + */ + ata_delay(chp, 10, "ahcirstw", flags); + cmd_h->cmdh_flags = htole16(RHD_FISLEN / 4 | (drive << AHCI_CMDH_F_PMP_SHIFT)); cmd_h->cmdh_prdbc = 0;