Module Name: src
Committed By: knakahara
Date: Mon Nov 26 23:20:57 UTC 2018
Modified Files:
src/usr.sbin/tprof: tprof.8
src/usr.sbin/tprof/arch: tprof_x86.c
Log Message:
tprof: Add goldmont plus support. Tested by msaitoh@n.o, thanks.
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/usr.sbin/tprof/tprof.8
cvs rdiff -u -r1.6 -r1.7 src/usr.sbin/tprof/arch/tprof_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/tprof/tprof.8
diff -u src/usr.sbin/tprof/tprof.8:1.12 src/usr.sbin/tprof/tprof.8:1.13
--- src/usr.sbin/tprof/tprof.8:1.12 Mon Nov 26 07:45:47 2018
+++ src/usr.sbin/tprof/tprof.8 Mon Nov 26 23:20:56 2018
@@ -1,4 +1,4 @@
-.\" $NetBSD: tprof.8,v 1.12 2018/11/26 07:45:47 knakahara Exp $
+.\" $NetBSD: tprof.8,v 1.13 2018/11/26 23:20:56 knakahara Exp $
.\"
.\" Copyright (c)2011 YAMAMOTO Takashi,
.\" All rights reserved.
@@ -24,7 +24,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.Dd November 26, 2018
+.Dd November 27, 2018
.Dt TPROF 8
.Os
.Sh NAME
@@ -137,6 +137,8 @@ x86 Intel Skylake/Kabylake
x86 Intel Silvermont/Airmont
.It
x86 Intel Goldmont
+.It
+x86 Intel Goldmont Plus
.El
.Sh DIAGNOSTICS
The
Index: src/usr.sbin/tprof/arch/tprof_x86.c
diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.6 src/usr.sbin/tprof/arch/tprof_x86.c:1.7
--- src/usr.sbin/tprof/arch/tprof_x86.c:1.6 Mon Nov 26 07:45:47 2018
+++ src/usr.sbin/tprof/arch/tprof_x86.c Mon Nov 26 23:20:57 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86.c,v 1.6 2018/11/26 07:45:47 knakahara Exp $ */
+/* $NetBSD: tprof_x86.c,v 1.7 2018/11/26 23:20:57 knakahara Exp $ */
/*
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -312,6 +312,45 @@ init_intel_goldmont(void)
}
/*
+ * Intel Goldmont Plus (Additions from Goldmont)
+ */
+static struct name_to_event intel_goldmontplus_names[] = {
+ { "INST_RETIRED.ANY", 0x00, 0x01, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 0x08, 0x02, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 0x08, 0x04, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED_1GB", 0x08, 0x08, true },
+ { "DTLB_LOAD_MISSES.WALK_PENDING", 0x08, 0x10, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 0x49, 0x02, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 0x49, 0x04, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED_1GB", 0x49, 0x08, true },
+ { "DTLB_STORE_MISSES.WALK_PENDING", 0x49, 0x10, true },
+ { "EPT.WALK_PENDING", 0x4F, 0x10, true },
+ { "ITLB_MISSES.WALK_COMPLETED_4K", 0x85, 0x08, true },
+ { "ITLB_MISSES.WALK_COMPLETED_2M_4M", 0x85, 0x04, true },
+ { "ITLB_MISSES.WALK_COMPLETED_1GB", 0x85, 0x08, true },
+ { "ITLB_MISSES.WALK_PENDING", 0x85, 0x10, true },
+ { "TLB_FLUSHES.STLB_ANY", 0xBD, 0x20, true },
+ { "MACHINE_CLEARS.PAGE_FAULT", 0xC3, 0x20, true },
+};
+
+static struct event_table intel_goldmontplus = {
+ .tablename = "Intel Goldmont Plus",
+ .names = intel_goldmontplus_names,
+ .nevents = sizeof(intel_goldmontplus_names) /
+ sizeof(struct name_to_event),
+ .next = NULL
+};
+
+static struct event_table *
+init_intel_goldmontplus(void)
+{
+
+ intel_goldmont.next = &intel_goldmontplus;
+
+ return &intel_goldmont;
+}
+
+/*
* Intel Skylake/Kabylake.
*
* The events that are not listed, because they are of little interest or
@@ -514,6 +553,9 @@ init_intel_generic(void)
case 0x5F: /* Goldmont (Denvertion) */
table->next = init_intel_goldmont();
break;
+ case 0x7A: /* Goldmont Plus (Gemini Lake) */
+ table->next = init_intel_goldmontplus();
+ break;
case 0x4E: /* Skylake */
case 0x5E: /* Skylake */
case 0x8E: /* Kabylake */
