Module Name: src Committed By: msaitoh Date: Fri Nov 30 08:19:45 UTC 2018
Modified Files: src/sys/dev/pci: pci_subr.c Log Message: The downstream port of PCIe switch is not a root port, so don't print root port related register. For example, Intel 63xxESB controller's downstream port device was printed by pcictl(8) with this bug: ----------------------------- PCI configuration registers: Common header: 0x00: 0x35108086 0x00100147 0x06040001 0x00010010 Vendor Name: Intel (0x8086) Device Name: 63xxESB PCI Express Downstream Port #1 (0x3510) (snip) Capability register at 0x44 <============= type: 0x10 (PCI Express) Capability register at 0x60 <============= 0x60 - 0x44 = 0x1c type: 0x05 (MSI) Capability register at 0x70 type: 0x01 (Power Management) Capability register at 0x80 type: 0x0d (Subsystem vendor ID) (snip) PCI Message Signaled Interrupt Message Control register: 0x0080 MSI Enabled: off Multiple Message Capable: no (1 vector) Multiple Message Enabled: off (1 vector) 64 Bit Address Capable: on Per-Vector Masking Capable: off Extended Message Data Capable: off Extended Message Data Enable: off Message Address (lower) register: 0x00000000 Message Address (upper) register: 0x00000000 Message Data register: 0x0000 (snip) PCI Express Capabilities Register (snip) Root Control Register: 0x7005 <=== 0x7005 is the first two byte SERR on Correctable Error Enable: on of the MSI capability structure SERR on Non-Fatal Error Enable: off SERR on Fatal Error Enable: on PME Interrupt Enable: off CRS Software Visibility Enable: off Root Capability Register: 0x0080 CRS Software Visibility: off Root Status Register: 0x00000000 PME Requester ID: 0x0000 PME was asserted: off another PME is pending: off Device-dependent header: 0x40: 0x00c00000 0x00616010 0x00000001 0x00005026 | |<- PCIe | 0x50: 0x0203f441 0x10010020 0x00000000 0x004803c0 | ->| 0x60: 0x00807005 0x00000000 0x00000000 0x00000000 |<- MSI ->| 0x70: 0xc8028001 0x00000100 0x00000000 0x00000000 |<- PM ->| 0x80: 0x0000000d 0x00000000 0x00000000 0x00000000 |<- subsystem ID | -------------------------------------- To generate a diff of this commit: cvs rdiff -u -r1.207 -r1.208 src/sys/dev/pci/pci_subr.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/dev/pci/pci_subr.c diff -u src/sys/dev/pci/pci_subr.c:1.207 src/sys/dev/pci/pci_subr.c:1.208 --- src/sys/dev/pci/pci_subr.c:1.207 Mon Nov 5 03:51:31 2018 +++ src/sys/dev/pci/pci_subr.c Fri Nov 30 08:19:45 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: pci_subr.c,v 1.207 2018/11/05 03:51:31 msaitoh Exp $ */ +/* $NetBSD: pci_subr.c,v 1.208 2018/11/30 08:19:45 msaitoh Exp $ */ /* * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. @@ -40,7 +40,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.207 2018/11/05 03:51:31 msaitoh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.208 2018/11/30 08:19:45 msaitoh Exp $"); #ifdef _KERNEL_OPT #include "opt_pci.h" @@ -1791,7 +1791,6 @@ pci_conf_print_pcie_cap(const pcireg_t * case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ printf("Downstream Port of PCI Express Switch\n"); check_slot = true; - check_rootport = true; break; case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ printf("PCI Express to PCI/PCI-X Bridge\n");