Module Name: src
Committed By: skrll
Date: Fri Dec 14 12:29:22 UTC 2018
Modified Files:
src/sys/arch/arm/nvidia: tegra210_car.c tegra210_carreg.h
tegra210_xusbpad.c tegra_ahcisata.c tegra_ahcisatareg.h tegra_var.h
Log Message:
Support SATA on TEGRA210
Thanks to jmcneill for help with this.
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/nvidia/tegra210_car.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/nvidia/tegra210_carreg.h
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/nvidia/tegra210_xusbpad.c
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/nvidia/tegra_ahcisata.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/nvidia/tegra_ahcisatareg.h
cvs rdiff -u -r1.44 -r1.45 src/sys/arch/arm/nvidia/tegra_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/nvidia/tegra210_car.c
diff -u src/sys/arch/arm/nvidia/tegra210_car.c:1.22 src/sys/arch/arm/nvidia/tegra210_car.c:1.23
--- src/sys/arch/arm/nvidia/tegra210_car.c:1.22 Wed Dec 12 09:55:34 2018
+++ src/sys/arch/arm/nvidia/tegra210_car.c Fri Dec 14 12:29:22 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_car.c,v 1.22 2018/12/12 09:55:34 skrll Exp $ */
+/* $NetBSD: tegra210_car.c,v 1.23 2018/12/14 12:29:22 skrll Exp $ */
/*-
* Copyright (c) 2015-2017 Jared McNeill <jmcne...@invisible.ca>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.22 2018/12/12 09:55:34 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_car.c,v 1.23 2018/12/14 12:29:22 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -457,6 +457,9 @@ static const char *mux_hda_p[] =
{ "PLL_P", "PLL_C2", "PLL_C", "PLL_C4_OUT0",
NULL, "PLL_C4_OUT1", "CLK_M", "PLL_C4_OUT2" };
+static const char *mux_sata_p[] =
+ { "PLL_P", NULL, "PLL_C", NULL, NULL, NULL, "CLK_M" };
+
static struct tegra_clk tegra210_car_clocks[] = {
CLK_FIXED("CLK_M", TEGRA210_REF_FREQ),
@@ -536,6 +539,13 @@ static struct tegra_clk tegra210_car_clo
CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC,
mux_hda_p),
+ CLK_MUX("MUX_SATA_OOB",
+ CAR_CLKSRC_SATA_OOB_REG , CAR_CLKSRC_SATA_OOB_SRC,
+ mux_sata_p),
+ CLK_MUX("MUX_SATA",
+ CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_SRC,
+ mux_sata_p),
+
CLK_DIV("DIV_UARTA", "MUX_UARTA",
CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV),
CLK_DIV("DIV_UARTB", "MUX_UARTB",
@@ -595,6 +605,11 @@ static struct tegra_clk tegra210_car_clo
CLK_DIV("DIV_HDA", "MUX_HDA",
CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV),
+ CLK_DIV("DIV_SATA_OOB", "MUX_SATA_OOB",
+ CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_DIV),
+ CLK_DIV("DIV_SATA", "MUX_SATA",
+ CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_DIV),
+
CLK_GATE_SIMPLE("PLL_U_OUT1", "DIV_PLL_U_OUT1",
CAR_PLLU_OUTA_REG, CAR_PLLU_OUTA_OUT1_CLKEN),
CLK_GATE_SIMPLE("PLL_U_OUT2", "DIV_PLL_U_OUT2",
@@ -636,6 +651,9 @@ static struct tegra_clk tegra210_car_clo
CLK_GATE_W("HDA2HDMI", "CLK_M", CAR_DEV_W_HDA2HDMICODEC),
CLK_GATE_V("HDA2CODEC_2X", "DIV_HDA2CODEC_2X", CAR_DEV_V_HDA2CODEC_2X),
CLK_GATE_V("HDA", "DIV_HDA", CAR_DEV_V_HDA),
+
+ CLK_GATE_V("SATA_OOB", "DIV_SATA_OOB", CAR_DEV_V_SATA_OOB),
+ CLK_GATE_V("SATA", "DIV_SATA", CAR_DEV_V_SATA),
};
struct tegra210_init_parent {
@@ -661,6 +679,8 @@ struct tegra210_init_parent {
{ "CML1", NULL, 0, 0 },
{ "AFI", NULL, 0, 1 },
{ "PCIE", NULL, 0, 1 },
+ { "SATA", "PLL_P", 104000000, 0 },
+ { "SATA_OOB", "PLL_P", 204000000, 0 },
};
struct tegra210_car_rst {
@@ -1681,3 +1701,35 @@ tegra210_car_xusbio_enable_hw_seq(void)
tegra_reg_set_clear(bst, bsh, CAR_XUSBIO_PLL_CFG0_REG,
CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE, 0);
}
+
+void
+tegra210_car_sata_enable_hw_control(void)
+{
+ device_t dev = device_find_by_driver_unit("tegra210car", 0);
+ KASSERT(dev != NULL);
+ struct tegra210_car_softc * const sc = device_private(dev);
+ bus_space_tag_t bst = sc->sc_bst;
+ bus_space_handle_t bsh = sc->sc_bsh;
+
+ tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
+ 0,
+ CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL);
+ tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
+ CAR_SATA_PLL_CFG0_SEQ_PADPLL_SLEEP_IDDQ |
+ CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET,
+ 0);
+}
+
+void
+tegra210_car_sata_enable_hw_seq(void)
+{
+ device_t dev = device_find_by_driver_unit("tegra210car", 0);
+ KASSERT(dev != NULL);
+ struct tegra210_car_softc * const sc = device_private(dev);
+ bus_space_tag_t bst = sc->sc_bst;
+ bus_space_handle_t bsh = sc->sc_bsh;
+
+ tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
+ CAR_SATA_PLL_CFG0_SEQ_ENABLE, 0);
+}
+
Index: src/sys/arch/arm/nvidia/tegra210_carreg.h
diff -u src/sys/arch/arm/nvidia/tegra210_carreg.h:1.8 src/sys/arch/arm/nvidia/tegra210_carreg.h:1.9
--- src/sys/arch/arm/nvidia/tegra210_carreg.h:1.8 Mon Sep 25 08:55:07 2017
+++ src/sys/arch/arm/nvidia/tegra210_carreg.h Fri Dec 14 12:29:22 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_carreg.h,v 1.8 2017/09/25 08:55:07 jmcneill Exp $ */
+/* $NetBSD: tegra210_carreg.h,v 1.9 2018/12/14 12:29:22 skrll Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -552,6 +552,7 @@
#define CAR_SATA_PLL_CFG0_SEQ_STATE __BITS(27,26)
#define CAR_SATA_PLL_CFG0_SEQ_START_STATE __BIT(25)
#define CAR_SATA_PLL_CFG0_SEQ_ENABLE __BIT(24)
+#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_SLEEP_IDDQ __BIT(13)
#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE __BIT(7)
#define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6)
#define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5)
Index: src/sys/arch/arm/nvidia/tegra210_xusbpad.c
diff -u src/sys/arch/arm/nvidia/tegra210_xusbpad.c:1.10 src/sys/arch/arm/nvidia/tegra210_xusbpad.c:1.11
--- src/sys/arch/arm/nvidia/tegra210_xusbpad.c:1.10 Wed Dec 12 09:55:34 2018
+++ src/sys/arch/arm/nvidia/tegra210_xusbpad.c Fri Dec 14 12:29:22 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra210_xusbpad.c,v 1.10 2018/12/12 09:55:34 skrll Exp $ */
+/* $NetBSD: tegra210_xusbpad.c,v 1.11 2018/12/14 12:29:22 skrll Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.10 2018/12/12 09:55:34 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra210_xusbpad.c,v 1.11 2018/12/14 12:29:22 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -63,7 +63,7 @@ __KERNEL_RCSID(0, "$NetBSD: tegra210_xus
#define XUSB_PADCTL_ELPG_PROGRAM_1_SSPn_ELPG_CLAMP_EN(n) __BIT((n) * 3 + 0)
#define XUSB_PADCTL_USB3_PAD_MUX_REG 0x28
-#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE __BIT(8)
+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE(n) __BIT(8 + (n))
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE(n) __BIT(1 + (n))
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADn_CTL_1_REG(n) (0x84 + (n) * 0x40)
@@ -98,17 +98,25 @@ __KERNEL_RCSID(0, "$NetBSD: tegra210_xus
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_NDIV __BITS(27,20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREQ_MDIV __BITS(17,16)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_LOCKDET_STATUS __BIT(15)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_MODE __BITS(9,8)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_BYPASS_ENABLE __BIT(7)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_FREERUN_ENABLE __BIT(6)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_PWR_OVRD __BIT(4)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_ENABLE __BIT(3)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_SLEEP __BITS(2,1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_1_IDDQ __BIT(0)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_REG 0x364
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_CTRL __BITS(27,4)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_RESET __BIT(3)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_OVRD __BIT(2)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_DONE __BIT(1)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_2_CAL_EN __BIT(0)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_3_REG 0x368
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_3_LOCKDET_CTRL __BITS(27,4)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_3_LOCKDET_RESET __BIT(0)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REG 0x36c
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TCLKOUT_EN __BIT(28)
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_CLKDIST_CTRL __BITS(23,20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_EN __BIT(15)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_TXCLKREF_SEL __BITS(13,12)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_4_REFCLKBUF_EN __BIT(8)
@@ -126,6 +134,44 @@ __KERNEL_RCSID(0, "$NetBSD: tegra210_xus
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_10_REG 0x384
#define XUSB_PADCTL_UPHY_PLL_P0_CTL_11_REG 0x388
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG 0x860
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_PSDIV __BITS(29,28)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_NDIV __BITS(27,20)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_MDIV __BITS(17,16)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_LOCKDET_STATUS __BIT(15)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_MODE __BITS(9,8)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_BYPASS_ENABLE __BIT(7)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREERUN_ENABLE __BIT(6)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_PWR_OVRD __BIT(4)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_ENABLE __BIT(3)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_SLEEP __BITS(2,1)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_1_IDDQ __BIT(0)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG 0x864
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_CTRL __BITS(27,4)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_RESET __BIT(3)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_OVRD __BIT(2)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_DONE __BIT(1)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_EN __BIT(0)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_3_REG 0x868
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_3_LOCKDET_CTRL __BITS(27,4)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_3_LOCKDET_RESET __BIT(0)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG 0x86c
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TCLKOUT_EN __BIT(28)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_CLKDIST_CTRL __BITS(23,20)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_EN __BIT(15)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_SEL __BITS(13,12)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLKBUF_EN __BIT(8)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLK_SEL __BITS(7,4)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_5_REG 0x870
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_5_DCO_CTRL __BITS(23,16)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_6_REG 0x874
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_7_REG 0x878
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG 0x87c
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_DONE __BIT(31)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_OVRD __BIT(15)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_CLK_EN __BIT(13)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_EN __BIT(12)
+
#define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_1_REG(n) (0xa60 + (n) * 0x40)
#define XUSB_PADCTL_UPHY_USB3_PADn_ECTL_2_TX_TERM_CTRL __BITS(19,18)
@@ -377,6 +423,153 @@ tegra210_xusbpad_lane_enable_usb2(struct
delay(50);
}
+
+static void
+tegra210_xusbpad_uphy_enable_sata(struct tegra210_xusbpad_softc *sc)
+{
+ uint32_t val;
+ int retry;
+
+ /* UPHY PLLs */
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,
+ __SHIFTIN(0x136, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_CTRL),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_CTRL);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_5_REG,
+ __SHIFTIN(0x2a, XUSB_PADCTL_UPHY_PLL_S0_CTL_5_DCO_CTRL),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_5_DCO_CTRL);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_1_PWR_OVRD, 0);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_OVRD, 0);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_OVRD, 0);
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG,
+ __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLK_SEL),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLK_SEL);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG,
+ __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_SEL),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_SEL);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_4_TXCLKREF_EN, 0);
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_MDIV),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_MDIV);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ __SHIFTIN(0x1e, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_NDIV),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_NDIV);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ __SHIFTIN(0, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_PSDIV),
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_1_FREQ_PSDIV);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_IDDQ);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_SLEEP);
+
+ delay(20);
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_4_REFCLKBUF_EN, 0);
+
+ /* Calibration */
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_EN, 0);
+ for (retry = 10000; retry > 0; retry--) {
+ delay(2);
+ val = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG);
+ if ((val & XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_DONE) != 0)
+ break;
+ }
+ if (retry == 0) {
+ aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (1)\n");
+ return;
+ }
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_EN);
+ for (retry = 10000; retry > 0; retry--) {
+ delay(2);
+ val = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG);
+ if ((val & XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_DONE) == 0)
+ break;
+ }
+ if (retry == 0) {
+ aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (2)\n");
+ return;
+ }
+
+ /* Enable the PLL */
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_1_ENABLE, 0);
+ for (retry = 10000; retry > 0; retry--) {
+ delay(2);
+ val = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG);
+ if ((val & XUSB_PADCTL_UPHY_PLL_S0_CTL_1_LOCKDET_STATUS) != 0)
+ break;
+ }
+ if (retry == 0) {
+ aprint_error_dev(sc->sc_dev, "timeout enabling UPHY PLL\n");
+ return;
+ }
+
+ /* RCAL */
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_EN, 0);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,
+ XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_CLK_EN, 0);
+ for (retry = 10000; retry > 0; retry--) {
+ delay(2);
+ val = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG);
+ if ((val & XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_DONE) != 0)
+ break;
+ }
+ if (retry == 0) {
+ aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (3)\n");
+ return;
+ }
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_EN);
+ for (retry = 10000; retry > 0; retry--) {
+ delay(2);
+ val = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG);
+ if ((val & XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_DONE) == 0)
+ break;
+ }
+ if (retry == 0) {
+ aprint_error_dev(sc->sc_dev, "timeout calibrating UPHY PLL (4)\n");
+ return;
+ }
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_CLK_EN);
+
+ tegra210_car_sata_enable_hw_control();
+
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_S0_CTL_1_PWR_OVRD);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_S0_CTL_2_CAL_OVRD);
+ SETCLR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_REG,
+ 0, XUSB_PADCTL_UPHY_PLL_S0_CTL_8_RCAL_OVRD);
+
+ delay(1);
+
+ tegra210_car_sata_enable_hw_seq();
+}
+
+static void
+tegra210_xusbpad_lane_enable_sata(struct tegra210_xusbpad_softc *sc, int index)
+{
+ tegra210_xusbpad_uphy_enable_sata(sc);
+
+ KASSERT(index == 0);
+ SETCLR4(sc, XUSB_PADCTL_USB3_PAD_MUX_REG,
+ XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE(index), 0);
+}
+
+
#define XUSBPAD_LANE(n, i, r, m, f, ef) \
{ \
.name = (n), \
@@ -426,8 +619,8 @@ static const struct tegra210_xusbpad_lan
XUSBPAD_LANE("pcie-6", 6, 0x28, __BITS(25,24), tegra210_xusbpad_pcie_func,
tegra210_xusbpad_lane_enable_pcie),
- XUSBPAD_LANE("sata-0", 0, 0x28, __BITS(31,30), tegra210_xusbpad_pcie_func,
- NULL),
+ XUSBPAD_LANE("sata-0", 0, XUSB_PADCTL_USB3_PAD_MUX_REG, __BITS(31,30),
+ tegra210_xusbpad_pcie_func, tegra210_xusbpad_lane_enable_sata),
};
#define XUSBPAD_PORT(n, i, r, m, im) \
Index: src/sys/arch/arm/nvidia/tegra_ahcisata.c
diff -u src/sys/arch/arm/nvidia/tegra_ahcisata.c:1.11 src/sys/arch/arm/nvidia/tegra_ahcisata.c:1.12
--- src/sys/arch/arm/nvidia/tegra_ahcisata.c:1.11 Tue Sep 19 20:46:12 2017
+++ src/sys/arch/arm/nvidia/tegra_ahcisata.c Fri Dec 14 12:29:22 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_ahcisata.c,v 1.11 2017/09/19 20:46:12 jmcneill Exp $ */
+/* $NetBSD: tegra_ahcisata.c,v 1.12 2018/12/14 12:29:22 skrll Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.11 2017/09/19 20:46:12 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_ahcisata.c,v 1.12 2018/12/14 12:29:22 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -56,6 +56,8 @@ struct tegra_ahcisata_softc {
bus_space_tag_t sc_bst;
bus_space_handle_t sc_bsh;
void *sc_ih;
+
+ int sc_phandle;
struct clk *sc_clk_sata;
struct clk *sc_clk_sata_oob;
struct clk *sc_clk_cml1;
@@ -65,9 +67,12 @@ struct tegra_ahcisata_softc {
struct fdtbus_reset *sc_rst_sata_cold;
struct tegra_gpio_pin *sc_pin_power;
+
+ struct tegra_ahcisata_data
+ *sc_tad;
};
-static const char * const tegra_ahcisata_supplies[] = {
+static const char * const tegra124_ahcisata_supplies[] = {
"hvdd-supply",
"vddio-supply",
"avdd-supply",
@@ -75,6 +80,35 @@ static const char * const tegra_ahcisata
"target-12v-supply"
};
+enum tegra_ahcisata_type {
+ TEGRA124,
+ TEGRA210
+};
+
+struct tegra_ahcisata_data {
+ enum tegra_ahcisata_type tad_type;
+ const char * const * tad_supplies;
+ size_t tad_nsupplies;
+};
+
+struct tegra_ahcisata_data tegra124_ahcisata_data = {
+ .tad_type = TEGRA124,
+ .tad_supplies = tegra124_ahcisata_supplies,
+ .tad_nsupplies = __arraycount(tegra124_ahcisata_supplies),
+};
+
+struct tegra_ahcisata_data tegra210_ahcisata_data = {
+ .tad_type = TEGRA210,
+};
+
+
+static const struct of_compat_data compat_data[] = {
+ { "nvidia,tegra124-ahci", (uintptr_t)&tegra124_ahcisata_data },
+ { "nvidia,tegra210-ahci", (uintptr_t)&tegra210_ahcisata_data },
+ { NULL },
+};
+
+
static void tegra_ahcisata_init(struct tegra_ahcisata_softc *);
static int tegra_ahcisata_init_clocks(struct tegra_ahcisata_softc *);
@@ -84,10 +118,9 @@ CFATTACH_DECL_NEW(tegra_ahcisata, sizeof
static int
tegra_ahcisata_match(device_t parent, cfdata_t cf, void *aux)
{
- const char * const compatible[] = { "nvidia,tegra124-ahci", NULL };
struct fdt_attach_args * const faa = aux;
- return of_match_compatible(faa->faa_phandle, compatible);
+ return of_match_compat_data(faa->faa_phandle, compat_data);
}
static void
@@ -120,16 +153,6 @@ tegra_ahcisata_attach(device_t parent, d
aprint_error(": couldn't get clock sata-oob\n");
return;
}
- sc->sc_clk_cml1 = fdtbus_clock_get(phandle, "cml1");
- if (sc->sc_clk_cml1 == NULL) {
- aprint_error(": couldn't get clock cml1\n");
- return;
- }
- sc->sc_clk_pll_e = fdtbus_clock_get(phandle, "pll_e");
- if (sc->sc_clk_pll_e == NULL) {
- aprint_error(": couldn't get clock pll_e\n");
- return;
- }
sc->sc_rst_sata = fdtbus_reset_get(phandle, "sata");
if (sc->sc_rst_sata == NULL) {
aprint_error(": couldn't get reset sata\n");
@@ -146,6 +169,21 @@ tegra_ahcisata_attach(device_t parent, d
return;
}
+ uintptr_t data = of_search_compatible(faa->faa_phandle, compat_data)->data;
+ sc->sc_tad = (struct tegra_ahcisata_data *)data;
+ if (sc->sc_tad->tad_type == TEGRA124) {
+ sc->sc_clk_cml1 = fdtbus_clock_get(phandle, "cml1");
+ if (sc->sc_clk_cml1 == NULL) {
+ aprint_error(": couldn't get clock cml1\n");
+ return;
+ }
+ sc->sc_clk_pll_e = fdtbus_clock_get(phandle, "pll_e");
+ if (sc->sc_clk_pll_e == NULL) {
+ aprint_error(": couldn't get clock pll_e\n");
+ return;
+ }
+ }
+
sc->sc_bst = faa->faa_bst;
error = bus_space_map(sc->sc_bst, sata_addr, sata_size, 0, &sc->sc_bsh);
if (error) {
@@ -153,6 +191,7 @@ tegra_ahcisata_attach(device_t parent, d
return;
}
+ sc->sc_phandle = faa->faa_phandle;
sc->sc.sc_atac.atac_dev = self;
sc->sc.sc_dmat = faa->faa_dmat;
sc->sc.sc_ahcit = faa->faa_bst;
@@ -168,8 +207,8 @@ tegra_ahcisata_attach(device_t parent, d
aprint_naive("\n");
aprint_normal(": SATA\n");
- for (n = 0; n < __arraycount(tegra_ahcisata_supplies); n++) {
- const char *supply = tegra_ahcisata_supplies[n];
+ for (n = 0; n < sc->sc_tad->tad_nsupplies; n++) {
+ const char *supply = sc->sc_tad->tad_supplies[n];
reg = fdtbus_regulator_acquire(phandle, supply);
if (reg == NULL) {
aprint_error_dev(self, "couldn't acquire %s\n", supply);
@@ -211,11 +250,6 @@ tegra_ahcisata_init(struct tegra_ahcisat
bus_space_tag_t bst = sc->sc_bst;
bus_space_handle_t bsh = sc->sc_bsh;
- const u_int gen1_tx_amp = 0x18;
- const u_int gen1_tx_peak = 0x04;
- const u_int gen2_tx_amp = 0x18;
- const u_int gen2_tx_peak = 0x0a;
-
/* Set RX idle detection source and disable RX idle detection interrupt */
tegra_reg_set_clear(bst, bsh, TEGRA_SATA_AUX_MISC_CNTL_1_REG,
TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL, 0);
@@ -234,34 +268,78 @@ tegra_ahcisata_init(struct tegra_ahcisat
tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG,
TEGRA_SATA_CONFIGURATION_EN_FPCI, 0);
- /* PHY config */
- bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG,
- TEGRA_T_SATA0_INDEX_CH1);
- tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_REG,
- __SHIFTIN(gen1_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP) |
- __SHIFTIN(gen1_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK),
- TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP |
- TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK);
- tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_REG,
- __SHIFTIN(gen2_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP) |
- __SHIFTIN(gen2_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK),
- TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP |
- TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK);
- bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL11_REG,
- __SHIFTIN(0x2800, TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ));
- bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL2_REG,
- __SHIFTIN(0x23, TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1));
- bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG, 0);
+ /* Electrical settings for better link stability */
+ bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL17_REG, 0x55010000);
+ bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL18_REG, 0x55010000);
+ bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL20_REG, 1);
+ bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL21_REG, 1);
+
+ tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_PHY_0_REG,
+ TEGRA_T_SATA0_CFG_PHY_0_MASK_SQUELCH,
+ TEGRA_T_SATA0_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD);
+
+ tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_NVOOB_REG,
+ __SHIFTIN(0x7, TEGRA_T_SATA0_NVOOB_COMMA_CNT) |
+ __SHIFTIN(0x3, TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH) |
+ __SHIFTIN(0x1, TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE),
+ TEGRA_T_SATA0_NVOOB_COMMA_CNT |
+ TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
+ TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
+
+ tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_2NVOOB_2_REG,
+ __SHIFTIN(0xc, TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW),
+ TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW);
+
+ if (sc->sc_tad->tad_type == TEGRA124) {
+ const u_int gen1_tx_amp = 0x18;
+ const u_int gen1_tx_peak = 0x04;
+ const u_int gen2_tx_amp = 0x18;
+ const u_int gen2_tx_peak = 0x0a;
+
+ /* PHY config */
+ bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG,
+ TEGRA_T_SATA0_INDEX_CH1);
+ tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_REG,
+ __SHIFTIN(gen1_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP) |
+ __SHIFTIN(gen1_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK),
+ TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP |
+ TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK);
+ tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_REG,
+ __SHIFTIN(gen2_tx_amp, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP) |
+ __SHIFTIN(gen2_tx_peak, TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK),
+ TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP |
+ TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK);
+ bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL11_REG,
+ __SHIFTIN(0x2800, TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ));
+ bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CHX_PHY_CTRL2_REG,
+ __SHIFTIN(0x23, TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1));
+ bus_space_write_4(bst, bsh, TEGRA_T_SATA0_INDEX_REG, 0);
+ }
/* Backdoor update the programming interface field and class code */
tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG,
TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN, 0);
+
bus_space_write_4(bst, bsh, TEGRA_T_SATA0_BKDOOR_CC_REG,
- __SHIFTIN(0x1016, TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE) |
+ __SHIFTIN(0x0106, TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE) |
__SHIFTIN(0x1, TEGRA_T_SATA0_BKDOOR_CC_PROG_IF));
tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_SATA_REG,
0, TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN);
+ tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_REG,
+ TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
+ TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM |
+ TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
+ TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP, 0);
+
+ tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG_PHY_1_REG,
+ TEGRA_T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
+ TEGRA_T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN, 0);
+
+ /* Enable IFPS device block */
+ tegra_reg_set_clear(bst, bsh, TEGRA_SATA_CONFIGURATION_REG,
+ 0, TEGRA_SATA_CONFIGURATION_CLKEN_OVERRIDE);
+
/* Enable access and bus mastering */
tegra_reg_set_clear(bst, bsh, TEGRA_T_SATA0_CFG1_REG,
TEGRA_T_SATA0_CFG1_SERR |
@@ -272,7 +350,9 @@ tegra_ahcisata_init(struct tegra_ahcisat
/* MMIO setup */
bus_space_write_4(bst, bsh, TEGRA_SATA_FPCI_BAR5_REG,
- __SHIFTIN(0x10000, TEGRA_SATA_FPCI_BAR_START));
+ __SHIFTIN(0x10000, TEGRA_SATA_FPCI_BAR_START) |
+ TEGRA_SATA_FPCI_BAR_ACCESS_TYPE);
+
bus_space_write_4(bst, bsh, TEGRA_T_SATA0_CFG9_REG,
__SHIFTIN(0x8000, TEGRA_T_SATA0_CFG9_BASE_ADDRESS));
@@ -314,7 +394,7 @@ tegra_ahcisata_init_clocks(struct tegra_
tegra_pmc_remove_clamping(PMC_PARTID_SAX);
delay(20);
- /* Un-gate clocks and enable CML clock for SATA */
+ /* Un-gate clocks for SATA */
error = clk_enable(sc->sc_clk_sata);
if (error) {
aprint_error_dev(self, "couldn't enable sata: %d\n", error);
@@ -325,12 +405,22 @@ tegra_ahcisata_init_clocks(struct tegra_
aprint_error_dev(self, "couldn't enable sata-oob: %d\n", error);
return error;
}
- error = clk_enable(sc->sc_clk_cml1);
- if (error) {
- aprint_error_dev(self, "couldn't enable cml1: %d\n", error);
- return error;
+
+ if (sc->sc_clk_cml1) {
+ /* Enable CML clock for SATA */
+ error = clk_enable(sc->sc_clk_cml1);
+ if (error) {
+ aprint_error_dev(self, "couldn't enable cml1: %d\n", error);
+ return error;
+ }
}
+ /* Enable PHYs */
+ struct fdtbus_phy *phy;
+ for (u_int n = 0; (phy = fdtbus_phy_get_index(sc->sc_phandle, n)) != NULL; n++)
+ if (fdtbus_phy_enable(phy, true) != 0)
+ aprint_error_dev(self, "failed to enable PHY #%d\n", n);
+
/* De-assert resets */
fdtbus_reset_deassert(sc->sc_rst_sata);
fdtbus_reset_deassert(sc->sc_rst_sata_cold);
Index: src/sys/arch/arm/nvidia/tegra_ahcisatareg.h
diff -u src/sys/arch/arm/nvidia/tegra_ahcisatareg.h:1.2 src/sys/arch/arm/nvidia/tegra_ahcisatareg.h:1.3
--- src/sys/arch/arm/nvidia/tegra_ahcisatareg.h:1.2 Thu Oct 15 09:04:35 2015
+++ src/sys/arch/arm/nvidia/tegra_ahcisatareg.h Fri Dec 14 12:29:22 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_ahcisatareg.h,v 1.2 2015/10/15 09:04:35 jmcneill Exp $ */
+/* $NetBSD: tegra_ahcisatareg.h,v 1.3 2018/12/14 12:29:22 skrll Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -35,6 +35,7 @@
#define TEGRA_SATA_FPCI_BAR_ACCESS_TYPE __BIT(0)
#define TEGRA_SATA_CONFIGURATION_REG 0x180
+#define TEGRA_SATA_CONFIGURATION_CLKEN_OVERRIDE __BIT(31)
#define TEGRA_SATA_CONFIGURATION_EN_FPCI __BIT(0)
#define TEGRA_SATA_INTR_MASK_REG 0x188
@@ -49,18 +50,41 @@
#define TEGRA_T_SATA0_CFG1_MEM_SPACE __BIT(1)
#define TEGRA_T_SATA0_CFG1_IO_SPACE __BIT(0)
+
#define TEGRA_T_SATA0_CFG9_REG 0x1024
-#define TEGRA_T_SATA0_CFG9_BASE_ADDRESS __BITS(31,13)
+#define TEGRA_T_SATA0_CFG9_BASE_ADDRESS __BITS(31,13)
#define TEGRA_T_SATA0_CFG9_SPACE_TYPE __BIT(0)
#define TEGRA_SATA_AUX_MISC_CNTL_1_REG 0x1108
#define TEGRA_SATA_AUX_MISC_CNTL_1_AUX_OR_CORE_IDLE_STATUS_SEL __BIT(18)
-#define TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT __BIT(13)
-#define TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR __BIT(7)
+#define TEGRA_SATA_AUX_MISC_CNTL_1_SDS_SUPPORT __BIT(13)
+#define TEGRA_SATA_AUX_MISC_CNTL_1_OOB_ON_POR __BIT(7)
#define TEGRA_SATA_AUX_RX_STAT_INT_REG 0x110c
#define TEGRA_SATA_AUX_RX_STAT_INT_SATA_RX_STAT_INT_DISABLE __BIT(2)
+#define TEGRA_T_SATA0_NVOOB_REG 0x1114
+#define TEGRA_T_SATA0_NVOOB_COMMA_CNT __BITS(30,28)
+#define TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH __BITS(27,26)
+#define TEGRA_T_SATA0_NVOOB_SQUELCH_FILTER_MODE __BITS(25,24)
+
+#define TEGRA_T_SATA0_CFG_PHY_0_REG 0x1120
+#define TEGRA_T_SATA0_CFG_PHY_0_MASK_SQUELCH __BIT(24)
+#define TEGRA_T_SATA0_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD __BIT(11)
+
+#define TEGRA_T_SATA0_CFG_PHY_1_REG 0x112c
+#define TEGRA_T_SATA0_CFG_PHY_1_PADS_IDDQ_EN __BIT(23)
+#define TEGRA_T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN __BIT(22)
+
+#define TEGRA_T_SATA0_CFG_2NVOOB_2_REG 0x1134
+#define TEGRA_T_SATA0_CFG_2NVOOB_2_COMWAKE_IDLE_CNT_LOW __BITS(26,18)
+
+#define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_REG 0x1300
+#define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SALP __BIT(26)
+#define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM __BIT(17)
+#define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP __BIT(14)
+#define TEGRA_T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP __BIT(13)
+
#define TEGRA_T_SATA0_BKDOOR_CC_REG 0x14a4
#define TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE __BITS(31,16)
#define TEGRA_T_SATA0_BKDOOR_CC_PROG_IF __BITS(15,8)
@@ -100,4 +124,10 @@
#define TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ __BITS(31,16)
#define TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN1_RX_EQ __BITS(15,0)
+#define TEGRA_T_SATA0_CHX_PHY_CTRL17_REG 0x16e8
+#define TEGRA_T_SATA0_CHX_PHY_CTRL18_REG 0x16ec
+#define TEGRA_T_SATA0_CHX_PHY_CTRL19_REG 0x16f0
+#define TEGRA_T_SATA0_CHX_PHY_CTRL20_REG 0x16f4
+#define TEGRA_T_SATA0_CHX_PHY_CTRL21_REG 0x16f8
+
#endif /* _ARM_TEGRA_AHCISATAREG_H */
Index: src/sys/arch/arm/nvidia/tegra_var.h
diff -u src/sys/arch/arm/nvidia/tegra_var.h:1.44 src/sys/arch/arm/nvidia/tegra_var.h:1.45
--- src/sys/arch/arm/nvidia/tegra_var.h:1.44 Thu Oct 18 09:01:53 2018
+++ src/sys/arch/arm/nvidia/tegra_var.h Fri Dec 14 12:29:22 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_var.h,v 1.44 2018/10/18 09:01:53 skrll Exp $ */
+/* $NetBSD: tegra_var.h,v 1.45 2018/12/14 12:29:22 skrll Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -55,6 +55,8 @@ void tegra_pmc_hdmi_enable(void);
void tegra210_car_xusbio_enable_hw_control(void);
void tegra210_car_xusbio_enable_hw_seq(void);
+void tegra210_car_sata_enable_hw_control(void);
+void tegra210_car_sata_enable_hw_seq(void);
uint32_t tegra_fuse_read(u_int);
