Module Name: src
Committed By: cliff
Date: Sun Jan 3 08:37:07 UTC 2010
Modified Files:
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_ehci.c rmixl_ohci.c
rmixlreg.h
Log Message:
- unconfuse bit defines for rmixl gpio RESET and RESET_CFG registers
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.1 -r1.1.2.2 src/sys/arch/mips/rmi/rmixl_ehci.c \
src/sys/arch/mips/rmi/rmixl_ohci.c
cvs rdiff -u -r1.1.2.5 -r1.1.2.6 src/sys/arch/mips/rmi/rmixlreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/rmi/rmixl_ehci.c
diff -u src/sys/arch/mips/rmi/rmixl_ehci.c:1.1.2.1 src/sys/arch/mips/rmi/rmixl_ehci.c:1.1.2.2
--- src/sys/arch/mips/rmi/rmixl_ehci.c:1.1.2.1 Mon Dec 14 07:22:37 2009
+++ src/sys/arch/mips/rmi/rmixl_ehci.c Sun Jan 3 08:37:07 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_ehci.c,v 1.1.2.1 2009/12/14 07:22:37 cliff Exp $ */
+/* $NetBSD: rmixl_ehci.c,v 1.1.2.2 2010/01/03 08:37:07 cliff Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2002, 2003 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rmixl_ehci.c,v 1.1.2.1 2009/12/14 07:22:37 cliff Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rmixl_ehci.c,v 1.1.2.2 2010/01/03 08:37:07 cliff Exp $");
#include "locators.h"
@@ -82,7 +82,7 @@
/* check state of IO_AD9 signal latched in GPIO Reset Config reg */
r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG);
- if ((r & RMIXL_GPIO_RESET_USB_DEV) == 0) {
+ if ((r & RMIXL_GPIO_RESET_CFG_USB_DEV) == 0) {
aprint_error_dev(self,
"IO_AD9 selects Device mode, abort Host attach\n");
return;
Index: src/sys/arch/mips/rmi/rmixl_ohci.c
diff -u src/sys/arch/mips/rmi/rmixl_ohci.c:1.1.2.1 src/sys/arch/mips/rmi/rmixl_ohci.c:1.1.2.2
--- src/sys/arch/mips/rmi/rmixl_ohci.c:1.1.2.1 Mon Dec 14 07:22:15 2009
+++ src/sys/arch/mips/rmi/rmixl_ohci.c Sun Jan 3 08:37:07 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_ohci.c,v 1.1.2.1 2009/12/14 07:22:15 cliff Exp $ */
+/* $NetBSD: rmixl_ohci.c,v 1.1.2.2 2010/01/03 08:37:07 cliff Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2002, 2003 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "locators.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rmixl_ohci.c,v 1.1.2.1 2009/12/14 07:22:15 cliff Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rmixl_ohci.c,v 1.1.2.2 2010/01/03 08:37:07 cliff Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -83,7 +83,7 @@
/* check state of IO_AD9 signal latched in GPIO Reset Config reg */
r = RMIXL_IOREG_READ(RMIXL_IO_DEV_GPIO + RMIXL_GPIO_RESET_CFG);
- if ((r & RMIXL_GPIO_RESET_USB_DEV) == 0) {
+ if ((r & RMIXL_GPIO_RESET_CFG_USB_DEV) == 0) {
aprint_error_dev(self,
"IO_AD9 selects Device mode, abort Host attach\n");
return;
Index: src/sys/arch/mips/rmi/rmixlreg.h
diff -u src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.5 src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.6
--- src/sys/arch/mips/rmi/rmixlreg.h:1.1.2.5 Mon Dec 14 07:19:16 2009
+++ src/sys/arch/mips/rmi/rmixlreg.h Sun Jan 3 08:37:07 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixlreg.h,v 1.1.2.5 2009/12/14 07:19:16 cliff Exp $ */
+/* $NetBSD: rmixlreg.h,v 1.1.2.6 2010/01/03 08:37:07 cliff Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -417,66 +417,73 @@
#define RMIXL_GPIO_RESET _RMIXL_OFFSET(0x8) /* XLS Soft Reset register */
/*
- * RMIXL_GPIO_RESET bits
+ * RMIXL_GPIO_RESET_CFG bits
*/
-#define RMIXL_GPIO_RESET_RESa __BITS(31,28)
-#define RMIXL_GPIO_RESET_PCIE_SRIO_SEL __BITS(27,26) /* PCIe or SRIO Select:
+#define RMIXL_GPIO_RESET_RESV __BITS(31,1)
+#define RMIXL_GPIO_RESET_RESET __BIT(0)
+
+
+/* GPIO System Control Registers */
+#define RMIXL_GPIO_RESET_CFG _RMIXL_OFFSET(0x15) /* Reset Configuration register */
+#define RMIXL_GPIO_THERMAL_CSR _RMIXL_OFFSET(0x16) /* Thermal Control/Status register */
+#define RMIXL_GPIO_THERMAL_SHFT _RMIXL_OFFSET(0x17) /* Thermal Shift register */
+#define RMIXL_GPIO_BIST_ALL_STS _RMIXL_OFFSET(0x18) /* BIST All Status register */
+#define RMIXL_GPIO_BIST_EACH_STS _RMIXL_OFFSET(0x19) /* BIST Each Status register */
+#define RMIXL_GPIO_SGMII_0_3_PHY_CTL _RMIXL_OFFSET(0x20) /* SGMII #0..3 PHY Control register */
+#define RMIXL_GPIO_AUI_0_PHY_CTL _RMIXL_OFFSET(0x20) /* AUI port#0 PHY Control register */
+#define RMIXL_GPIO_SGMII_4_7_PLL_CTL _RMIXL_OFFSET(0x21) /* SGMII #4..7 PLL Control register */
+#define RMIXL_GPIO_AUI_1_PLL_CTL _RMIXL_OFFSET(0x21) /* AUI port#1 PLL Control register */
+#define RMIXL_GPIO_SGMII_4_7_PHY_CTL _RMIXL_OFFSET(0x22) /* SGMII #4..7 PHY Control register */
+#define RMIXL_GPIO_AUI_1_PHY_CTL _RMIXL_OFFSET(0x22) /* AUI port#1 PHY Control register */
+#define RMIXL_GPIO_INT_MAP _RMIXL_OFFSET(0x25) /* Interrupt Map to PIC, 0=int14, 1=int30 */
+#define RMIXL_GPIO_EXT_INT _RMIXL_OFFSET(0x26) /* External Interrupt control register */
+#define RMIXL_GPIO_CPU_RST _RMIXL_OFFSET(0x28) /* CPU Reset control register */
+#define RMIXL_GPIO_LOW_PWR_DIS _RMIXL_OFFSET(0x29) /* Low Power Dissipation register */
+#define RMIXL_GPIO_RANDOM _RMIXL_OFFSET(0x2b) /* Low Power Dissipation register */
+#define RMIXL_GPIO_CPU_CLK_DIS _RMIXL_OFFSET(0x2d) /* CPU Clock Disable register */
+
+/*
+ * RMIXL_GPIO_RESET_CFG bits
+ */
+#define RMIXL_GPIO_RESET_CFG_RESa __BITS(31,28)
+#define RMIXL_GPIO_RESET_CFG_PCIE_SRIO_SEL __BITS(27,26) /* PCIe or SRIO Select:
* 00 = PCIe selected, SRIO not available
* 01 = SRIO selected, 1.25 Gbaud (1.0 Gbps)
* 10 = SRIO selected, 2.25 Gbaud (2.0 Gbps)
* 11 = SRIO selected, 3.125 Gbaud (2.5 Gbps)
*/
-#define RMIXL_GPIO_RESET_XAUI_PORT1_SEL __BIT(25) /* XAUI Port 1 Select:
+#define RMIXL_GPIO_RESET_CFG_XAUI_PORT1_SEL __BIT(25) /* XAUI Port 1 Select:
* 0 = Disabled - Port is SGMII ports 4-7
* 1 = Enabled - Port is 4-lane XAUI Port 1
*/
-#define RMIXL_GPIO_RESET_XAUI_PORT0_SEL __BIT(24) /* XAUI Port 0 Select:
+#define RMIXL_GPIO_RESET_CFG_XAUI_PORT0_SEL __BIT(24) /* XAUI Port 0 Select:
* 0 = Disabled - Port is SGMII ports 0-3
* 1 = Enabled - Port is 4-lane XAUI Port 0
*/
-#define RMIXL_GPIO_RESET_RESb __BIT(23)
-#define RMIXL_GPIO_RESET_USB_DEV __BIT(22) /* USB Device:
+#define RMIXL_GPIO_RESET_CFG_RESb __BIT(23)
+#define RMIXL_GPIO_RESET_CFG_USB_DEV __BIT(22) /* USB Device:
* 0 = Device Mode
* 1 = Host Mode
*/
-#define RMIXL_GPIO_RESET_PCIE_CFG __BITS(21,20) /* PCIe or SRIO configuration */
-#define RMIXL_GPIO_RESET_FLASH33_EN __BIT(19) /* Flash 33 MHZ Enable:
+#define RMIXL_GPIO_RESET_CFG_PCIE_CFG __BITS(21,20) /* PCIe or SRIO configuration */
+#define RMIXL_GPIO_RESET_CFG_FLASH33_EN __BIT(19) /* Flash 33 MHZ Enable:
* 0 = 66.67 MHz
* 1 = 33.33 MHz
*/
-#define RMIXL_GPIO_RESET_BIST_DIAG_EN __BIT(18) /* BIST Diagnostics enable */
-#define RMIXL_GPIO_RESET_BIST_RUN_EN __BIT(18) /* BIST Run enable */
-#define RMIXL_GPIO_RESET_NOOT_NAND __BIT(16) /* Enable boot from NAND Flash */
-#define RMIXL_GPIO_RESET_BOOT_PCMCIA __BIT(15) /* Enable boot from PCMCIA */
-#define RMIXL_GPIO_RESET_FLASH_CFG __BIT(14) /* Flash 32-bit Data Configuration:
+#define RMIXL_GPIO_RESET_CFG_BIST_DIAG_EN __BIT(18) /* BIST Diagnostics enable */
+#define RMIXL_GPIO_RESET_CFG_BIST_RUN_EN __BIT(18) /* BIST Run enable */
+#define RMIXL_GPIO_RESET_CFG_NOOT_NAND __BIT(16) /* Enable boot from NAND Flash */
+#define RMIXL_GPIO_RESET_CFG_BOOT_PCMCIA __BIT(15) /* Enable boot from PCMCIA */
+#define RMIXL_GPIO_RESET_CFG_FLASH_CFG __BIT(14) /* Flash 32-bit Data Configuration:
* 0 = 32-bit address / 16-bit data
* 1 = 32-bit address / 32-bit data
*/
-#define RMIXL_GPIO_RESET_PCMCIA_EN __BIT(13) /* PCMCIA Enable Status */
-#define RMIXL_GPIO_RESET_PARITY_EN __BIT(12) /* Parity Enable Status */
-#define RMIXL_GPIO_RESET_BIGEND __BIT(11) /* Big Endian Mode Enable Status */
-#define RMIXL_GPIO_RESET_PLL1_OUT_DIV __BITS(10,8) /* PLL1 (Core PLL) Output Divider */
-#define RMIXL_GPIO_RESET_PLL1_FB_DIV __BITS(7,0) /* PLL1 Feedback Divider */
-
+#define RMIXL_GPIO_RESET_CFG_PCMCIA_EN __BIT(13) /* PCMCIA Enable Status */
+#define RMIXL_GPIO_RESET_CFG_PARITY_EN __BIT(12) /* Parity Enable Status */
+#define RMIXL_GPIO_RESET_CFG_BIGEND __BIT(11) /* Big Endian Mode Enable Status */
+#define RMIXL_GPIO_RESET_CFG_PLL1_OUT_DIV __BITS(10,8) /* PLL1 (Core PLL) Output Divider */
+#define RMIXL_GPIO_RESET_CFG_PLL1_FB_DIV __BITS(7,0) /* PLL1 Feedback Divider */
-/* GPIO System Control Registers */
-#define RMIXL_GPIO_RESET_CFG _RMIXL_OFFSET(0x15) /* Reset Configuration register */
-#define RMIXL_GPIO_THERMAL_CSR _RMIXL_OFFSET(0x16) /* Thermal Control/Status register */
-#define RMIXL_GPIO_THERMAL_SHFT _RMIXL_OFFSET(0x17) /* Thermal Shift register */
-#define RMIXL_GPIO_BIST_ALL_STS _RMIXL_OFFSET(0x18) /* BIST All Status register */
-#define RMIXL_GPIO_BIST_EACH_STS _RMIXL_OFFSET(0x19) /* BIST Each Status register */
-#define RMIXL_GPIO_SGMII_0_3_PHY_CTL _RMIXL_OFFSET(0x20) /* SGMII #0..3 PHY Control register */
-#define RMIXL_GPIO_AUI_0_PHY_CTL _RMIXL_OFFSET(0x20) /* AUI port#0 PHY Control register */
-#define RMIXL_GPIO_SGMII_4_7_PLL_CTL _RMIXL_OFFSET(0x21) /* SGMII #4..7 PLL Control register */
-#define RMIXL_GPIO_AUI_1_PLL_CTL _RMIXL_OFFSET(0x21) /* AUI port#1 PLL Control register */
-#define RMIXL_GPIO_SGMII_4_7_PHY_CTL _RMIXL_OFFSET(0x22) /* SGMII #4..7 PHY Control register */
-#define RMIXL_GPIO_AUI_1_PHY_CTL _RMIXL_OFFSET(0x22) /* AUI port#1 PHY Control register */
-#define RMIXL_GPIO_INT_MAP _RMIXL_OFFSET(0x25) /* Interrupt Map to PIC, 0=int14, 1=int30 */
-#define RMIXL_GPIO_EXT_INT _RMIXL_OFFSET(0x26) /* External Interrupt control register */
-#define RMIXL_GPIO_CPU_RST _RMIXL_OFFSET(0x28) /* CPU Reset control register */
-#define RMIXL_GPIO_LOW_PWR_DIS _RMIXL_OFFSET(0x29) /* Low Power Dissipation register */
-#define RMIXL_GPIO_RANDOM _RMIXL_OFFSET(0x2b) /* Low Power Dissipation register */
-#define RMIXL_GPIO_CPU_CLK_DIS _RMIXL_OFFSET(0x2d) /* CPU Clock Disable register */
/*
* PCIE Interface Controller registers
