Module Name: src
Committed By: martin
Date: Thu Dec 27 12:17:19 UTC 2018
Modified Files:
src/sys/arch/x86/include [netbsd-8]: specialreg.h
src/sys/arch/x86/x86 [netbsd-8]: identcpu.c
Log Message:
Pull up following revision(s) (requested by maxv in ticket #1148):
sys/arch/x86/x86/identcpu.c: revision 1.81
sys/arch/x86/x86/identcpu.c: revision 1.82
sys/arch/x86/x86/identcpu.c: revision 1.84
sys/arch/x86/include/specialreg.h: revision 1.131
Declare the MSR_VIA_ACE values as macros, and use a consistent naming,
similar to the rest of the file.
I'm wondering if I'm not fixing a huge bug here. The ECX8 value we were
using was wrong: ECX8 is bit 1, not bit 0. Bit 0 is ALTINST, an alternate
ISA, which is now known to be backdoored.
So it looks like we were explicitly enabling the backdoor.
Not tested, because I don't have a VIA cpu.
-
Merge the VIA detection code into cpu_probe_c3.
-
Explicitly disable ALTINST on VIA, in case it isn't disabled by default
already (the 'VIA cpu backdoor').
To generate a diff of this commit:
cvs rdiff -u -r1.98.2.8 -r1.98.2.9 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.55.2.5 -r1.55.2.6 src/sys/arch/x86/x86/identcpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.98.2.8 src/sys/arch/x86/include/specialreg.h:1.98.2.9
--- src/sys/arch/x86/include/specialreg.h:1.98.2.8 Tue Dec 4 11:52:57 2018
+++ src/sys/arch/x86/include/specialreg.h Thu Dec 27 12:17:19 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.98.2.8 2018/12/04 11:52:57 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.98.2.9 2018/12/27 12:17:19 martin Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -871,7 +871,9 @@
#define MSR_VIA_RNG_NOISE_B 0x00000100
#define MSR_VIA_RNG_2NOISE 0x00000300
#define MSR_VIA_ACE 0x00001107
-#define MSR_VIA_ACE_ENABLE 0x10000000
+#define VIA_ACE_ALTINST 0x00000001
+#define VIA_ACE_ECX8 0x00000002
+#define VIA_ACE_ENABLE 0x10000000
/*
* VIA "Eden" MSRs
Index: src/sys/arch/x86/x86/identcpu.c
diff -u src/sys/arch/x86/x86/identcpu.c:1.55.2.5 src/sys/arch/x86/x86/identcpu.c:1.55.2.6
--- src/sys/arch/x86/x86/identcpu.c:1.55.2.5 Fri Jul 13 15:51:28 2018
+++ src/sys/arch/x86/x86/identcpu.c Thu Dec 27 12:17:19 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu.c,v 1.55.2.5 2018/07/13 15:51:28 martin Exp $ */
+/* $NetBSD: identcpu.c,v 1.55.2.6 2018/12/27 12:17:19 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.55.2.5 2018/07/13 15:51:28 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.55.2.6 2018/12/27 12:17:19 martin Exp $");
#include "opt_xen.h"
@@ -482,32 +482,13 @@ static void
cpu_probe_winchip(struct cpu_info *ci)
{
- if (cpu_vendor != CPUVENDOR_IDT)
+ if (cpu_vendor != CPUVENDOR_IDT ||
+ CPUID_TO_FAMILY(ci->ci_signature) != 5)
return;
- switch (CPUID_TO_FAMILY(ci->ci_signature)) {
- case 5:
- /* WinChip C6 */
- if (CPUID_TO_MODEL(ci->ci_signature) == 4)
- ci->ci_feat_val[0] &= ~CPUID_TSC;
- break;
- case 6:
- /*
- * VIA Eden ESP
- *
- * Quoting from page 3-4 of: "VIA Eden ESP Processor Datasheet"
- * http://www.via.com.tw/download/mainboards/6/14/Eden20v115.pdf
- *
- * 1. The CMPXCHG8B instruction is provided and always enabled,
- * however, it appears disabled in the corresponding CPUID
- * function bit 0 to avoid a bug in an early version of
- * Windows NT. However, this default can be changed via a
- * bit in the FCR MSR.
- */
- ci->ci_feat_val[0] |= CPUID_CX8;
- wrmsr(MSR_VIA_FCR, rdmsr(MSR_VIA_FCR) | 0x00000001);
- break;
- }
+ /* WinChip C6 */
+ if (CPUID_TO_MODEL(ci->ci_signature) == 4)
+ ci->ci_feat_val[0] &= ~CPUID_TSC;
}
static void
@@ -528,8 +509,25 @@ cpu_probe_c3(struct cpu_info *ci)
x86_cpuid(0x80000000, descs);
lfunc = descs[0];
+ if (family == 6) {
+ /*
+ * VIA Eden ESP.
+ *
+ * Quoting from page 3-4 of: "VIA Eden ESP Processor Datasheet"
+ * http://www.via.com.tw/download/mainboards/6/14/Eden20v115.pdf
+ *
+ * 1. The CMPXCHG8B instruction is provided and always enabled,
+ * however, it appears disabled in the corresponding CPUID
+ * function bit 0 to avoid a bug in an early version of
+ * Windows NT. However, this default can be changed via a
+ * bit in the FCR MSR.
+ */
+ ci->ci_feat_val[0] |= CPUID_CX8;
+ wrmsr(MSR_VIA_FCR, rdmsr(MSR_VIA_FCR) | VIA_ACE_ECX8);
+ }
+
if (family > 6 || model > 0x9 || (model == 0x9 && stepping >= 3)) {
- /* Nehemiah or Esther */
+ /* VIA Nehemiah or Esther. */
x86_cpuid(0xc0000000, descs);
lfunc = descs[0];
if (lfunc >= 0xc0000001) { /* has ACE, RNG */
@@ -598,12 +596,17 @@ cpu_probe_c3(struct cpu_info *ci)
if (ace_enable) {
msr = rdmsr(MSR_VIA_ACE);
- wrmsr(MSR_VIA_ACE, msr | MSR_VIA_ACE_ENABLE);
+ wrmsr(MSR_VIA_ACE, msr | VIA_ACE_ENABLE);
}
-
}
}
+ /* Explicitly disable unsafe ALTINST mode. */
+ if (ci->ci_feat_val[4] & CPUID_VIA_DO_ACE) {
+ msr = rdmsr(MSR_VIA_ACE);
+ wrmsr(MSR_VIA_ACE, msr & ~VIA_ACE_ALTINST);
+ }
+
/*
* Determine L1 cache/TLB info.
*/
