Module Name: src
Committed By: mrg
Date: Sun Jan 3 11:44:58 UTC 2010
Modified Files:
src/sys/arch/sparc/sparc: genassym.cf locore.s
Log Message:
use genassym generated names for struct intrhand elements and avoid magic.
To generate a diff of this commit:
cvs rdiff -u -r1.59 -r1.60 src/sys/arch/sparc/sparc/genassym.cf
cvs rdiff -u -r1.250 -r1.251 src/sys/arch/sparc/sparc/locore.s
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc/sparc/genassym.cf
diff -u src/sys/arch/sparc/sparc/genassym.cf:1.59 src/sys/arch/sparc/sparc/genassym.cf:1.60
--- src/sys/arch/sparc/sparc/genassym.cf:1.59 Thu Dec 10 05:10:03 2009
+++ src/sys/arch/sparc/sparc/genassym.cf Sun Jan 3 11:44:58 2010
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.59 2009/12/10 05:10:03 rmind Exp $
+# $NetBSD: genassym.cf,v 1.60 2010/01/03 11:44:58 mrg Exp $
#
# Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -130,6 +130,12 @@
define EV_COUNT offsetof(struct evcnt, ev_count)
define EV_STRUCTSIZE sizeof(struct evcnt)
+# interrupt handler fields
+define IH_FUN offsetof(struct intrhand, ih_fun)
+define IH_ARG offsetof(struct intrhand, ih_arg)
+define IH_NEXT offsetof(struct intrhand, ih_next)
+define IH_CLASSIPL offsetof(struct intrhand, ih_classipl)
+
# CPU info structure
define CPUINFO_STRUCTSIZE sizeof(struct cpu_info)
define CPUINFO_CPUNO offsetof(struct cpu_info, ci_cpuid)
Index: src/sys/arch/sparc/sparc/locore.s
diff -u src/sys/arch/sparc/sparc/locore.s:1.250 src/sys/arch/sparc/sparc/locore.s:1.251
--- src/sys/arch/sparc/sparc/locore.s:1.250 Sun Dec 20 03:53:46 2009
+++ src/sys/arch/sparc/sparc/locore.s Sun Jan 3 11:44:58 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.250 2009/12/20 03:53:46 mrg Exp $ */
+/* $NetBSD: locore.s,v 1.251 2010/01/03 11:44:58 mrg Exp $ */
/*
* Copyright (c) 1996 Paul Kranenburg
@@ -2557,18 +2557,18 @@
b 3f
st %fp, [%sp + CCFSZ + 16]
-1: ld [%l4 + 12], %o2 ! ih->ih_classipl
+1: ld [%l4 + IH_CLASSIPL], %o2 ! ih->ih_classipl
rd %psr, %o3 ! (bits already shifted to PIL field)
andn %o3, PSR_PIL, %o3 ! %o3 = psr & ~PSR_PIL
wr %o3, %o2, %psr ! splraise(ih->ih_classipl)
- ld [%l4], %o1
- ld [%l4 + 4], %o0
+ ld [%l4 + IH_FUN], %o1
+ ld [%l4 + IH_ARG], %o0
nop ! one more isns before touching ICC
tst %o0
bz,a 2f
add %sp, CCFSZ, %o0
2: jmpl %o1, %o7 ! (void)(*ih->ih_fun)(...)
- ld [%l4 + 8], %l4 ! and ih = ih->ih_next
+ ld [%l4 + IH_NEXT], %l4 ! and ih = ih->ih_next
3: tst %l4 ! while ih != NULL
bnz 1b
nop
@@ -2754,18 +2754,18 @@
b 3f
st %fp, [%sp + CCFSZ + 16]
-1: ld [%l4 + 12], %o2 ! ih->ih_classipl
+1: ld [%l4 + IH_CLASSIPL], %o2 ! ih->ih_classipl
rd %psr, %o3 ! (bits already shifted to PIL field)
andn %o3, PSR_PIL, %o3 ! %o3 = psr & ~PSR_PIL
wr %o3, %o2, %psr ! splraise(ih->ih_classipl)
- ld [%l4], %o1
- ld [%l4 + 4], %o0
+ ld [%l4 + IH_FUN], %o1
+ ld [%l4 + IH_ARG], %o0
nop ! one more isns before touching ICC
tst %o0
bz,a 2f
add %sp, CCFSZ, %o0
2: jmpl %o1, %o7 ! handled = (*ih->ih_fun)(...)
- ld [%l4 + 8], %l4 ! and ih = ih->ih_next
+ ld [%l4 + IH_NEXT], %l4 ! and ih = ih->ih_next
tst %o0
bnz 4f ! if (handled) break
nop
