Module Name: src
Committed By: jmcneill
Date: Thu Jan 3 15:12:00 UTC 2019
Modified Files:
src/sys/arch/arm/arm32: arm32_boot.c cpu.c
Log Message:
Read mpidr and cpuid from the secondary processor itself instead of the
boot processor. While here, add Cortex-A15 r4p0 to supported list.
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/arm/arm32/arm32_boot.c
cvs rdiff -u -r1.125 -r1.126 src/sys/arch/arm/arm32/cpu.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/arm32_boot.c
diff -u src/sys/arch/arm/arm32/arm32_boot.c:1.28 src/sys/arch/arm/arm32/arm32_boot.c:1.29
--- src/sys/arch/arm/arm32/arm32_boot.c:1.28 Thu Jan 3 10:26:41 2019
+++ src/sys/arch/arm/arm32/arm32_boot.c Thu Jan 3 15:12:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: arm32_boot.c,v 1.28 2019/01/03 10:26:41 skrll Exp $ */
+/* $NetBSD: arm32_boot.c,v 1.29 2019/01/03 15:12:00 jmcneill Exp $ */
/*
* Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved.
@@ -122,7 +122,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.28 2019/01/03 10:26:41 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.29 2019/01/03 15:12:00 jmcneill Exp $");
#include "opt_arm_debug.h"
#include "opt_cputypes.h"
@@ -350,6 +350,7 @@ cpu_hatch(struct cpu_info *ci, u_int cpu
VPRINTF("%s(%s): ", __func__, cpu_name(ci));
ci->ci_ctrl = armreg_sctlr_read();
uint32_t mpidr = armreg_mpidr_read();
+ ci->ci_mpidr = armreg_mpidr_read();
if (mpidr & MPIDR_MT) {
ci->ci_smt_id = mpidr & MPIDR_AFF0;
ci->ci_core_id = mpidr & MPIDR_AFF1;
@@ -359,6 +360,10 @@ cpu_hatch(struct cpu_info *ci, u_int cpu
ci->ci_package_id = mpidr & MPIDR_AFF1;
}
+ ci->ci_arm_cpuid = cpu_idnum();
+ ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK;
+ ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK;
+
/*
* Make sure we have the right vector page.
*/
Index: src/sys/arch/arm/arm32/cpu.c
diff -u src/sys/arch/arm/arm32/cpu.c:1.125 src/sys/arch/arm/arm32/cpu.c:1.126
--- src/sys/arch/arm/arm32/cpu.c:1.125 Thu Jan 3 10:26:41 2019
+++ src/sys/arch/arm/arm32/cpu.c Thu Jan 3 15:12:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.125 2019/01/03 10:26:41 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.126 2019/01/03 15:12:00 jmcneill Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.125 2019/01/03 10:26:41 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.126 2019/01/03 15:12:00 jmcneill Exp $");
#include <sys/param.h>
#include <sys/conf.h>
@@ -111,21 +111,8 @@ cpu_attach(device_t dv, cpuid_t id)
ci = kmem_zalloc(sizeof(*ci), KM_SLEEP);
ci->ci_cpl = IPL_HIGH;
ci->ci_cpuid = id;
- ci->ci_mpidr = armreg_mpidr_read();
- if (ci->ci_mpidr & MPIDR_MT) {
- ci->ci_smt_id = ci->ci_mpidr & MPIDR_AFF0;
- ci->ci_core_id = ci->ci_mpidr & MPIDR_AFF1;
- ci->ci_package_id = ci->ci_mpidr & MPIDR_AFF2;
- } else {
- ci->ci_core_id = ci->ci_mpidr & MPIDR_AFF0;
- ci->ci_package_id = ci->ci_mpidr & MPIDR_AFF1;
- }
ci->ci_data.cpu_cc_freq = cpu_info_store.ci_data.cpu_cc_freq;
- ci->ci_arm_cpuid = cpu_idnum();
- ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK;
- ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK;
-
ci->ci_undefsave[2] = cpu_info_store.ci_undefsave[2];
cpu_info[unit] = ci;
@@ -191,13 +178,8 @@ cpu_attach(device_t dv, cpuid_t id)
* and we are done if this is a secondary processor.
*/
if (unit != 0) {
-#if 1
aprint_naive("\n");
aprint_normal("\n");
-#else
- aprint_naive(": %s\n", cpu_getmodel());
- aprint_normal(": %s\n", cpu_getmodel());
-#endif
mi_cpu_attach(ci);
#ifdef ARM_MMU_EXTENDED
pmap_tlb_info_attach(&pmap_tlb0_info, ci);
@@ -526,6 +508,8 @@ const struct cpuidtab cpuids[] = {
pN_steppings, "7A" },
{ CPU_ID_CORTEXA15R3, CPU_CLASS_CORTEX, "Cortex-A15 r3",
pN_steppings, "7A" },
+ { CPU_ID_CORTEXA15R4, CPU_CLASS_CORTEX, "Cortex-A15 r4",
+ pN_steppings, "7A" },
{ CPU_ID_CORTEXA17R1, CPU_CLASS_CORTEX, "Cortex-A17 r1",
pN_steppings, "7A" },
{ CPU_ID_CORTEXA35R0, CPU_CLASS_CORTEX, "Cortex-A35 r0",
