Module Name: src
Committed By: maxv
Date: Fri Feb 1 06:49:59 UTC 2019
Modified Files:
src/lib/libnvmm: libnvmm_x86.c
src/tests/lib/libnvmm: h_mem_assist.c h_mem_assist_asm.S
Log Message:
Fix two issues:
* Uh I put the wrong masks in some GPRs, fuck.
* When the opsize of MOVZX is 4, we need to combine the zero-extend from
the instruction with the natural zero-extend of long mode.
Add two associated tests.
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/lib/libnvmm/libnvmm_x86.c
cvs rdiff -u -r1.3 -r1.4 src/tests/lib/libnvmm/h_mem_assist.c
cvs rdiff -u -r1.2 -r1.3 src/tests/lib/libnvmm/h_mem_assist_asm.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libnvmm/libnvmm_x86.c
diff -u src/lib/libnvmm/libnvmm_x86.c:1.17 src/lib/libnvmm/libnvmm_x86.c:1.18
--- src/lib/libnvmm/libnvmm_x86.c:1.17 Sun Jan 27 02:08:35 2019
+++ src/lib/libnvmm/libnvmm_x86.c Fri Feb 1 06:49:58 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: libnvmm_x86.c,v 1.17 2019/01/27 02:08:35 pgoyette Exp $ */
+/* $NetBSD: libnvmm_x86.c,v 1.18 2019/02/01 06:49:58 maxv Exp $ */
/*
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -1489,7 +1489,7 @@ static const struct x86_reg gpr_map[2][8
[4] = { -1, 0 },
[5] = { -1, 0 },
[6] = { -1, 0 },
- [7] = { NVMM_X64_GPR_RAX, 0x00000000FFFFFFFF }, /* RAX */
+ [7] = { NVMM_X64_GPR_RAX, 0xFFFFFFFFFFFFFFFF }, /* RAX */
},
[0b001] = {
[0] = { NVMM_X64_GPR_RCX, 0x00000000000000FF }, /* CL */
@@ -1499,7 +1499,7 @@ static const struct x86_reg gpr_map[2][8
[4] = { -1, 0 },
[5] = { -1, 0 },
[6] = { -1, 0 },
- [7] = { NVMM_X64_GPR_RCX, 0x00000000FFFFFFFF }, /* RCX */
+ [7] = { NVMM_X64_GPR_RCX, 0xFFFFFFFFFFFFFFFF }, /* RCX */
},
[0b010] = {
[0] = { NVMM_X64_GPR_RDX, 0x00000000000000FF }, /* DL */
@@ -1509,7 +1509,7 @@ static const struct x86_reg gpr_map[2][8
[4] = { -1, 0 },
[5] = { -1, 0 },
[6] = { -1, 0 },
- [7] = { NVMM_X64_GPR_RDX, 0x00000000FFFFFFFF }, /* RDX */
+ [7] = { NVMM_X64_GPR_RDX, 0xFFFFFFFFFFFFFFFF }, /* RDX */
},
[0b011] = {
[0] = { NVMM_X64_GPR_RBX, 0x00000000000000FF }, /* BL */
@@ -1519,7 +1519,7 @@ static const struct x86_reg gpr_map[2][8
[4] = { -1, 0 },
[5] = { -1, 0 },
[6] = { -1, 0 },
- [7] = { NVMM_X64_GPR_RBX, 0x00000000FFFFFFFF }, /* RBX */
+ [7] = { NVMM_X64_GPR_RBX, 0xFFFFFFFFFFFFFFFF }, /* RBX */
},
[0b100] = {
[0] = { -1, 0 }, /* SPECIAL */
@@ -1572,7 +1572,7 @@ static const struct x86_reg gpr_map[2][8
[4] = { -1, 0 },
[5] = { -1, 0 },
[6] = { -1, 0 },
- [7] = { NVMM_X64_GPR_R8, 0x00000000FFFFFFFF }, /* R8 */
+ [7] = { NVMM_X64_GPR_R8, 0xFFFFFFFFFFFFFFFF }, /* R8 */
},
[0b001] = {
[0] = { NVMM_X64_GPR_R9, 0x00000000000000FF }, /* R9B */
@@ -1582,7 +1582,7 @@ static const struct x86_reg gpr_map[2][8
[4] = { -1, 0 },
[5] = { -1, 0 },
[6] = { -1, 0 },
- [7] = { NVMM_X64_GPR_R9, 0x00000000FFFFFFFF }, /* R9 */
+ [7] = { NVMM_X64_GPR_R9, 0xFFFFFFFFFFFFFFFF }, /* R9 */
},
[0b010] = {
[0] = { NVMM_X64_GPR_R10, 0x00000000000000FF }, /* R10B */
@@ -1592,7 +1592,7 @@ static const struct x86_reg gpr_map[2][8
[4] = { -1, 0 },
[5] = { -1, 0 },
[6] = { -1, 0 },
- [7] = { NVMM_X64_GPR_R10, 0x00000000FFFFFFFF }, /* R10 */
+ [7] = { NVMM_X64_GPR_R10, 0xFFFFFFFFFFFFFFFF }, /* R10 */
},
[0b011] = {
[0] = { NVMM_X64_GPR_R11, 0x00000000000000FF }, /* R11B */
@@ -1602,7 +1602,7 @@ static const struct x86_reg gpr_map[2][8
[4] = { -1, 0 },
[5] = { -1, 0 },
[6] = { -1, 0 },
- [7] = { NVMM_X64_GPR_R11, 0x00000000FFFFFFFF }, /* R11 */
+ [7] = { NVMM_X64_GPR_R11, 0xFFFFFFFFFFFFFFFF }, /* R11 */
},
[0b100] = {
[0] = { NVMM_X64_GPR_R12, 0x00000000000000FF }, /* R12B */
@@ -1612,7 +1612,7 @@ static const struct x86_reg gpr_map[2][8
[4] = { -1, 0 },
[5] = { -1, 0 },
[6] = { -1, 0 },
- [7] = { NVMM_X64_GPR_R12, 0x00000000FFFFFFFF }, /* R12 */
+ [7] = { NVMM_X64_GPR_R12, 0xFFFFFFFFFFFFFFFF }, /* R12 */
},
[0b101] = {
[0] = { NVMM_X64_GPR_R13, 0x00000000000000FF }, /* R13B */
@@ -1622,7 +1622,7 @@ static const struct x86_reg gpr_map[2][8
[4] = { -1, 0 },
[5] = { -1, 0 },
[6] = { -1, 0 },
- [7] = { NVMM_X64_GPR_R13, 0x00000000FFFFFFFF }, /* R13 */
+ [7] = { NVMM_X64_GPR_R13, 0xFFFFFFFFFFFFFFFF }, /* R13 */
},
[0b110] = {
[0] = { NVMM_X64_GPR_R14, 0x00000000000000FF }, /* R14B */
@@ -1632,7 +1632,7 @@ static const struct x86_reg gpr_map[2][8
[4] = { -1, 0 },
[5] = { -1, 0 },
[6] = { -1, 0 },
- [7] = { NVMM_X64_GPR_R14, 0x00000000FFFFFFFF }, /* R14 */
+ [7] = { NVMM_X64_GPR_R14, 0xFFFFFFFFFFFFFFFF }, /* R14 */
},
[0b111] = {
[0] = { NVMM_X64_GPR_R15, 0x00000000000000FF }, /* R15B */
@@ -1642,7 +1642,7 @@ static const struct x86_reg gpr_map[2][8
[4] = { -1, 0 },
[5] = { -1, 0 },
[6] = { -1, 0 },
- [7] = { NVMM_X64_GPR_R15, 0x00000000FFFFFFFF }, /* R15 */
+ [7] = { NVMM_X64_GPR_R15, 0xFFFFFFFFFFFFFFFF }, /* R15 */
},
}
};
@@ -2267,12 +2267,17 @@ node_secondary_opcode(struct x86_decode_
instr->operand_size = get_operand_size(fsm, instr);
instr->address_size = get_address_size(fsm, instr);
+ if (fsm->is64bit && (instr->operand_size == 4)) {
+ /* Zero-extend to 64 bits. */
+ instr->zeroextend_mask = ~size_to_mask(4);
+ }
+
if (opcode->flags & FLAG_ze) {
/*
* Compute the mask for zero-extend. Update the operand size,
* we move fewer bytes.
*/
- instr->zeroextend_mask = size_to_mask(instr->operand_size);
+ instr->zeroextend_mask |= size_to_mask(instr->operand_size);
instr->zeroextend_mask &= ~size_to_mask(opcode->defsize);
instr->operand_size = opcode->defsize;
}
Index: src/tests/lib/libnvmm/h_mem_assist.c
diff -u src/tests/lib/libnvmm/h_mem_assist.c:1.3 src/tests/lib/libnvmm/h_mem_assist.c:1.4
--- src/tests/lib/libnvmm/h_mem_assist.c:1.3 Fri Feb 1 05:32:08 2019
+++ src/tests/lib/libnvmm/h_mem_assist.c Fri Feb 1 06:49:58 2019
@@ -290,6 +290,8 @@ extern uint8_t test6_begin, test6_end;
extern uint8_t test7_begin, test7_end;
extern uint8_t test8_begin, test8_end;
extern uint8_t test9_begin, test9_end;
+extern uint8_t test10_begin, test10_end;
+extern uint8_t test11_begin, test11_end;
static const struct test tests[] = {
{ "test1 - MOV", &test1_begin, &test1_end, 0x3004 },
@@ -301,6 +303,8 @@ static const struct test tests[] = {
{ "test7 - STOS", &test7_begin, &test7_end, 0x00123456 },
{ "test8 - LODS", &test8_begin, &test8_end, 0x12345678 },
{ "test9 - MOVS", &test9_begin, &test9_end, 0x12345678 },
+ { "test10 - MOVZXB", &test10_begin, &test10_end, 0x00000078 },
+ { "test11 - MOVZXW", &test11_begin, &test11_end, 0x00005678 },
{ NULL, NULL, NULL, -1 }
};
Index: src/tests/lib/libnvmm/h_mem_assist_asm.S
diff -u src/tests/lib/libnvmm/h_mem_assist_asm.S:1.2 src/tests/lib/libnvmm/h_mem_assist_asm.S:1.3
--- src/tests/lib/libnvmm/h_mem_assist_asm.S:1.2 Thu Dec 27 07:22:31 2018
+++ src/tests/lib/libnvmm/h_mem_assist_asm.S Fri Feb 1 06:49:58 2019
@@ -36,6 +36,8 @@
.globl test7_begin, test7_end
.globl test8_begin, test8_end
.globl test9_begin, test9_end
+ .globl test10_begin, test10_end
+ .globl test11_begin, test11_end
.text
.code64
@@ -177,3 +179,26 @@ test9_begin:
TEST_END
test9_end:
+ .align 64
+test10_begin:
+ movq $0x1000,%rax
+ movq $0x12345678,(%rax)
+
+ movq $0xFFFFFFFFFFFFFFFF,%rbx
+ movzxb (%rax),%ebx
+ movq %rbx,(%rax)
+
+ TEST_END
+test10_end:
+
+ .align 64
+test11_begin:
+ movq $0x1000,%rax
+ movq $0x12345678,(%rax)
+
+ movq $0xFFFFFFFFFFFFFFFF,%rbx
+ movzxw (%rax),%rbx
+ movq %rbx,(%rax)
+
+ TEST_END
+test11_end:
