Module Name: src
Committed By: maxv
Date: Sat Feb 16 12:05:30 UTC 2019
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/dev/nvmm/x86: nvmm_x86_vmx.c
Log Message:
Handle MSR_MISC_ENABLE on NVMM-Intel (Intel-specific).
To generate a diff of this commit:
cvs rdiff -u -r1.140 -r1.141 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.4 -r1.5 src/sys/dev/nvmm/x86/nvmm_x86_vmx.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.140 src/sys/arch/x86/include/specialreg.h:1.141
--- src/sys/arch/x86/include/specialreg.h:1.140 Mon Feb 11 14:59:32 2019
+++ src/sys/arch/x86/include/specialreg.h Sat Feb 16 12:05:30 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.140 2019/02/11 14:59:32 cherry Exp $ */
+/* $NetBSD: specialreg.h,v 1.141 2019/02/16 12:05:30 maxv Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -768,7 +768,16 @@
#define MSR_THERM_STATUS 0x19c
#define MSR_THERM2_CTL 0x19d /* Pentium M */
#define MSR_MISC_ENABLE 0x1a0
-#define IA32_MISC_MWAIT_EN 0x40000
+#define IA32_MISC_FAST_STR_EN __BIT(0)
+#define IA32_MISC_ATCC_EN __BIT(3)
+#define IA32_MISC_PERFMON_EN __BIT(7)
+#define IA32_MISC_BTS_UNAVAIL __BIT(11)
+#define IA32_MISC_PEBS_UNAVAIL __BIT(12)
+#define IA32_MISC_EISST_EN __BIT(16)
+#define IA32_MISC_MWAIT_EN __BIT(18)
+#define IA32_MISC_LIMIT_CPUID __BIT(22)
+#define IA32_MISC_XTPR_DIS __BIT(23)
+#define IA32_MISC_XD_DIS __BIT(34)
#define MSR_TEMPERATURE_TARGET 0x1a2
#define MSR_DEBUGCTLMSR 0x1d9
#define MSR_LASTBRANCHFROMIP 0x1db
Index: src/sys/dev/nvmm/x86/nvmm_x86_vmx.c
diff -u src/sys/dev/nvmm/x86/nvmm_x86_vmx.c:1.4 src/sys/dev/nvmm/x86/nvmm_x86_vmx.c:1.5
--- src/sys/dev/nvmm/x86/nvmm_x86_vmx.c:1.4 Fri Feb 15 13:17:05 2019
+++ src/sys/dev/nvmm/x86/nvmm_x86_vmx.c Sat Feb 16 12:05:30 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86_vmx.c,v 1.4 2019/02/15 13:17:05 maxv Exp $ */
+/* $NetBSD: nvmm_x86_vmx.c,v 1.5 2019/02/16 12:05:30 maxv Exp $ */
/*
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_vmx.c,v 1.4 2019/02/15 13:17:05 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_vmx.c,v 1.5 2019/02/16 12:05:30 maxv Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -665,6 +665,7 @@ struct vmx_cpudata {
/* Guest state */
struct msr_entry *gmsr;
paddr_t gmsr_pa;
+ uint64_t gmsr_misc_enable;
uint64_t gcr2;
uint64_t gcr8;
uint64_t gxcr0;
@@ -1361,6 +1362,12 @@ vmx_inkernel_handle_msr(struct nvmm_mach
cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32);
goto handled;
}
+ if (exit->u.msr.msr == MSR_MISC_ENABLE) {
+ val = cpudata->gmsr_misc_enable;
+ cpudata->gprs[NVMM_X64_GPR_RAX] = (val & 0xFFFFFFFF);
+ cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32);
+ goto handled;
+ }
for (i = 0; i < __arraycount(msr_ignore_list); i++) {
if (msr_ignore_list[i] != exit->u.msr.msr)
continue;
@@ -1381,6 +1388,10 @@ vmx_inkernel_handle_msr(struct nvmm_mach
vmx_vmwrite(VMCS_GUEST_IA32_PAT, exit->u.msr.val);
goto handled;
}
+ if (exit->u.msr.msr == MSR_MISC_ENABLE) {
+ /* Don't care. */
+ goto handled;
+ }
for (i = 0; i < __arraycount(msr_ignore_list); i++) {
if (msr_ignore_list[i] != exit->u.msr.msr)
continue;
@@ -2007,6 +2018,13 @@ vmx_vcpu_init(struct nvmm_machine *mach,
mach->vm->vm_map.pmap->pm_pdirpa[0];
vmx_vmwrite(VMCS_EPTP, eptp);
+ /* Init IA32_MISC_ENABLE. */
+ cpudata->gmsr_misc_enable = rdmsr(MSR_MISC_ENABLE);
+ cpudata->gmsr_misc_enable &=
+ ~(IA32_MISC_PERFMON_EN|IA32_MISC_EISST_EN|IA32_MISC_MWAIT_EN);
+ cpudata->gmsr_misc_enable |=
+ (IA32_MISC_BTS_UNAVAIL|IA32_MISC_PEBS_UNAVAIL);
+
/* Must always be set. */
vmx_vmwrite(VMCS_GUEST_CR4, CR4_VMXE);
vmx_vmwrite(VMCS_GUEST_CR0, CR0_NE);
