Module Name: src
Committed By: msaitoh
Date: Fri Mar 1 09:26:00 UTC 2019
Modified Files:
src/sys/arch/arm/imx: imx6_pcie.c
src/sys/arch/arm/xscale: i80312.c i80312_pci.c
src/sys/arch/evbarm/iq80310: iq80310_machdep.c iq80310_pci.c
src/sys/arch/macppc/pci: pci_machdep.c
src/sys/arch/sparc/sparc: pci_fixup.c
src/sys/arch/sparc64/sparc64: rbus_machdep.c
src/sys/arch/x86/pci: pci_bus_fixup.c pci_ranges.c
src/sys/dev/acpi: acpi_pci.c
src/sys/dev/cardbus: rbus_ppb.c
src/sys/dev/pci: btvmeii.c pccbb.c pci_subr.c pciconf.c pcireg.h ppb.c
ppbreg.h
Log Message:
- Almost all ppbreg.h's definitions are also in pcireg.h. Remove duplicated
definitions from ppbreg.h and move some definitions from ppbreg.h to
pcireg.h.
- Change fast back-to-back "capable" to "enable" in pci_subr.c.
- Print Primary Discard Timer, Secondary Discard Timer, Discard Timer Status
and Discard Timer SERR# Enable bit in pci_subr.c.
- PCI_BRIDGE_PREFETCHBASE32_REG and PCI_BRIDGE_PREFETCHLIMIT32_REG are
"upper" 32bit registers, rename to *UP32_REG to avoid confusion.
- Use macro.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/imx/imx6_pcie.c
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/xscale/i80312.c
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/xscale/i80312_pci.c
cvs rdiff -u -r1.89 -r1.90 src/sys/arch/evbarm/iq80310/iq80310_machdep.c
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/evbarm/iq80310/iq80310_pci.c
cvs rdiff -u -r1.41 -r1.42 src/sys/arch/macppc/pci/pci_machdep.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/sparc/sparc/pci_fixup.c
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/sparc64/sparc64/rbus_machdep.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/x86/pci/pci_bus_fixup.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/x86/pci/pci_ranges.c
cvs rdiff -u -r1.25 -r1.26 src/sys/dev/acpi/acpi_pci.c
cvs rdiff -u -r1.45 -r1.46 src/sys/dev/cardbus/rbus_ppb.c
cvs rdiff -u -r1.22 -r1.23 src/sys/dev/pci/btvmeii.c
cvs rdiff -u -r1.213 -r1.214 src/sys/dev/pci/pccbb.c
cvs rdiff -u -r1.211 -r1.212 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.40 -r1.41 src/sys/dev/pci/pciconf.c
cvs rdiff -u -r1.146 -r1.147 src/sys/dev/pci/pcireg.h
cvs rdiff -u -r1.67 -r1.68 src/sys/dev/pci/ppb.c
cvs rdiff -u -r1.9 -r1.10 src/sys/dev/pci/ppbreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/imx/imx6_pcie.c
diff -u src/sys/arch/arm/imx/imx6_pcie.c:1.7 src/sys/arch/arm/imx/imx6_pcie.c:1.8
--- src/sys/arch/arm/imx/imx6_pcie.c:1.7 Sun Dec 16 16:45:11 2018
+++ src/sys/arch/arm/imx/imx6_pcie.c Fri Mar 1 09:25:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_pcie.c,v 1.7 2018/12/16 16:45:11 skrll Exp $ */
+/* $NetBSD: imx6_pcie.c,v 1.8 2019/03/01 09:25:59 msaitoh Exp $ */
/*
* Copyright (c) 2016 Genetec Corporation. All rights reserved.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.7 2018/12/16 16:45:11 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.8 2019/03/01 09:25:59 msaitoh Exp $");
#include "opt_pci.h"
@@ -688,12 +688,11 @@ imx6pcie_setup(struct imx6pcie_softc * c
/* Bus number */
v = PCIE_READ(sc, PCI_BRIDGE_BUS_REG);
- v &= ~(PCI_BRIDGE_BUS_EACH_MASK << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT |
- PCI_BRIDGE_BUS_EACH_MASK << PCI_BRIDGE_BUS_SECONDARY_SHIFT |
- PCI_BRIDGE_BUS_EACH_MASK << PCI_BRIDGE_BUS_PRIMARY_SHIFT);
- v |= PCI_BRIDGE_BUS_SUBORDINATE(1);
- v |= PCI_BRIDGE_BUS_SECONDARY(1);
- v |= PCI_BRIDGE_BUS_PRIMARY(0);
+ v &= ~(PCI_BRIDGE_BUS_SUBORDINATE | PCI_BRIDGE_BUS_SECONDARY |
+ PCI_BRIDGE_BUS_PRIMARY);
+ v |= PCI_BRIDGE_BUS_NUM_SUBORDINATE(1);
+ v |= PCI_BRIDGE_BUS_NUM_SECONDARY(1);
+ v |= PCI_BRIDGE_BUS_NUM_PRIMARY(0);
PCIE_WRITE(sc, PCI_BRIDGE_BUS_REG, v);
/* Command register */
Index: src/sys/arch/arm/xscale/i80312.c
diff -u src/sys/arch/arm/xscale/i80312.c:1.23 src/sys/arch/arm/xscale/i80312.c:1.24
--- src/sys/arch/arm/xscale/i80312.c:1.23 Sun Oct 14 14:20:57 2012
+++ src/sys/arch/arm/xscale/i80312.c Fri Mar 1 09:25:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i80312.c,v 1.23 2012/10/14 14:20:57 msaitoh Exp $ */
+/* $NetBSD: i80312.c,v 1.24 2019/03/01 09:25:59 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i80312.c,v 1.23 2012/10/14 14:20:57 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i80312.c,v 1.24 2019/03/01 09:25:59 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -268,10 +268,10 @@ i80312_attach(struct i80312_softc *sc)
*/
if (sc->sc_is_host) {
bus_space_write_4(sc->sc_st, sc->sc_ppb_sh,
- PPB_REG_BUSINFO,
- (0 << PCI_BRIDGE_BUS_PRIMARY_SHIFT) |
- (1 << PCI_BRIDGE_BUS_SECONDARY_SHIFT) |
- (1 << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT));
+ PCI_BRIDGE_BUS_REG,
+ __SHIFTIN(0, PCI_BRIDGE_BUS_PRIMARY) |
+ __SHIFTIN(1, PCI_BRIDGE_BUS_SECONDARY) |
+ __SHIFTIN(1, PCI_BRIDGE_BUS_SUBORDINATE));
}
/* Initialize the bus space tags. */
@@ -306,13 +306,13 @@ i80312_attach(struct i80312_softc *sc)
* is the only bus on which we can have a private device
* space.
*/
- preg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
+ preg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG);
pba.pba_iot = &sc->sc_pci_iot;
pba.pba_memt = &sc->sc_pci_memt;
pba.pba_dmat = &sc->sc_pci_dmat;
pba.pba_dmat64 = NULL;
pba.pba_pc = &sc->sc_pci_chipset;
- pba.pba_bus = PPB_BUSINFO_SECONDARY(preg);
+ pba.pba_bus = PCI_BRIDGE_BUS_NUM_SECONDARY(preg);
pba.pba_bridgetag = NULL;
pba.pba_intrswiz = 3;
pba.pba_intrtag = 0;
Index: src/sys/arch/arm/xscale/i80312_pci.c
diff -u src/sys/arch/arm/xscale/i80312_pci.c:1.16 src/sys/arch/arm/xscale/i80312_pci.c:1.17
--- src/sys/arch/arm/xscale/i80312_pci.c:1.16 Fri Oct 2 05:22:50 2015
+++ src/sys/arch/arm/xscale/i80312_pci.c Fri Mar 1 09:25:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: i80312_pci.c,v 1.16 2015/10/02 05:22:50 msaitoh Exp $ */
+/* $NetBSD: i80312_pci.c,v 1.17 2019/03/01 09:25:59 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i80312_pci.c,v 1.16 2015/10/02 05:22:50 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i80312_pci.c,v 1.17 2019/03/01 09:25:59 msaitoh Exp $");
#include "opt_pci.h"
#include "pci.h"
@@ -106,9 +106,9 @@ i80312_pci_init(pci_chipset_tag_t pc, vo
* the Secondary bus.
*/
- binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
- /* pbus = PPB_BUSINFO_PRIMARY(binfo); */
- sbus = PPB_BUSINFO_SECONDARY(binfo);
+ binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG);
+ /* pbus = PCI_BRIDGE_BUS_NUM_PRIMARY(binfo); */
+ sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(binfo);
ioext = extent_create("pciio", sc->sc_sioout_base,
sc->sc_sioout_base + sc->sc_sioout_size - 1,
@@ -185,9 +185,9 @@ i80312_pci_conf_setup(struct i80312_soft
i80312_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f);
- binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
- pbus = PPB_BUSINFO_PRIMARY(binfo);
- sbus = PPB_BUSINFO_SECONDARY(binfo);
+ binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG);
+ pbus = PCI_BRIDGE_BUS_NUM_PRIMARY(binfo);
+ sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(binfo);
/*
* If the bus # is the Primary bus #, use the Primary
Index: src/sys/arch/evbarm/iq80310/iq80310_machdep.c
diff -u src/sys/arch/evbarm/iq80310/iq80310_machdep.c:1.89 src/sys/arch/evbarm/iq80310/iq80310_machdep.c:1.90
--- src/sys/arch/evbarm/iq80310/iq80310_machdep.c:1.89 Sun Oct 28 14:30:31 2018
+++ src/sys/arch/evbarm/iq80310/iq80310_machdep.c Fri Mar 1 09:25:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: iq80310_machdep.c,v 1.89 2018/10/28 14:30:31 skrll Exp $ */
+/* $NetBSD: iq80310_machdep.c,v 1.90 2019/03/01 09:25:59 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
@@ -73,7 +73,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: iq80310_machdep.c,v 1.89 2018/10/28 14:30:31 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: iq80310_machdep.c,v 1.90 2019/03/01 09:25:59 msaitoh Exp $");
#include "opt_arm_debug.h"
#include "opt_console.h"
@@ -376,13 +376,13 @@ initarm(void *arg)
printf("Resetting secondary PCI bus...\n");
#endif
reg = bus_space_read_4(&obio_bs_tag,
- I80312_PMMR_BASE + I80312_PPB_BASE, PPB_REG_BRIDGECONTROL);
+ I80312_PMMR_BASE + I80312_PPB_BASE, PCI_BRIDGE_CONTROL_REG);
bus_space_write_4(&obio_bs_tag,
- I80312_PMMR_BASE + I80312_PPB_BASE, PPB_REG_BRIDGECONTROL,
- reg | PPB_BC_SECONDARY_RESET);
+ I80312_PMMR_BASE + I80312_PPB_BASE, PCI_BRIDGE_CONTROL_REG,
+ reg | PCI_BRIDGE_CONTROL_SECBR);
delay(10 * 1000); /* 10ms enough? */
bus_space_write_4(&obio_bs_tag,
- I80312_PMMR_BASE + I80312_PPB_BASE, PPB_REG_BRIDGECONTROL,
+ I80312_PMMR_BASE + I80312_PPB_BASE, PCI_BRIDGE_CONTROL_REG,
reg);
}
Index: src/sys/arch/evbarm/iq80310/iq80310_pci.c
diff -u src/sys/arch/evbarm/iq80310/iq80310_pci.c:1.15 src/sys/arch/evbarm/iq80310/iq80310_pci.c:1.16
--- src/sys/arch/evbarm/iq80310/iq80310_pci.c:1.15 Fri Nov 16 15:06:23 2018
+++ src/sys/arch/evbarm/iq80310/iq80310_pci.c Fri Mar 1 09:25:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: iq80310_pci.c,v 1.15 2018/11/16 15:06:23 jmcneill Exp $ */
+/* $NetBSD: iq80310_pci.c,v 1.16 2019/03/01 09:25:59 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: iq80310_pci.c,v 1.15 2018/11/16 15:06:23 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: iq80310_pci.c,v 1.16 2019/03/01 09:25:59 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -95,8 +95,8 @@ iq80310_pci_intr_map(const struct pci_at
* the i80312.
*/
- reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
- sbus = PPB_BUSINFO_SECONDARY(reg);
+ reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG);
+ sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(reg);
if (pa->pa_bus != sbus) {
printf("iq80310_pci_intr_map: %d/%d/%d not on Secondary bus\n",
@@ -149,9 +149,9 @@ iq80310_pci_intr_map(const struct pci_at
* and can determine if we're looking at that device.
*/
- reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
- pbus = PPB_BUSINFO_PRIMARY(reg);
- sbus = PPB_BUSINFO_SECONDARY(reg);
+ reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG);
+ pbus = PCI_BRIDGE_BUS_NUM_PRIMARY(reg);
+ sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(reg);
/*
* XXX We don't know how to map interrupts on the Primary
@@ -192,8 +192,8 @@ iq80310_pci_intr_map(const struct pci_at
}
/* Now read the PPB's secondary bus number. */
- reg = pci_conf_read(pa->pa_pc, tag, PPB_REG_BUSINFO);
- sbus = PPB_BUSINFO_SECONDARY(reg);
+ reg = pci_conf_read(pa->pa_pc, tag, PCI_BRIDGE_BUS_REG);
+ sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(reg);
if (pa->pa_bus == sbus && pa->pa_device == 0 &&
pa->pa_function == 0) {
Index: src/sys/arch/macppc/pci/pci_machdep.c
diff -u src/sys/arch/macppc/pci/pci_machdep.c:1.41 src/sys/arch/macppc/pci/pci_machdep.c:1.42
--- src/sys/arch/macppc/pci/pci_machdep.c:1.41 Wed Oct 19 00:08:41 2016
+++ src/sys/arch/macppc/pci/pci_machdep.c Fri Mar 1 09:25:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_machdep.c,v 1.41 2016/10/19 00:08:41 nonaka Exp $ */
+/* $NetBSD: pci_machdep.c,v 1.42 2019/03/01 09:25:59 msaitoh Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.41 2016/10/19 00:08:41 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.42 2019/03/01 09:25:59 msaitoh Exp $");
#include <sys/types.h>
#include <sys/param.h>
@@ -318,7 +318,7 @@ fixpci(int parent, pci_chipset_tag_t pc)
* we found a CardBus bridge. Check if the bus number
* is sane
*/
- bi = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
+ bi = pci_conf_read(pc, tag, PCI_BRIDGE_BUS_REG);
busid = bi & 0xff;
if (busid == 0) {
fix_cardbus_bridge(node, pc, tag);
@@ -360,11 +360,11 @@ fix_cardbus_bridge(int node, pci_chipset
path[len] = 0;
aprint_verbose("\n%s: fixing bus number to %d", path, bus_number);
pci_decompose_tag(pc, tag, &bus, &dev, &fn);
- bi = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
+ bi = pci_conf_read(pc, tag, PCI_BRIDGE_BUS_REG);
bi &= 0xff000000;
/* XXX subordinate is always 32 here */
bi |= (bus & 0xff) | (bus_number << 8) | 0x200000;
- pci_conf_write(pc, tag, PPB_REG_BUSINFO, bi);
+ pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, bi);
}
}
Index: src/sys/arch/sparc/sparc/pci_fixup.c
diff -u src/sys/arch/sparc/sparc/pci_fixup.c:1.1 src/sys/arch/sparc/sparc/pci_fixup.c:1.2
--- src/sys/arch/sparc/sparc/pci_fixup.c:1.1 Tue Apr 16 06:57:06 2013
+++ src/sys/arch/sparc/sparc/pci_fixup.c Fri Mar 1 09:25:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_fixup.c,v 1.1 2013/04/16 06:57:06 jdc Exp $ */
+/* $NetBSD: pci_fixup.c,v 1.2 2019/03/01 09:25:59 msaitoh Exp $ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -479,10 +479,10 @@ mspcic_pci_fixup(int depth, pcitag_t sta
/* 64-bit prefetchable range (if supported) - set it to 0 */
val = pci_conf_read(NULL, starttag, PCI_BRIDGE_PREFETCHMEM_REG);
if (val & 0x01) {
- pci_conf_write(NULL, starttag, PCI_BRIDGE_PREFETCHBASE32_REG,
- (pcireg_t) ~0);
- pci_conf_write(NULL, starttag, PCI_BRIDGE_PREFETCHLIMIT32_REG,
- (pcireg_t) 0);
+ pci_conf_write(NULL, starttag,
+ PCI_BRIDGE_PREFETCHBASEUP32_REG, (pcireg_t) ~0);
+ pci_conf_write(NULL, starttag,
+ PCI_BRIDGE_PREFETCHLIMITUP32_REG, (pcireg_t) 0);
}
#ifdef SPARC_PCI_FIXUP_DEBUG
Index: src/sys/arch/sparc64/sparc64/rbus_machdep.c
diff -u src/sys/arch/sparc64/sparc64/rbus_machdep.c:1.16 src/sys/arch/sparc64/sparc64/rbus_machdep.c:1.17
--- src/sys/arch/sparc64/sparc64/rbus_machdep.c:1.16 Fri Jul 1 18:49:24 2011
+++ src/sys/arch/sparc64/sparc64/rbus_machdep.c Fri Mar 1 09:25:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: rbus_machdep.c,v 1.16 2011/07/01 18:49:24 dyoung Exp $ */
+/* $NetBSD: rbus_machdep.c,v 1.17 2019/03/01 09:25:59 msaitoh Exp $ */
/*
* Copyright (c) 2003 Takeshi Nakayama.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rbus_machdep.c,v 1.16 2011/07/01 18:49:24 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rbus_machdep.c,v 1.17 2019/03/01 09:25:59 msaitoh Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -157,10 +157,10 @@ pccbb_attach_hook(device_t parent, devic
if (bus >= 256)
printf("pccbb_attach_hook: 256 >= busses exist\n");
else {
- reg = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO);
+ reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_BUS_REG);
reg &= 0xff000000;
reg |= pa->pa_bus | (bus << 8) | (bus << 16);
- pci_conf_write(pc, pa->pa_tag, PPB_REG_BUSINFO, reg);
+ pci_conf_write(pc, pa->pa_tag, PCI_BRIDGE_BUS_REG, reg);
#ifdef DIAGNOSTIC
if ((*pc->spc_busnode)[bus].node != 0)
printf("pccbb_attach_hook: override bus %d"
Index: src/sys/arch/x86/pci/pci_bus_fixup.c
diff -u src/sys/arch/x86/pci/pci_bus_fixup.c:1.2 src/sys/arch/x86/pci/pci_bus_fixup.c:1.3
--- src/sys/arch/x86/pci/pci_bus_fixup.c:1.2 Fri Jul 1 18:22:08 2011
+++ src/sys/arch/x86/pci/pci_bus_fixup.c Fri Mar 1 09:25:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_bus_fixup.c,v 1.2 2011/07/01 18:22:08 dyoung Exp $ */
+/* $NetBSD: pci_bus_fixup.c,v 1.3 2019/03/01 09:25:59 msaitoh Exp $ */
/*
* Copyright (c) 1999, by UCHIYAMA Yasushi
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_bus_fixup.c,v 1.2 2011/07/01 18:22:08 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_bus_fixup.c,v 1.3 2019/03/01 09:25:59 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -119,10 +119,12 @@ pci_bus_fixup(pci_chipset_tag_t pc, int
/* Assign the bridge's secondary bus #. */
bus_max++;
- reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
+ reg = pci_conf_read(pc, tag,
+ PCI_BRIDGE_BUS_REG);
reg &= 0xff000000;
reg |= bus | (bus_max << 8) | (0xff << 16);
- pci_conf_write(pc, tag, PPB_REG_BUSINFO, reg);
+ pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG,
+ reg);
/* Scan subordinate bus. */
bus_sub = pci_bus_fixup(pc, bus_max);
@@ -130,7 +132,8 @@ pci_bus_fixup(pci_chipset_tag_t pc, int
/* Configure the bridge. */
reg &= 0xff000000;
reg |= bus | (bus_max << 8) | (bus_sub << 16);
- pci_conf_write(pc, tag, PPB_REG_BUSINFO, reg);
+ pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG,
+ reg);
/* record relationship */
pci_bus_parent[bus_max]=bus;
@@ -157,8 +160,8 @@ pci_bridge_reset(pci_chipset_tag_t pc, p
{
pcireg_t reg;
- reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
+ reg = pci_conf_read(pc, tag, PCI_BRIDGE_BUS_REG);
reg &= 0xff000000;
reg |= 0x00ffffff; /* max bus # */
- pci_conf_write(pc, tag, PPB_REG_BUSINFO, reg);
+ pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, reg);
}
Index: src/sys/arch/x86/pci/pci_ranges.c
diff -u src/sys/arch/x86/pci/pci_ranges.c:1.7 src/sys/arch/x86/pci/pci_ranges.c:1.8
--- src/sys/arch/x86/pci/pci_ranges.c:1.7 Thu Jun 1 02:45:08 2017
+++ src/sys/arch/x86/pci/pci_ranges.c Fri Mar 1 09:25:59 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_ranges.c,v 1.7 2017/06/01 02:45:08 chs Exp $ */
+/* $NetBSD: pci_ranges.c,v 1.8 2019/03/01 09:25:59 msaitoh Exp $ */
/*-
* Copyright (c) 2011 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_ranges.c,v 1.7 2017/06/01 02:45:08 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_ranges.c,v 1.8 2019/03/01 09:25:59 msaitoh Exp $");
#include <sys/types.h>
#include <sys/param.h>
@@ -173,15 +173,14 @@ io_range_extend_by_vga_enable(struct ran
, .r_mask = PCI_COMMAND_IO_ENABLE
}, {
.r_ofs = PCI_BRIDGE_CONTROL_REG
- , .r_mask =
- PCI_BRIDGE_CONTROL_VGA << PCI_BRIDGE_CONTROL_SHIFT
+ , .r_mask = PCI_BRIDGE_CONTROL_VGA;
}}
}, pal[2];
aprint_debug("%s: %d.%d.%d enter\n", __func__, bus, dev, fun);
if ((csr & PCI_COMMAND_IO_ENABLE) == 0 ||
- (bcr & (PCI_BRIDGE_CONTROL_VGA << PCI_BRIDGE_CONTROL_SHIFT)) == 0) {
+ (bcr & PCI_BRIDGE_CONTROL_VGA) == 0) {
aprint_debug("%s: %d.%d.%d I/O or VGA disabled\n",
__func__, bus, dev, fun);
return true;
@@ -228,10 +227,8 @@ io_range_extend_by_win(struct range_infe
r[0].r_ofs = ofs;
r[0].r_val = io;
- baser = ((io >> PCI_BRIDGE_STATIO_IOBASE_SHIFT) &
- PCI_BRIDGE_STATIO_IOBASE_MASK) >> 4;
- limitr = ((io >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) &
- PCI_BRIDGE_STATIO_IOLIMIT_MASK) >> 4;
+ baser = __SHIFTOUT(io, PCI_BRIDGE_STATIO_IOBASE) >> 4;
+ limitr = __SHIFTOUT(io, PCI_BRIDGE_STATIO_IOLIMIT) >> 4;
if (PCI_BRIDGE_IO_32BITS(io)) {
pcireg_t baseh, limith;
@@ -240,10 +237,8 @@ io_range_extend_by_win(struct range_infe
r[1].r_ofs = ofshigh;
r[1].r_val = iohigh;
- baseh = (iohigh >> PCI_BRIDGE_IOHIGH_BASE_SHIFT)
- & PCI_BRIDGE_IOHIGH_BASE_MASK;
- limith = (iohigh >> PCI_BRIDGE_IOHIGH_LIMIT_SHIFT)
- & PCI_BRIDGE_IOHIGH_LIMIT_MASK;
+ baseh = __SHIFTOUT(iohigh, PCI_BRIDGE_IOHIGH_BASE);
+ limith = __SHIFTOUT(iohigh, PCI_BRIDGE_IOHIGH_LIMIT);
baser |= baseh << 4;
limitr |= limith << 4;
@@ -447,15 +442,14 @@ mmio_range_extend_by_vga_enable(struct r
, .r_mask = PCI_COMMAND_MEM_ENABLE
}, {
.r_ofs = PCI_BRIDGE_CONTROL_REG
- , .r_mask =
- PCI_BRIDGE_CONTROL_VGA << PCI_BRIDGE_CONTROL_SHIFT
+ , .r_mask = PCI_BRIDGE_CONTROL_VGA
}}
}, pal;
aprint_debug("%s: %d.%d.%d enter\n", __func__, bus, dev, fun);
if ((csr & PCI_COMMAND_MEM_ENABLE) == 0 ||
- (bcr & (PCI_BRIDGE_CONTROL_VGA << PCI_BRIDGE_CONTROL_SHIFT)) == 0) {
+ (bcr & PCI_BRIDGE_CONTROL_VGA) == 0) {
aprint_debug("%s: %d.%d.%d memory or VGA disabled\n",
__func__, bus, dev, fun);
return true;
Index: src/sys/dev/acpi/acpi_pci.c
diff -u src/sys/dev/acpi/acpi_pci.c:1.25 src/sys/dev/acpi/acpi_pci.c:1.26
--- src/sys/dev/acpi/acpi_pci.c:1.25 Sun Jan 27 02:08:41 2019
+++ src/sys/dev/acpi/acpi_pci.c Fri Mar 1 09:26:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: acpi_pci.c,v 1.25 2019/01/27 02:08:41 pgoyette Exp $ */
+/* $NetBSD: acpi_pci.c,v 1.26 2019/03/01 09:26:00 msaitoh Exp $ */
/*
* Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: acpi_pci.c,v 1.25 2019/01/27 02:08:41 pgoyette Exp $");
+__KERNEL_RCSID(0, "$NetBSD: acpi_pci.c,v 1.26 2019/03/01 09:26:00 msaitoh Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -354,8 +354,8 @@ acpi_pcidev_ppb_downbus(uint16_t segment
return AE_TYPE;
/* This is a PCI-to-PCI bridge. Get its secondary bus#. */
- val = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
- *downbus = PPB_BUSINFO_SECONDARY(val);
+ val = pci_conf_read(pc, tag, PCI_BRIDGE_BUS_REG);
+ *downbus = PCI_BRIDGE_BUS_NUM_SECONDARY(val);
return AE_OK;
}
Index: src/sys/dev/cardbus/rbus_ppb.c
diff -u src/sys/dev/cardbus/rbus_ppb.c:1.45 src/sys/dev/cardbus/rbus_ppb.c:1.46
--- src/sys/dev/cardbus/rbus_ppb.c:1.45 Thu Jun 1 02:45:09 2017
+++ src/sys/dev/cardbus/rbus_ppb.c Fri Mar 1 09:26:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: rbus_ppb.c,v 1.45 2017/06/01 02:45:09 chs Exp $ */
+/* $NetBSD: rbus_ppb.c,v 1.46 2019/03/01 09:26:00 msaitoh Exp $ */
/*
* Copyright (c) 1999 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.45 2017/06/01 02:45:09 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rbus_ppb.c,v 1.46 2019/03/01 09:26:00 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -265,12 +265,12 @@ rbus_pci_addr_fixup(struct ppb_cardbus_s
/* first round amount of space up */
rct.bussize_ioreqs[busnum] =
- rbus_round_up(rct.bussize_ioreqs[busnum], PPB_IO_MIN);
+ rbus_round_up(rct.bussize_ioreqs[busnum], PCI_BRIDGE_IO_MIN);
rct.bussize_ioreqs[pci_bus_parent[busnum]] +=
rct.bussize_ioreqs[busnum];
rct.bussize_memreqs[busnum] =
- rbus_round_up(rct.bussize_memreqs[busnum], PPB_MEM_MIN);
+ rbus_round_up(rct.bussize_memreqs[busnum], PCI_BRIDGE_MEM_MIN);
rct.bussize_memreqs[pci_bus_parent[busnum]] +=
rct.bussize_memreqs[busnum];
@@ -278,8 +278,8 @@ rbus_pci_addr_fixup(struct ppb_cardbus_s
}
rct.bussize_ioreqs[minbus] =
- rbus_round_up(rct.bussize_ioreqs[minbus], 4096);
- rct.bussize_memreqs[minbus] =
+ rbus_round_up(rct.bussize_ioreqs[minbus], PCI_BRIDGE_IO_MIN);
+ rct.bussize_memreqs[minbus] = /* XXX Not 8 but PCI_BRIDGE_MEM_MIN ? */
rbus_round_up(rct.bussize_memreqs[minbus], 8);
printf("%s: total needs IO %08zx and MEM %08zx\n",
@@ -376,11 +376,11 @@ rbus_pci_addr_fixup(struct ppb_cardbus_s
PCI_COMMAND_STATUS_REG, reg);
/* now init the limit register for I/O */
- pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_IOSTATUS,
- (((start & 0xf000) >> 8) << PPB_IOBASE_SHIFT) |
- ((((start +
- rct.bussize_ioreqs[busnum] +
- 4095) & 0xf000) >> 8) << PPB_IOLIMIT_SHIFT));
+ pci_conf_write(pc, pci_bus_tag[busnum], PCI_BRIDGE_STATIO_REG,
+ __SHIFTIN((start >> 8)
+ & PCI_BRIDGE_STATIO_IOADDR, PCI_BRIDGE_STATIO_IOBASE) |
+ __SHIFTIN(((start + rct.bussize_ioreqs[busnum] + 4095) >> 8)
+ & PCI_BRIDGE_STATIO_IOADDR, PCI_BRIDGE_STATIO_IOLIMIT));
}
if(rct.bussize_memreqs[busnum]) {
@@ -412,22 +412,20 @@ rbus_pci_addr_fixup(struct ppb_cardbus_s
PCI_COMMAND_STATUS_REG, reg);
/* now init the limit register for memory */
- pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_MEM,
- ((start & PPB_MEM_MASK)
- >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT |
- (((start +
- rct.bussize_memreqs[busnum] +
- PPB_MEM_MIN-1) >> PPB_MEM_SHIFT)
- << PPB_MEMLIMIT_SHIFT));
+ pci_conf_write(pc, pci_bus_tag[busnum], PCI_BRIDGE_MEMORY_REG,
+ __SHIFTIN((start >> 16) & PCI_BRIDGE_MEMORY_ADDR,
+ PCI_BRIDGE_MEMORY_BASE) |
+ __SHIFTIN(((start + rct.bussize_memreqs[busnum] + PPB_MEM_MIN
+ - 1) >> 16) & PCI_BRIDGE_MEMORY_ADDR,
+ PCI_BRIDGE_MEMORY_LIMIT));
/* and set the prefetchable limits as well */
- pci_conf_write(pc, pci_bus_tag[busnum], PPB_REG_PREFMEM,
- ((start & PPB_MEM_MASK)
- >> PPB_MEM_SHIFT) << PPB_MEMBASE_SHIFT |
- (((start +
- rct.bussize_memreqs[busnum] +
- PPB_MEM_MIN-1) >> PPB_MEM_SHIFT)
- << PPB_MEMLIMIT_SHIFT));
+ pci_conf_write(pc, pci_bus_tag[busnum], PCI_BRIDGE_PREFETCHMEM_REG,
+ __SHIFTIN((start >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR,
+ PCI_BRIDGE_PREFETCHMEM_BASE) |
+ __SHIFTIN(((start + rct.bussize_memreqs[busnum] + PPB_MEM_MIN
+ - 1) >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR,
+ PCI_BRIDGE_PREFETCHMEM_LIMIT));
/* pci_conf_print(pc, pci_bus_tag[busnum], NULL); */
}
@@ -622,38 +620,37 @@ ppb_cardbus_attach(device_t parent, devi
csc->sc_tag = ca->ca_tag;
- busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO);
+ busdata = Cardbus_conf_read(ct, ca->ca_tag, PCI_BRIDGE_BUS_REG);
minbus = pcibios_max_bus;
maxbus = minbus; /* XXX; gcc */
- if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
+ if (PCI_BRIDGE_BUS_NUM_SECONDARY(busdata) == 0) {
aprint_error_dev(self, "not configured by system firmware calling pci_bus_fixup(%d)\n", 0);
/*
* first, pull the reset wire on the secondary bridge
* to clear all devices
*/
- busdata = Cardbus_conf_read(ct, ca->ca_tag,
- PPB_REG_BRIDGECONTROL);
- Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL,
- busdata | PPB_BC_SECONDARY_RESET);
+ busdata = Cardbus_conf_read(ct, ca->ca_tag, PCI_BRIDGE_CONTROL_REG);
+ Cardbus_conf_write(ct, ca->ca_tag, PCI_BRIDGE_CONTROL_REG,
+ busdata | PCI_BRIDGE_CONTROL_SECBR);
delay(1);
- Cardbus_conf_write(ct, ca->ca_tag, PPB_REG_BRIDGECONTROL,
+ Cardbus_conf_write(ct, ca->ca_tag, PCI_BRIDGE_CONTROL_REG,
busdata);
/* then go initialize the bridge control registers */
maxbus = pci_bus_fixup(psc->sc_pc, 0);
}
- busdata = Cardbus_conf_read(ct, ca->ca_tag, PPB_REG_BUSINFO);
- if(PPB_BUSINFO_SECONDARY(busdata) == 0) {
+ busdata = Cardbus_conf_read(ct, ca->ca_tag, PCI_BRIDGE_BUS_REG);
+ if(PCI_BRIDGE_BUS_NUM_SECONDARY(busdata) == 0) {
aprint_error_dev(self, "still not configured, not fixable.\n");
return;
}
#if 0
- minbus = PPB_BUSINFO_SECONDARY(busdata);
- maxbus = PPB_BUSINFO_SUBORDINATE(busdata);
+ minbus = PCI_BRIDGE_BUS_NUM_SECONDARY(busdata);
+ maxbus = PCI_BRIDGE_BUS_NUM_SUBORDINATE(busdata);
#endif
/* now, go and assign addresses for the new devices */
@@ -691,8 +688,8 @@ ppb_cardbus_attach(device_t parent, devi
pba.pba_memt = ca->ca_memt;
pba.pba_dmat = ca->ca_dmat;
pba.pba_pc = psc->sc_pc;
- pba.pba_flags = PCI_FLAGS_IO_OKAY|PCI_FLAGS_MEM_OKAY;
- pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
+ pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
+ pba.pba_bus = PCI_BRIDGE_BUS_NUM_SECONDARY(busdata);
pba.pba_bridgetag = &csc->sc_tag;
/*pba.pba_intrswiz = parent_sc->sc_intrswiz; */
pba.pba_intrtag = psc->sc_pa.pa_intrtag;
Index: src/sys/dev/pci/btvmeii.c
diff -u src/sys/dev/pci/btvmeii.c:1.22 src/sys/dev/pci/btvmeii.c:1.23
--- src/sys/dev/pci/btvmeii.c:1.22 Sat Oct 27 17:18:28 2012
+++ src/sys/dev/pci/btvmeii.c Fri Mar 1 09:26:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: btvmeii.c,v 1.22 2012/10/27 17:18:28 chs Exp $ */
+/* $NetBSD: btvmeii.c,v 1.23 2019/03/01 09:26:00 msaitoh Exp $ */
/*
* Copyright (c) 1999
@@ -32,7 +32,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: btvmeii.c,v 1.22 2012/10/27 17:18:28 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: btvmeii.c,v 1.23 2019/03/01 09:26:00 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -145,8 +145,8 @@ b3_2706_match(device_t parent, cfdata_t
|| (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_DEC_21152))
return (0);
- secbus = PPB_BUSINFO_SECONDARY(pci_conf_read(pc, pa->pa_tag,
- PPB_REG_BUSINFO));
+ secbus = PCI_BRIDGE_BUS_NUM_SECONDARY(pci_conf_read(pc, pa->pa_tag,
+ PCI_BRIDGE_BUS_REG));
if (secbus == 0) {
printf("b3_2706_match: ppb not configured\n");
return (0);
@@ -195,8 +195,8 @@ b3_2706_attach(device_t parent, device_t
aprint_naive(": VME bus adapter\n");
aprint_normal("\n");
- secbus = PPB_BUSINFO_SECONDARY(pci_conf_read(pc, pa->pa_tag,
- PPB_REG_BUSINFO));
+ secbus = PCI_BRIDGE_BUS_NUM_SECONDARY(pci_conf_read(pc, pa->pa_tag,
+ PCI_BRIDGE_BUS_REG));
memcpy(&aa, pa, sizeof(struct pci_attach_args));
aa.pa_device = 4;
Index: src/sys/dev/pci/pccbb.c
diff -u src/sys/dev/pci/pccbb.c:1.213 src/sys/dev/pci/pccbb.c:1.214
--- src/sys/dev/pci/pccbb.c:1.213 Fri Mar 1 05:41:56 2019
+++ src/sys/dev/pci/pccbb.c Fri Mar 1 09:26:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pccbb.c,v 1.213 2019/03/01 05:41:56 msaitoh Exp $ */
+/* $NetBSD: pccbb.c,v 1.214 2019/03/01 09:26:00 msaitoh Exp $ */
/*
* Copyright (c) 1998, 1999 and 2000
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.213 2019/03/01 05:41:56 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.214 2019/03/01 09:26:00 msaitoh Exp $");
/*
#define CBB_DEBUG
@@ -764,13 +764,13 @@ pccbb_chipinit(struct pccbb_softc *sc)
bcr |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */
bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */
/* assert reset */
- bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT;
+ bcr |= PCI_BRIDGE_CONTROL_SECBR;
/* Set master abort mode to 1, forward SERR# from secondary
* to primary, and detect parity errors on secondary.
*/
- bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT;
- bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT;
- bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT;
+ bcr |= PCI_BRIDGE_CONTROL_MABRT;
+ bcr |= PCI_BRIDGE_CONTROL_SERR;
+ bcr |= PCI_BRIDGE_CONTROL_PERE;
pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr);
switch (sc->sc_chipset) {
@@ -1443,14 +1443,14 @@ cb_reset(struct pccbb_softc *sc)
aprint_debug("%s: enter bcr %" PRIx32 "\n", __func__, bcr);
/* Reset bit Assert (bit 6 at 0x3E) */
- bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT;
+ bcr |= PCI_BRIDGE_CONTROL_SECBR;
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG, bcr);
aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr);
delay_ms(reset_duration, sc);
if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */
/* Reset bit Deassert (bit 6 at 0x3E) */
- bcr &= ~(PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT);
+ bcr &= ~(PCI_BRIDGE_CONTROL_SECBR);
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BRIDGE_CONTROL_REG,
bcr);
aprint_debug("%s: wrote bcr %" PRIx32 "\n", __func__, bcr);
Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.211 src/sys/dev/pci/pci_subr.c:1.212
--- src/sys/dev/pci/pci_subr.c:1.211 Thu Feb 28 16:56:35 2019
+++ src/sys/dev/pci/pci_subr.c Fri Mar 1 09:26:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.211 2019/02/28 16:56:35 khorben Exp $ */
+/* $NetBSD: pci_subr.c,v 1.212 2019/03/01 09:26:00 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.211 2019/02/28 16:56:35 khorben Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.212 2019/03/01 09:26:00 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -4504,13 +4504,13 @@ pci_conf_print_type1(
rval = regs[o2i(PCI_BRIDGE_BUS_REG)];
printf(" Primary bus number: 0x%02x\n",
- PCI_BRIDGE_BUS_PRIMARY(rval));
+ PCI_BRIDGE_BUS_NUM_PRIMARY(rval));
printf(" Secondary bus number: 0x%02x\n",
- PCI_BRIDGE_BUS_SECONDARY(rval));
+ PCI_BRIDGE_BUS_NUM_SECONDARY(rval));
printf(" Subordinate bus number: 0x%02x\n",
- PCI_BRIDGE_BUS_SUBORDINATE(rval));
+ PCI_BRIDGE_BUS_NUM_SUBORDINATE(rval));
printf(" Secondary bus latency timer: 0x%02x\n",
- PCI_BRIDGE_BUS_SEC_LATTIMER(rval));
+ PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(rval));
rval = regs[o2i(PCI_BRIDGE_STATIO_REG)];
pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16)));
@@ -4524,14 +4524,12 @@ pci_conf_print_type1(
else
use_upper = 0;
onoff("32bit I/O", rval, use_upper);
- base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8;
- limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT)
- & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8;
- limit |= 0x00000fff;
+ base = PCI_BRIDGE_STATIO_IOBASE_ADDR(rval);
+ limit = PCI_BRIDGE_STATIO_IOLIMIT_ADDR(rval);
rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)];
- base_h = (rval >> 0) & 0xffff;
- limit_h = (rval >> 16) & 0xffff;
+ base_h = __SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_BASE);
+ limit_h = __SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_LIMIT);
printf(" base upper 16 bits register: 0x%04x\n", base_h);
printf(" limit upper 16 bits register: 0x%04x\n", limit_h);
@@ -4550,14 +4548,12 @@ pci_conf_print_type1(
/* Non-prefetchable memory region */
rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)];
printf(" Memory region:\n");
- printf(" base register: 0x%04x\n",
- (rval >> 0) & 0xffff);
- printf(" limit register: 0x%04x\n",
- (rval >> 16) & 0xffff);
- base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT)
- & PCI_BRIDGE_MEMORY_BASE_MASK) << 20;
- limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT)
- & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff;
+ printf(" base register: 0x%04hx\n",
+ (uint16_t)__SHIFTOUT(rval, PCI_BRIDGE_MEMORY_BASE));
+ printf(" limit register: 0x%04hx\n",
+ (uint16_t)__SHIFTOUT(rval, PCI_BRIDGE_MEMORY_LIMIT));
+ base = PCI_BRIDGE_MEMORY_BASE_ADDR(rval);
+ limit = PCI_BRIDGE_MEMORY_LIMIT_ADDR(rval);
if (base < limit)
printf(" range: 0x%08x-0x%08x\n", base, limit);
else
@@ -4570,8 +4566,8 @@ pci_conf_print_type1(
(rval >> 0) & 0xffff);
printf(" limit register: 0x%04x\n",
(rval >> 16) & 0xffff);
- base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)];
- limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)];
+ base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASEUP32_REG)];
+ limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMITUP32_REG)];
printf(" base upper 32 bits register: 0x%08x\n",
base_h);
printf(" limit upper 32 bits register: 0x%08x\n",
@@ -4581,10 +4577,8 @@ pci_conf_print_type1(
else
use_upper = 0;
onoff("64bit memory address", rval, use_upper);
- pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT)
- & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20;
- plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT)
- & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff;
+ pbase = PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(rval);
+ plimit = PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(rval);
if (use_upper == 1) {
pbase |= (uint64_t)base_h << 32;
plimit |= (uint64_t)limit_h << 32;
@@ -4606,8 +4600,8 @@ pci_conf_print_type1(
else
printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]);
- /* XXX */
- printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]);
+ printf(" Expansion ROM Base Address: 0x%08x\n",
+ regs[o2i(PCI_BRIDGE_EXPROMADDR_REG)]);
rval = regs[o2i(PCI_INTERRUPT_REG)];
printf(" Interrupt line: 0x%02x\n",
@@ -4635,9 +4629,9 @@ pci_conf_print_type1(
break;
}
printf("\n");
- rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT)
- & PCI_BRIDGE_CONTROL_MASK;
- printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */
+ rval = regs[o2i(PCI_BRIDGE_CONTROL_REG)];
+ printf(" Bridge control register: 0x%04hx\n",
+ (uint16_t)__SHIFTOUT(rval, PCI_BRIDGE_CONTROL));
onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE);
onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR);
onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA);
@@ -4651,7 +4645,15 @@ pci_conf_print_type1(
onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16);
onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT);
onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR);
- onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B);
+ onoff("Fast back-to-back enable", rval, PCI_BRIDGE_CONTROL_SECFASTB2B);
+ onoff("Primary Discard Timer", rval,
+ PCI_BRIDGE_CONTROL_PRI_DISC_TIMER);
+ onoff("Secondary Discard Timer",
+ rval, PCI_BRIDGE_CONTROL_SEC_DISC_TIMER);
+ onoff("Discard Timer Status", rval,
+ PCI_BRIDGE_CONTROL_DISC_TIMER_STAT);
+ onoff("Discard Timer SERR# Enable", rval,
+ PCI_BRIDGE_CONTROL_DISC_TIMER_SERR);
}
static void
Index: src/sys/dev/pci/pciconf.c
diff -u src/sys/dev/pci/pciconf.c:1.40 src/sys/dev/pci/pciconf.c:1.41
--- src/sys/dev/pci/pciconf.c:1.40 Fri Mar 1 07:02:56 2019
+++ src/sys/dev/pci/pciconf.c Fri Mar 1 09:26:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pciconf.c,v 1.40 2019/03/01 07:02:56 msaitoh Exp $ */
+/* $NetBSD: pciconf.c,v 1.41 2019/03/01 09:26:00 msaitoh Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -65,7 +65,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.40 2019/03/01 07:02:56 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.41 2019/03/01 09:26:00 msaitoh Exp $");
#include "opt_pci.h"
@@ -306,9 +306,9 @@ set_busreg(pci_chipset_tag_t pc, pcitag_
{
pcireg_t busreg;
- busreg = prim << PCI_BRIDGE_BUS_PRIMARY_SHIFT;
- busreg |= sec << PCI_BRIDGE_BUS_SECONDARY_SHIFT;
- busreg |= sub << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT;
+ busreg = __SHIFTIN(prim, PCI_BRIDGE_BUS_PRIMARY);
+ busreg |= __SHIFTIN(sec, PCI_BRIDGE_BUS_SECONDARY);
+ busreg |= __SHIFTIN(sub, PCI_BRIDGE_BUS_SUBORDINATE);
pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg);
}
@@ -486,9 +486,9 @@ pci_do_device_query(pciconf_bus_t *pb, p
busreg = pci_conf_read(pb->pc, tag, PCI_BUSNUM);
busreg = (busreg & 0xff000000) |
- pb->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT |
- pb->next_busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT |
- pb->next_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT;
+ __SHIFTIN(pb->busno, PCI_BRIDGE_BUS_PRIMARY) |
+ __SHIFTIN(pb->next_busno, PCI_BRIDGE_BUS_SECONDARY) |
+ __SHIFTIN(pb->next_busno, PCI_BRIDGE_BUS_SUBORDINATE);
pci_conf_write(pb->pc, tag, PCI_BUSNUM, busreg);
pb->next_busno++;
@@ -867,9 +867,8 @@ configure_bridge(pciconf_dev_t *pd)
io_limit = 0x0000;
}
if (pb->io_32bit) {
- iohigh =
- ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) |
- ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT);
+ iohigh = __SHIFTIN(io_base >> 16, PCI_BRIDGE_IOHIGH_BASE) |
+ __SHIFTIN(io_limit >> 16, PCI_BRIDGE_IOHIGH_LIMIT);
} else {
if (io_limit > 0xFFFF) {
printf("Bus %d bridge does not support 32-bit I/O. ",
@@ -881,11 +880,11 @@ configure_bridge(pciconf_dev_t *pd)
iohigh = 0;
}
io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) &
- (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT);
- io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK)
- << PCI_BRIDGE_STATIO_IOBASE_SHIFT);
- io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK)
- << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT);
+ PCI_BRIDGE_STATIO_STATUS;
+ io |= __SHIFTIN((io_base >> 8) & PCI_BRIDGE_STATIO_IOADDR,
+ PCI_BRIDGE_STATIO_IOBASE);
+ io |= __SHIFTIN((io_limit >> 8) & PCI_BRIDGE_STATIO_IOADDR,
+ PCI_BRIDGE_STATIO_IOLIMIT);
pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io);
pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh);
@@ -905,10 +904,10 @@ configure_bridge(pciconf_dev_t *pd)
mem_limit = 0x000000;
}
#endif
- mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK)
- << PCI_BRIDGE_MEMORY_BASE_SHIFT);
- mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK)
- << PCI_BRIDGE_MEMORY_LIMIT_SHIFT);
+ mem = __SHIFTIN((mem_base >> 16) & PCI_BRIDGE_MEMORY_ADDR,
+ PCI_BRIDGE_MEMORY_BASE);
+ mem |= __SHIFTIN((mem_limit >> 16) & PCI_BRIDGE_MEMORY_ADDR,
+ PCI_BRIDGE_MEMORY_LIMIT);
pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem);
/* Configure prefetchable mem base & limit */
@@ -930,10 +929,10 @@ configure_bridge(pciconf_dev_t *pd)
mem_limit = 0x000000;
}
#endif
- mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK)
- << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT);
- mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK)
- << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT);
+ mem = __SHIFTIN((mem_base >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR,
+ PCI_BRIDGE_PREFETCHMEM_BASE);
+ mem |= __SHIFTIN((mem_limit >> 16) & PCI_BRIDGE_PREFETCHMEM_ADDR,
+ PCI_BRIDGE_PREFETCHMEM_LIMIT);
pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem);
/*
* XXX -- 64-bit systems need a lot more than just this...
@@ -941,10 +940,10 @@ configure_bridge(pciconf_dev_t *pd)
if (isprefetchmem64) {
mem_base = (uint64_t)mem_base >> 32;
mem_limit = (uint64_t)mem_limit >> 32;
- pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG,
- mem_base & 0xffffffff);
- pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG,
- mem_limit & 0xffffffff);
+ pci_conf_write(pb->pc, pd->tag,
+ PCI_BRIDGE_PREFETCHBASEUP32_REG, mem_base & 0xffffffff);
+ pci_conf_write(pb->pc, pd->tag,
+ PCI_BRIDGE_PREFETCHLIMITUP32_REG, mem_limit & 0xffffffff);
}
rv = configure_bus(pb);
@@ -957,13 +956,11 @@ configure_bridge(pciconf_dev_t *pd)
extent_destroy(pb->pmemext);
if (rv == 0) {
cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG);
- cmd &= PCI_BRIDGE_CONTROL_MASK;
- cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR)
- << PCI_BRIDGE_CONTROL_SHIFT;
- if (pb->fast_b2b) {
- cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B
- << PCI_BRIDGE_CONTROL_SHIFT;
- }
+ cmd &= ~PCI_BRIDGE_CONTROL; /* Clear control bit first */
+ cmd |= PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR;
+ if (pb->fast_b2b)
+ cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B;
+
pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd);
cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG);
cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.146 src/sys/dev/pci/pcireg.h:1.147
--- src/sys/dev/pci/pcireg.h:1.146 Fri Nov 30 10:18:37 2018
+++ src/sys/dev/pci/pcireg.h Fri Mar 1 09:26:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.146 2018/11/30 10:18:37 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.147 2019/03/01 09:26:00 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -1290,67 +1290,85 @@ typedef u_int8_t pci_intr_line_t;
/* Header Type 1 (Bridge) configuration registers */
#define PCI_BRIDGE_BUS_REG 0x18
-#define PCI_BRIDGE_BUS_EACH_MASK 0xff
-#define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0
-#define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8
-#define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16
-#define PCI_BRIDGE_BUS_SEC_LATTIMER_SHIFT 24
-#define PCI_BRIDGE_BUS_PRIMARY(reg) \
- (((reg) >> PCI_BRIDGE_BUS_PRIMARY_SHIFT) & PCI_BRIDGE_BUS_EACH_MASK)
-#define PCI_BRIDGE_BUS_SECONDARY(reg) \
- (((reg) >> PCI_BRIDGE_BUS_SECONDARY_SHIFT) & PCI_BRIDGE_BUS_EACH_MASK)
-#define PCI_BRIDGE_BUS_SUBORDINATE(reg) \
- (((reg) >> PCI_BRIDGE_BUS_SUBORDINATE_SHIFT) &PCI_BRIDGE_BUS_EACH_MASK)
-#define PCI_BRIDGE_BUS_SEC_LATTIMER(reg) \
- (((reg) >> PCI_BRIDGE_BUS_SEC_LATTIMER_SHIFT)&PCI_BRIDGE_BUS_EACH_MASK)
-
-
-#define PCI_BRIDGE_STATIO_REG 0x1C
-#define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0
-#define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8
-#define PCI_BRIDGE_STATIO_STATUS_SHIFT 16
-#define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0
-#define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0
-#define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff
-#define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1)
+#define PCI_BRIDGE_BUS_PRIMARY __BITS(0, 7)
+#define PCI_BRIDGE_BUS_SECONDARY __BITS(8, 15)
+#define PCI_BRIDGE_BUS_SUBORDINATE __BITS(16, 23)
+#define PCI_BRIDGE_BUS_SEC_LATTIMER __BITS(24, 31)
+#define PCI_BRIDGE_BUS_NUM_PRIMARY(reg) \
+ ((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_PRIMARY))
+#define PCI_BRIDGE_BUS_NUM_SECONDARY(reg) \
+ ((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SECONDARY))
+#define PCI_BRIDGE_BUS_NUM_SUBORDINATE(reg) \
+ ((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SUBORDINATE))
+#define PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(reg) \
+ ((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SEC_LATTIMER))
+
+/* Minimum size of the window */
+#define PCI_BRIDGE_IO_MIN 0x00001000UL
+#define PCI_BRIDGE_MEM_MIN 0x00100000UL
+
+#define PCI_BRIDGE_STATIO_REG 0x1c
+#define PCI_BRIDGE_STATIO_IOBASE __BITS(0, 7)
+#define PCI_BRIDGE_STATIO_IOLIMIT __BITS(8, 15)
+#define PCI_BRIDGE_STATIO_STATUS __BITS(16, 31)
+#define PCI_BRIDGE_STATIO_IOADDR 0xf0
+#define PCI_BRIDGE_STATIO_IOADDR_TYPE 0x0f /* Read only */
+#define PCI_BRIDGE_STATIO_IOADDR_32 0x01
+#define PCI_BRIDGE_STATIO_IOBASE_ADDR(reg) \
+ ((__SHIFTOUT((reg), PCI_BRIDGE_STATIO_IOBASE) \
+ & PCI_BRIDGE_STATIO_IOADDR) << 8)
+#define PCI_BRIDGE_STATIO_IOLIMIT_ADDR(reg) \
+ (((__SHIFTOUT((reg), PCI_BRIDGE_STATIO_IOLIMIT) \
+ & PCI_BRIDGE_STATIO_IOADDR) << 8) | (PCI_BRIDGE_IO_MIN - 1))
+#define PCI_BRIDGE_IO_32BITS(reg) \
+ (((reg) & PCI_BRIDGE_STATIO_IOADDR_TYPE) == PCI_BRIDGE_STATIO_IOADDR_32)
#define PCI_BRIDGE_MEMORY_REG 0x20
-#define PCI_BRIDGE_MEMORY_BASE_SHIFT 4
-#define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20
-#define PCI_BRIDGE_MEMORY_BASE_MASK 0x0fff
-#define PCI_BRIDGE_MEMORY_LIMIT_MASK 0x0fff
+#define PCI_BRIDGE_MEMORY_BASE __BITS(0, 15)
+#define PCI_BRIDGE_MEMORY_LIMIT __BITS(16, 31)
+#define PCI_BRIDGE_MEMORY_ADDR 0xfff0
+#define PCI_BRIDGE_MEMORY_BASE_ADDR(reg) \
+ ((__SHIFTOUT((reg), PCI_BRIDGE_MEMORY_BASE) \
+ & PCI_BRIDGE_MEMORY_ADDR) << 16)
+#define PCI_BRIDGE_MEMORY_LIMIT_ADDR(reg) \
+ (((__SHIFTOUT((reg), PCI_BRIDGE_MEMORY_LIMIT) \
+ & PCI_BRIDGE_MEMORY_ADDR) << 16) | 0x000fffff)
#define PCI_BRIDGE_PREFETCHMEM_REG 0x24
-#define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4
-#define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20
-#define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0x0fff
-#define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0x0fff
+#define PCI_BRIDGE_PREFETCHMEM_BASE __BITS(0, 15)
+#define PCI_BRIDGE_PREFETCHMEM_LIMIT __BITS(16, 31)
+#define PCI_BRIDGE_PREFETCHMEM_ADDR 0xfff0
+#define PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(reg) \
+ ((__SHIFTOUT((reg), PCI_BRIDGE_PREFETCHMEM_BASE) \
+ & PCI_BRIDGE_PREFETCHMEM_ADDR) << 16)
+#define PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(reg) \
+ (((__SHIFTOUT((reg), PCI_BRIDGE_PREFETCHMEM_LIMIT) \
+ & PCI_BRIDGE_PREFETCHMEM_ADDR) << 16) | 0x000fffff)
#define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf)
-#define PCI_BRIDGE_PREFETCHBASE32_REG 0x28
-#define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2c
+#define PCI_BRIDGE_PREFETCHBASEUP32_REG 0x28
+#define PCI_BRIDGE_PREFETCHLIMITUP32_REG 0x2c
#define PCI_BRIDGE_IOHIGH_REG 0x30
-#define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0
-#define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16
-#define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff
-#define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff
-
-#define PCI_BRIDGE_CONTROL_REG 0x3c
-#define PCI_BRIDGE_CONTROL_SHIFT 16
-#define PCI_BRIDGE_CONTROL_MASK 0xffff
-#define PCI_BRIDGE_CONTROL_PERE (1 << 0)
-#define PCI_BRIDGE_CONTROL_SERR (1 << 1)
-#define PCI_BRIDGE_CONTROL_ISA (1 << 2)
-#define PCI_BRIDGE_CONTROL_VGA (1 << 3)
-#define PCI_BRIDGE_CONTROL_VGA16 (1 << 4)
-#define PCI_BRIDGE_CONTROL_MABRT (1 << 5)
-#define PCI_BRIDGE_CONTROL_SECBR (1 << 6)
-#define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7)
-#define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8)
-#define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9)
-#define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10)
-#define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11)
+#define PCI_BRIDGE_IOHIGH_BASE __BITS(0, 15)
+#define PCI_BRIDGE_IOHIGH_LIMIT __BITS(16, 31)
+
+#define PCI_BRIDGE_EXPROMADDR_REG 0x38
+
+#define PCI_BRIDGE_CONTROL_REG 0x3c /* Upper 16 bit */
+#define PCI_BRIDGE_CONTROL __BITS(16, 31)
+#define PCI_BRIDGE_CONTROL_PERE __BIT(16)
+#define PCI_BRIDGE_CONTROL_SERR __BIT(17)
+#define PCI_BRIDGE_CONTROL_ISA __BIT(18)
+#define PCI_BRIDGE_CONTROL_VGA __BIT(19)
+#define PCI_BRIDGE_CONTROL_VGA16 __BIT(20)
+#define PCI_BRIDGE_CONTROL_MABRT __BIT(21)
+#define PCI_BRIDGE_CONTROL_SECBR __BIT(22)
+#define PCI_BRIDGE_CONTROL_SECFASTB2B __BIT(23)
+#define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER __BIT(24)
+#define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER __BIT(25)
+#define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT __BIT(26)
+#define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR __BIT(27)
/* Reserved (1 << 12) - (1 << 15) */
/*
Index: src/sys/dev/pci/ppb.c
diff -u src/sys/dev/pci/ppb.c:1.67 src/sys/dev/pci/ppb.c:1.68
--- src/sys/dev/pci/ppb.c:1.67 Tue Jan 29 09:25:52 2019
+++ src/sys/dev/pci/ppb.c Fri Mar 1 09:26:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ppb.c,v 1.67 2019/01/29 09:25:52 msaitoh Exp $ */
+/* $NetBSD: ppb.c,v 1.68 2019/03/01 09:26:00 msaitoh Exp $ */
/*
* Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.67 2019/01/29 09:25:52 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.68 2019/03/01 09:26:00 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_ppb.h"
@@ -230,9 +230,9 @@ ppbattach(device_t parent, device_t self
sc->sc_tag = pa->pa_tag;
sc->sc_dev = self;
- busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO);
+ busdata = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_BUS_REG);
- if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
+ if (PCI_BRIDGE_BUS_NUM_SECONDARY(busdata) == 0) {
aprint_normal_dev(self, "not configured by system firmware\n");
return;
}
@@ -246,9 +246,9 @@ ppbattach(device_t parent, device_t self
* decompose our tag.
*/
/* sanity check. */
- if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata))
+ if (pa->pa_bus != PCI_BRIDGE_BUS_NUM_PRIMARY(busdata))
panic("ppbattach: bus in tag (%d) != bus in reg (%d)",
- pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata));
+ pa->pa_bus, PCI_BRIDGE_BUS_NUM_PRIMARY(busdata));
#endif
/* Check for PCI Express capabilities and setup hotplug support. */
@@ -360,22 +360,18 @@ ppbattach(device_t parent, device_t self
#endif /* PPB_USEINTR */
/* Configuration test */
- if (PPB_BUSINFO_SECONDARY(busdata) != 0) {
+ if (PCI_BRIDGE_BUS_NUM_SECONDARY(busdata) != 0) {
uint32_t base, limit;
/* I/O region test */
reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_STATIO_REG);
- base = (reg & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8;
- limit = ((reg >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT)
- & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8;
- limit |= 0x00000fff;
+ base = PCI_BRIDGE_STATIO_IOBASE_ADDR(reg);
+ limit = PCI_BRIDGE_STATIO_IOLIMIT_ADDR(reg);
if (PCI_BRIDGE_IO_32BITS(reg)) {
reg = pci_conf_read(pc, pa->pa_tag,
PCI_BRIDGE_IOHIGH_REG);
- base |= ((reg >> PCI_BRIDGE_IOHIGH_BASE_SHIFT)
- & 0xffff) << 16;
- limit |= ((reg >> PCI_BRIDGE_IOHIGH_LIMIT_SHIFT)
- & 0xffff) << 16;
+ base |= __SHIFTOUT(reg, PCI_BRIDGE_IOHIGH_BASE) << 16;
+ limit |= __SHIFTOUT(reg, PCI_BRIDGE_IOHIGH_LIMIT) <<16;
}
if (base < limit) {
second_configured = true;
@@ -384,10 +380,8 @@ ppbattach(device_t parent, device_t self
/* Non-prefetchable memory region test */
reg = pci_conf_read(pc, pa->pa_tag, PCI_BRIDGE_MEMORY_REG);
- base = ((reg >> PCI_BRIDGE_MEMORY_BASE_SHIFT)
- & PCI_BRIDGE_MEMORY_BASE_MASK) << 20;
- limit = (((reg >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT)
- & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff;
+ base = PCI_BRIDGE_MEMORY_BASE_ADDR(reg);
+ limit = PCI_BRIDGE_MEMORY_LIMIT_ADDR(reg);
if (base < limit) {
second_configured = true;
goto configure;
@@ -396,17 +390,16 @@ ppbattach(device_t parent, device_t self
/* Prefetchable memory region test */
reg = pci_conf_read(pc, pa->pa_tag,
PCI_BRIDGE_PREFETCHMEM_REG);
- base = ((reg >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT)
- & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20;
- limit = (((reg >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT)
- & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff;
+ base = PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(reg);
+ limit = PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(reg);
+
if (PCI_BRIDGE_PREFETCHMEM_64BITS(reg)) {
reg = pci_conf_read(pc, pa->pa_tag,
PCI_BRIDGE_IOHIGH_REG);
base |= (uint64_t)pci_conf_read(pc, pa->pa_tag,
- PCI_BRIDGE_PREFETCHBASE32_REG) << 32;
+ PCI_BRIDGE_PREFETCHBASEUP32_REG) << 32;
limit |= (uint64_t)pci_conf_read(pc, pa->pa_tag,
- PCI_BRIDGE_PREFETCHLIMIT32_REG) << 32;
+ PCI_BRIDGE_PREFETCHLIMITUP32_REG) << 32;
}
if (base < limit) {
second_configured = true;
@@ -441,8 +434,8 @@ configure:
pba.pba_dmat64 = pa->pa_dmat64;
pba.pba_pc = pc;
pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY;
- pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
- pba.pba_sub = PPB_BUSINFO_SUBORDINATE(busdata);
+ pba.pba_bus = PCI_BRIDGE_BUS_NUM_SECONDARY(busdata);
+ pba.pba_sub = PCI_BRIDGE_BUS_NUM_SUBORDINATE(busdata);
pba.pba_bridgetag = &sc->sc_tag;
pba.pba_intrswiz = pa->pa_intrswiz;
pba.pba_intrtag = pa->pa_intrtag;
Index: src/sys/dev/pci/ppbreg.h
diff -u src/sys/dev/pci/ppbreg.h:1.9 src/sys/dev/pci/ppbreg.h:1.10
--- src/sys/dev/pci/ppbreg.h:1.9 Mon Jul 2 04:04:08 2018
+++ src/sys/dev/pci/ppbreg.h Fri Mar 1 09:26:00 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: ppbreg.h,v 1.9 2018/07/02 04:04:08 msaitoh Exp $ */
+/* $NetBSD: ppbreg.h,v 1.10 2019/03/01 09:26:00 msaitoh Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@@ -30,39 +30,7 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/*
- * PCI-PCI Bridge chip register definitions and macros.
- * Derived from information found in the ``PCI to PCI Bridge
- * Architecture Specification, Revision 1.0, April 5, 1994.''
- *
- * XXX much is missing.
- */
-
-/*
- * Register offsets
- */
-#define PPB_REG_BASE0 0x10 /* Base Addr Reg. 0 */
-#define PPB_REG_BASE1 0x14 /* Base Addr Reg. 1 */
-#define PPB_REG_BUSINFO 0x18 /* Bus information */
-#define PPB_REG_IOSTATUS 0x1c /* I/O base+lim & sec stat */
-#define PPB_REG_MEM 0x20 /* Memory base/limit */
-#define PPB_REG_PREFMEM 0x24 /* Pref Mem base/limit */
-#define PPB_REG_PREFBASE_HI32 0x28 /* Pref Mem base high bits */
-#define PPB_REG_PREFLIM_HI32 0x2c /* Pref Mem lim high bits */
-#define PPB_REG_IO_HI 0x30 /* I/O base+lim high bits */
-#define PPB_REG_BRIDGECONTROL 0x3c /* bridge control register */
-
-/*
- * Macros to extract the contents of the "Bus Info" register.
- */
-#define PPB_BUSINFO_PRIMARY(bir) \
- ((bir >> 0) & 0xff)
-#define PPB_BUSINFO_SECONDARY(bir) \
- ((bir >> 8) & 0xff)
-#define PPB_BUSINFO_SUBORDINATE(bir) \
- ((bir >> 16) & 0xff)
-#define PPB_BUSINFO_SECLAT(bir) \
- ((bir >> 24) & 0xff)
+/* PCI-PCI Bridge chip macros. Register definitions are in pcireg.h. */
/*
* Routine to translate between secondary bus interrupt pin/device number and
@@ -70,42 +38,3 @@
*/
#define PPB_INTERRUPT_SWIZZLE(pin, device) \
((((pin) + (device) - 1) % 4) + 1)
-
-/*
- * secondary bus I/O base and limits
- */
-#define PPB_IOBASE_SHIFT 0
-#define PPB_IOLIMIT_SHIFT 8
-#define PPB_IO_MASK 0xf000
-#define PPB_IO_MIN 4096
-
-/*
- * secondary bus memory base and limits
- */
-#define PPB_MEMBASE_SHIFT 0
-#define PPB_MEMLIMIT_SHIFT 16
-#define PPB_MEM_MASK 0xfff00000
-#define PPB_MEM_SHIFT 16
-#define PPB_MEM_MIN 0x00100000
-
-/*
- * bridge control register (see table 3.9 of ppb rev. 1.1)
- *
- * Note these are in the *upper* 16 bits of the Bridge Control
- * Register (the bottom 16 are Interrupt Line and Interrupt Pin).
- */
-#define PPB_BC_BITBASE 16
-
-#define PPB_BC_PARITYERRORRESPONSE_ENABLE (1U << (0 + PPB_BC_BITBASE))
-#define PPB_BC_SERR_ENABLE (1U << (1 + PPB_BC_BITBASE))
-#define PPB_BC_ISA_ENABLE (1U << (2 + PPB_BC_BITBASE))
-#define PPB_BC_VGA_ENABLE (1U << (3 + PPB_BC_BITBASE))
-#define PPB_BC_VGA16_ENABLE (1U << (4 + PPB_BC_BITBASE))
-#define PPB_BC_MASTER_ABORT_MODE (1U << (5 + PPB_BC_BITBASE))
-#define PPB_BC_SECONDARY_RESET (1U << (6 + PPB_BC_BITBASE))
-#define PPB_BC_FAST_B2B_ENABLE (1U << (7 + PPB_BC_BITBASE))
- /* PCI 2.2 */
-#define PPB_BC_PRIMARY_DISCARD_TIMEOUT (1U << (8 + PPB_BC_BITBASE))
-#define PPB_BC_SECONDARY_DISCARD_TIMEOUT (1U << (9 + PPB_BC_BITBASE))
-#define PPB_BC_DISCARD_TIMER_STATUS (1U << (10 + PPB_BC_BITBASE))
-#define PPB_BC_DISCARD_TIMER_SERR_ENABLE (1U << (11 + PPB_BC_BITBASE))
