Module Name: src
Committed By: maxv
Date: Thu Mar 7 14:40:35 UTC 2019
Modified Files:
src/sys/arch/amd64/include: pte.h
src/sys/arch/i386/include: pte.h
Log Message:
Introduce a new set of PTE bits, with a different naming convention.
PG_V -> PTE_P /* Present */
PG_RW -> PTE_W /* Write */
PG_u -> PTE_U /* User */
PG_WT -> PTE_PWT /* Write-Through */
PG_N -> PTE_PCD /* Cache-Disable */
PG_U -> PTE_A /* Accessed */
PG_M -> PTE_D /* Dirty */
PG_PAT -> PTE_PAT /* PAT on 4KB Pages */
PG_PS -> PTE_PS /* Large Page Size */
PG_G -> PTE_G /* Global Translation */
PG_AVAIL1 -> PTE_AVL1 /* Ignored by Hardware */
PG_AVAIL2 -> PTE_AVL2 /* Ignored by Hardware */
PG_AVAIL3 -> PTE_AVL3 /* Ignored by Hardware */
PG_LGPAT -> PTE_LGPAT /* PAT on Large Pages */
PG_NX -> PTE_NX /* No Execute */
Until now we were using "PG_BIT". The "BIT" part of the naming did not
follow the x86 naming convention in the spec, and was very confusing. We
don't want the "PG_" part of it either, because UVM has similar flags
(ie PG_BUSY).
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/amd64/include/pte.h
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/i386/include/pte.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/amd64/include/pte.h
diff -u src/sys/arch/amd64/include/pte.h:1.10 src/sys/arch/amd64/include/pte.h:1.11
--- src/sys/arch/amd64/include/pte.h:1.10 Thu Mar 7 13:26:24 2019
+++ src/sys/arch/amd64/include/pte.h Thu Mar 7 14:40:35 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.10 2019/03/07 13:26:24 maxv Exp $ */
+/* $NetBSD: pte.h,v 1.11 2019/03/07 14:40:35 maxv Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -95,7 +95,34 @@ typedef uint64_t pt_entry_t; /* PTE */
#define L1_FRAME (L2_FRAME|L1_MASK)
/*
+ * x86 PTE/PDE bits.
+ */
+#define PTE_P 0x0000000000000001 /* Present */
+#define PTE_W 0x0000000000000002 /* Write */
+#define PTE_U 0x0000000000000004 /* User */
+#define PTE_PWT 0x0000000000000008 /* Write-Through */
+#define PTE_PCD 0x0000000000000010 /* Cache-Disable */
+#define PTE_A 0x0000000000000020 /* Accessed */
+#define PTE_D 0x0000000000000040 /* Dirty */
+#define PTE_PAT 0x0000000000000080 /* PAT on 4KB Pages */
+#define PTE_PS 0x0000000000000080 /* Large Page Size */
+#define PTE_G 0x0000000000000100 /* Global Translation */
+#define PTE_AVL1 0x0000000000000200 /* Ignored by Hardware */
+#define PTE_AVL2 0x0000000000000400 /* Ignored by Hardware */
+#define PTE_AVL3 0x0000000000000800 /* Ignored by Hardware */
+#define PTE_LGPAT 0x0000000000001000 /* PAT on Large Pages */
+#define PTE_NX 0x8000000000000000 /* No Execute */
+
+#define PTE_4KFRAME 0x000ffffffffff000
+#define PTE_2MFRAME 0x000fffffffe00000
+#define PTE_1GFRAME 0x000fffffc0000000
+
+#define PTE_FRAME PTE_4KFRAME
+#define PTE_LGFRAME PTE_2MFRAME
+
+/*
* PDE/PTE bits. These are no different from their i386 counterparts.
+ * XXX To be deleted.
*/
#define PG_V 0x0000000000000001 /* valid */
#define PG_RW 0x0000000000000002 /* read-write */
@@ -113,14 +140,9 @@ typedef uint64_t pt_entry_t; /* PTE */
#define PG_LGPAT 0x0000000000001000 /* PAT on large pages */
#define PG_FRAME 0x000ffffffffff000
#define PG_NX 0x8000000000000000
-
#define PG_2MFRAME 0x000fffffffe00000 /* large (2M) page frame mask */
#define PG_1GFRAME 0x000fffffc0000000 /* large (1G) page frame mask */
#define PG_LGFRAME PG_2MFRAME
-
-/*
- * Short forms of protection codes.
- */
#define PG_KW 0x0000000000000002 /* kernel read-write */
#include <x86/pte.h>
Index: src/sys/arch/i386/include/pte.h
diff -u src/sys/arch/i386/include/pte.h:1.29 src/sys/arch/i386/include/pte.h:1.30
--- src/sys/arch/i386/include/pte.h:1.29 Thu Mar 7 13:26:24 2019
+++ src/sys/arch/i386/include/pte.h Thu Mar 7 14:40:35 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.29 2019/03/07 13:26:24 maxv Exp $ */
+/* $NetBSD: pte.h,v 1.30 2019/03/07 14:40:35 maxv Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -96,10 +96,6 @@ typedef uint32_t pt_entry_t; /* PTE */
#endif
-/*
- * now we define various for playing with virtual addresses
- */
-
#ifdef PAE
#define L1_SHIFT 12
#define L2_SHIFT 21
@@ -117,9 +113,16 @@ typedef uint32_t pt_entry_t; /* PTE */
#define L2_FRAME (L3_FRAME | L2_MASK)
#define L1_FRAME (L2_FRAME|L1_MASK)
+/* XXX To be deleted. */
#define PG_FRAME 0x000ffffffffff000ULL /* page frame mask */
#define PG_LGFRAME 0x000fffffffe00000ULL /* large (2MB) page frame mask */
+#define PTE_4KFRAME 0x000ffffffffff000ULL
+#define PTE_2MFRAME 0x000fffffffe00000ULL
+
+#define PTE_FRAME PTE_4KFRAME
+#define PTE_LGFRAME PTE_2MFRAME
+
/* macros to get real L2 and L3 index, from our "extended" L2 index */
#define l2tol3(idx) ((idx) >> (L3_SHIFT - L2_SHIFT))
#define l2tol2(idx) ((idx) & (L2_REALMASK >> L2_SHIFT))
@@ -137,15 +140,45 @@ typedef uint32_t pt_entry_t; /* PTE */
#define L2_FRAME (L2_MASK)
#define L1_FRAME (L2_FRAME|L1_MASK)
+/* XXX To be deleted. */
#define PG_FRAME 0xfffff000 /* page frame mask */
#define PG_LGFRAME 0xffc00000 /* large (4MB) page frame mask */
+#define PTE_4KFRAME 0xfffff000
+#define PTE_4MFRAME 0xffc00000
+
+#define PTE_FRAME PTE_4KFRAME
+#define PTE_LGFRAME PTE_4MFRAME
+
#endif /* PAE */
/*
+ * x86 PTE/PDE bits.
+ */
+#define PTE_P 0x00000001 /* Present */
+#define PTE_W 0x00000002 /* Write */
+#define PTE_U 0x00000004 /* User */
+#define PTE_PWT 0x00000008 /* Write-Through */
+#define PTE_PCD 0x00000010 /* Cache-Disable */
+#define PTE_A 0x00000020 /* Accessed */
+#define PTE_D 0x00000040 /* Dirty */
+#define PTE_PAT 0x00000080 /* PAT on 4KB Pages */
+#define PTE_PS 0x00000080 /* Large Page Size */
+#define PTE_G 0x00000100 /* Global Translation */
+#define PTE_AVL1 0x00000200 /* Ignored by Hardware */
+#define PTE_AVL2 0x00000400 /* Ignored by Hardware */
+#define PTE_AVL3 0x00000800 /* Ignored by Hardware */
+#define PTE_LGPAT 0x00001000 /* PAT on Large Pages */
+#ifdef PAE
+#define PTE_NX 0x8000000000000000ULL /* No Execute */
+#else
+#define PTE_NX 0 /* Dummy */
+#endif
+
+/*
* here we define the bits of the PDE/PTE, as described above:
- *
* XXXCDC: need to rename these (PG_u == ugly).
+ * XXX To be deleted.
*/
#define PG_V 0x00000001 /* valid entry */
#define PG_RW 0x00000002 /* read-write page */
@@ -161,12 +194,7 @@ typedef uint32_t pt_entry_t; /* PTE */
#define PG_AVAIL2 0x00000400 /* ignored by hardware */
#define PG_AVAIL3 0x00000800 /* ignored by hardware */
#define PG_LGPAT 0x00001000 /* PAT on large pages */
-
-/*
- * various short-hand protection codes
- */
#define PG_KW 0x00000002 /* kernel read-write */
-
#ifdef PAE
#define PG_NX 0x8000000000000000ULL /* No-execute */
#else
