Module Name: src
Committed By: msaitoh
Date: Thu Jan 9 10:54:16 UTC 2020
Modified Files:
src/sys/dev/pci: if_stge.c if_stgereg.h
Log Message:
Reduce diff against OpenBSD. No functional change.
- USE CSR_{READ,WRITE}_*() macro.
- Move some macros from if_stge.c to if_stgereg.h
To generate a diff of this commit:
cvs rdiff -u -r1.75 -r1.76 src/sys/dev/pci/if_stge.c
cvs rdiff -u -r1.7 -r1.8 src/sys/dev/pci/if_stgereg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/if_stge.c
diff -u src/sys/dev/pci/if_stge.c:1.75 src/sys/dev/pci/if_stge.c:1.76
--- src/sys/dev/pci/if_stge.c:1.75 Thu Dec 26 15:32:37 2019
+++ src/sys/dev/pci/if_stge.c Thu Jan 9 10:54:16 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: if_stge.c,v 1.75 2019/12/26 15:32:37 msaitoh Exp $ */
+/* $NetBSD: if_stge.c,v 1.76 2020/01/09 10:54:16 msaitoh Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.75 2019/12/26 15:32:37 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.76 2020/01/09 10:54:16 msaitoh Exp $");
#include <sys/param.h>
@@ -76,23 +76,6 @@ __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v
#define STGE_VLAN_UNTAG 1
/* #define STGE_VLAN_CFI 1 */
-#define STGE_CDOFF(x) offsetof(struct stge_control_data, x)
-#define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)])
-#define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)])
-
-#define STGE_RXCHAIN_RESET(sc) \
-do { \
- (sc)->sc_rxtailp = &(sc)->sc_rxhead; \
- *(sc)->sc_rxtailp = NULL; \
- (sc)->sc_rxlen = 0; \
-} while (/*CONSTCOND*/0)
-
-#define STGE_RXCHAIN_LINK(sc, m) \
-do { \
- *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \
- (sc)->sc_rxtailp = &(m)->m_next; \
-} while (/*CONSTCOND*/0)
-
#ifdef STGE_EVENT_COUNTERS
#define STGE_EVCNT_INCR(ev) (ev)->ev_count++
#else
@@ -129,8 +112,6 @@ do { \
STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \
} while (/*CONSTCOND*/0)
-#define STGE_TIMEOUT 1000
-
static void stge_start(struct ifnet *);
static void stge_watchdog(struct ifnet *);
static int stge_ioctl(struct ifnet *, u_long, void *);
@@ -403,8 +384,7 @@ stge_attach(device_t parent, device_t se
* Determine if we're copper or fiber. It affects how we
* reset the card.
*/
- if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) &
- AC_PhyMedia)
+ if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
sc->sc_usefiber = 1;
else
sc->sc_usefiber = 0;
@@ -422,18 +402,12 @@ stge_attach(device_t parent, device_t se
* from EEPROM.
*/
if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) {
- enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh,
- STGE_StationAddress0) & 0xff;
- enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh,
- STGE_StationAddress0) >> 8;
- enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh,
- STGE_StationAddress1) & 0xff;
- enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh,
- STGE_StationAddress1) >> 8;
- enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh,
- STGE_StationAddress2) & 0xff;
- enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh,
- STGE_StationAddress2) >> 8;
+ enaddr[0] = CSR_READ_2(sc, STGE_StationAddress0) & 0xff;
+ enaddr[1] = CSR_READ_2(sc, STGE_StationAddress0) >> 8;
+ enaddr[2] = CSR_READ_2(sc, STGE_StationAddress1) & 0xff;
+ enaddr[3] = CSR_READ_2(sc, STGE_StationAddress1) >> 8;
+ enaddr[4] = CSR_READ_2(sc, STGE_StationAddress2) & 0xff;
+ enaddr[5] = CSR_READ_2(sc, STGE_StationAddress2) >> 8;
sc->sc_stge1023 = 0;
} else {
data = prop_dictionary_get(device_properties(self),
@@ -466,8 +440,8 @@ stge_attach(device_t parent, device_t se
/*
* Read some important bits from the PhyCtrl register.
*/
- sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh,
- STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
+ sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
+ (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
/*
* Initialize our media structures and probe the MII.
@@ -643,8 +617,7 @@ stge_dma_wait(struct stge_softc *sc)
for (i = 0; i < STGE_TIMEOUT; i++) {
delay(2);
- if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) &
- DMAC_TxDMAInProg) == 0)
+ if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
break;
}
@@ -836,7 +809,7 @@ stge_start(struct ifnet *ifp)
/*
* Kick the transmit DMA logic.
*/
- bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl,
+ CSR_WRITE_4(sc, STGE_DMACtrl,
sc->sc_DMACtrl | DMAC_TxDMAPollNow);
/*
@@ -946,12 +919,11 @@ stge_intr(void *arg)
int wantinit;
uint16_t isr;
- if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) &
- IS_InterruptStatus) == 0)
+ if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0)
return (0);
for (wantinit = 0; wantinit == 0;) {
- isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck);
+ isr = CSR_READ_2(sc, STGE_IntStatusAck);
if ((isr & sc->sc_IntEnable) == 0)
break;
@@ -995,8 +967,7 @@ stge_intr(void *arg)
if (isr & IS_TxComplete) {
STGE_EVCNT_INCR(&sc->sc_ev_txindintr);
for (;;) {
- txstat = bus_space_read_4(sc->sc_st, sc->sc_sh,
- STGE_TxStatus);
+ txstat = CSR_READ_4(sc, STGE_TxStatus);
if ((txstat & TS_TxComplete) == 0)
break;
if (txstat & TS_TxUnderrun) {
@@ -1020,8 +991,7 @@ stge_intr(void *arg)
if (wantinit)
stge_init(ifp);
- bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable,
- sc->sc_IntEnable);
+ CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
/* Try to get more packets going. */
if_schedule_deferred_start(ifp);
@@ -1291,29 +1261,27 @@ static void
stge_stats_update(struct stge_softc *sc)
{
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
- bus_space_tag_t st = sc->sc_st;
- bus_space_handle_t sh = sc->sc_sh;
- (void) bus_space_read_4(st, sh, STGE_OctetRcvOk);
+ (void) CSR_READ_4(sc, STGE_OctetRcvOk);
- (void) bus_space_read_4(st, sh, STGE_FramesRcvdOk);
+ (void) CSR_READ_4(sc, STGE_FramesRcvdOk);
ifp->if_ierrors +=
- (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors);
+ (u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors);
- (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk);
+ (void) CSR_READ_4(sc, STGE_OctetXmtdOk);
ifp->if_opackets +=
- bus_space_read_4(st, sh, STGE_FramesXmtdOk);
+ CSR_READ_4(sc, STGE_FramesXmtdOk);
ifp->if_collisions +=
- bus_space_read_4(st, sh, STGE_LateCollisions) +
- bus_space_read_4(st, sh, STGE_MultiColFrames) +
- bus_space_read_4(st, sh, STGE_SingleColFrames);
+ CSR_READ_4(sc, STGE_LateCollisions) +
+ CSR_READ_4(sc, STGE_MultiColFrames) +
+ CSR_READ_4(sc, STGE_SingleColFrames);
ifp->if_oerrors +=
- (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) +
- (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal);
+ (u_int) CSR_READ_2(sc, STGE_FramesAbortXSColls) +
+ (u_int) CSR_READ_2(sc, STGE_FramesWEXDeferal);
}
/*
@@ -1327,14 +1295,14 @@ stge_reset(struct stge_softc *sc)
uint32_t ac;
int i;
- ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl);
+ ac = CSR_READ_4(sc, STGE_AsicCtrl);
/*
* Only assert RstOut if we're fiber. We need GMII clocks
* to be present in order for the reset to complete on fiber
* cards.
*/
- bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl,
+ CSR_WRITE_4(sc, STGE_AsicCtrl,
ac | AC_GlobalReset | AC_RxReset | AC_TxReset |
AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
(sc->sc_usefiber ? AC_RstOut : 0));
@@ -1343,8 +1311,7 @@ stge_reset(struct stge_softc *sc)
for (i = 0; i < STGE_TIMEOUT; i++) {
delay(5000);
- if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) &
- AC_ResetBusy) == 0)
+ if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
break;
}
@@ -1364,8 +1331,6 @@ static int
stge_init(struct ifnet *ifp)
{
struct stge_softc *sc = ifp->if_softc;
- bus_space_tag_t st = sc->sc_st;
- bus_space_handle_t sh = sc->sc_sh;
struct stge_descsoft *ds;
int i, error = 0;
@@ -1419,15 +1384,15 @@ stge_init(struct ifnet *ifp)
/* Set the station address. */
for (i = 0; i < 6; i++)
- bus_space_write_1(st, sh, STGE_StationAddress0 + i,
+ CSR_WRITE_1(sc, STGE_StationAddress0 + i,
CLLADDR(ifp->if_sadl)[i]);
/*
* Set the statistics masks. Disable all the RMON stats,
* and disable selected stats in the non-RMON stats registers.
*/
- bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff);
- bus_space_write_4(st, sh, STGE_StatisticsMask,
+ CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
+ CSR_WRITE_4(sc, STGE_StatisticsMask,
(1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
(1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
(1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
@@ -1439,12 +1404,12 @@ stge_init(struct ifnet *ifp)
/*
* Give the transmit and receive ring to the chip.
*/
- bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */
- bus_space_write_4(st, sh, STGE_TFDListPtrLo,
+ CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */
+ CSR_WRITE_4(sc, STGE_TFDListPtrLo,
STGE_CDTXADDR(sc, sc->sc_txdirty));
- bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */
- bus_space_write_4(st, sh, STGE_RFDListPtrLo,
+ CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */
+ CSR_WRITE_4(sc, STGE_RFDListPtrLo,
STGE_CDRXADDR(sc, sc->sc_rxptr));
/*
@@ -1452,24 +1417,24 @@ stge_init(struct ifnet *ifp)
* large (255 is the max, but we use 127) -- we explicitly kick the
* transmit engine when there's actually a packet.
*/
- bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127);
+ CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
/* ..and the Rx auto-poll period. */
- bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64);
+ CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64);
/* Initialize the Tx start threshold. */
- bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh);
+ CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
/* RX DMA thresholds, from linux */
- bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30);
- bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30);
+ CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
+ CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
/* Rx early threhold, from Linux */
- bus_space_write_2(st, sh, STGE_RxEarlyThresh, 0x7ff);
+ CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
/* Tx DMA thresholds, from Linux */
- bus_space_write_1(st, sh, STGE_TxDMABurstThresh, 0x30);
- bus_space_write_1(st, sh, STGE_TxDMAUrgentThresh, 0x04);
+ CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
+ CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
/*
* Initialize the Rx DMA interrupt control register. We
@@ -1478,7 +1443,7 @@ stge_init(struct ifnet *ifp)
* interrupts pending reaches 8, we stop deferring the
* interrupt, and signal it immediately.
*/
- bus_space_write_4(st, sh, STGE_RxDMAIntCtrl,
+ CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512));
/*
@@ -1486,14 +1451,14 @@ stge_init(struct ifnet *ifp)
*/
sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats |
IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
- bus_space_write_2(st, sh, STGE_IntStatus, 0xffff);
- bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable);
+ CSR_WRITE_2(sc, STGE_IntStatus, 0xffff);
+ CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
/*
* Configure the DMA engine.
* XXX Should auto-tune TxBurstLimit.
*/
- bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl |
+ CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl |
DMAC_TxBurstLimit(3));
/*
@@ -1501,13 +1466,13 @@ stge_init(struct ifnet *ifp)
* FIFO, and send an un-PAUSE frame when we reach 3056 bytes
* in the Rx FIFO.
*/
- bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16);
- bus_space_write_2(st, sh, STGE_FlowOffThresh, 3056 / 16);
+ CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
+ CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
/*
* Set the maximum frame size.
*/
- bus_space_write_2(st, sh, STGE_MaxFrameSize,
+ CSR_WRITE_2(sc, STGE_MaxFrameSize,
ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
ETHER_VLAN_ENCAP_LEN : 0));
@@ -1520,7 +1485,7 @@ stge_init(struct ifnet *ifp)
* anything else.
*/
sc->sc_MACCtrl = MC_IFSSelect(0);
- bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl);
+ CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl);
sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
#ifdef STGE_VLAN_UNTAG
sc->sc_MACCtrl |= MC_AutoVLANuntagging;
@@ -1528,15 +1493,15 @@ stge_init(struct ifnet *ifp)
if (sc->sc_rev >= 6) { /* >= B.2 */
/* Multi-frag frame bug work-around. */
- bus_space_write_2(st, sh, STGE_DebugCtrl,
- bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200);
+ CSR_WRITE_2(sc, STGE_DebugCtrl,
+ CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
/* Tx Poll Now bug work-around. */
- bus_space_write_2(st, sh, STGE_DebugCtrl,
- bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010);
+ CSR_WRITE_2(sc, STGE_DebugCtrl,
+ CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
/* XXX ? from linux */
- bus_space_write_2(st, sh, STGE_DebugCtrl,
- bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020);
+ CSR_WRITE_2(sc, STGE_DebugCtrl,
+ CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
}
/*
@@ -1607,22 +1572,22 @@ stge_stop(struct ifnet *ifp, int disable
/*
* Disable interrupts.
*/
- bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0);
+ CSR_WRITE_2(sc, STGE_IntEnable, 0);
/*
* Stop receiver, transmitter, and stats update.
*/
- bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl,
+ CSR_WRITE_4(sc, STGE_MACCtrl,
MC_StatisticsDisable | MC_TxDisable | MC_RxDisable);
/*
* Stop the transmit and receive DMA.
*/
stge_dma_wait(sc);
- bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0);
- bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0);
- bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0);
- bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0);
+ CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
+ CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
+ CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
+ CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
/*
* Release any queued transmit buffers.
@@ -1653,8 +1618,7 @@ stge_eeprom_wait(struct stge_softc *sc)
for (i = 0; i < STGE_TIMEOUT; i++) {
delay(1000);
- if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) &
- EC_EepromBusy) == 0)
+ if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
return (0);
}
return (1);
@@ -1673,12 +1637,12 @@ stge_read_eeprom(struct stge_softc *sc,
printf("%s: EEPROM failed to come ready\n",
device_xname(sc->sc_dev));
- bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl,
+ CSR_WRITE_2(sc, STGE_EepromCtrl,
EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
if (stge_eeprom_wait(sc))
printf("%s: EEPROM read timed out\n",
device_xname(sc->sc_dev));
- *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData);
+ *data = CSR_READ_2(sc, STGE_EepromData);
}
/*
@@ -1812,14 +1776,11 @@ stge_set_filter(struct stge_softc *sc)
/*
* Program the multicast hash table.
*/
- bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0,
- mchash[0]);
- bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1,
- mchash[1]);
+ CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
+ CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
}
- bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode,
- sc->sc_ReceiveMode);
+ CSR_WRITE_2(sc, STGE_ReceiveMode, sc->sc_ReceiveMode);
}
/*
@@ -1867,7 +1828,7 @@ stge_mii_statchg(struct ifnet *ifp)
if ((sc->sc_mii.mii_media_active & IFM_ETH_TXPAUSE) != 0)
sc->sc_MACCtrl |= MC_TxFlowControlEnable;
- bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl);
+ CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl);
}
/*
@@ -1880,7 +1841,7 @@ stge_mii_bitbang_read(device_t self)
{
struct stge_softc *sc = device_private(self);
- return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl));
+ return (CSR_READ_1(sc, STGE_PhyCtrl));
}
/*
@@ -1893,6 +1854,5 @@ stge_mii_bitbang_write(device_t self, ui
{
struct stge_softc *sc = device_private(self);
- bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl,
- val | sc->sc_PhyCtrl);
+ CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl);
}
Index: src/sys/dev/pci/if_stgereg.h
diff -u src/sys/dev/pci/if_stgereg.h:1.7 src/sys/dev/pci/if_stgereg.h:1.8
--- src/sys/dev/pci/if_stgereg.h:1.7 Thu Dec 26 15:23:11 2019
+++ src/sys/dev/pci/if_stgereg.h Thu Jan 9 10:54:16 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: if_stgereg.h,v 1.7 2019/12/26 15:23:11 msaitoh Exp $ */
+/* $NetBSD: if_stgereg.h,v 1.8 2020/01/09 10:54:16 msaitoh Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -45,6 +45,23 @@
*/
/*
+ * Register access macros
+ */
+#define CSR_WRITE_4(_sc, reg, val) \
+ bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
+#define CSR_WRITE_2(_sc, reg, val) \
+ bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
+#define CSR_WRITE_1(_sc, reg, val) \
+ bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val))
+
+#define CSR_READ_4(_sc, reg) \
+ bus_space_read_4((_sc)->sc_st, (_sc)->sc_sh, (reg))
+#define CSR_READ_2(_sc, reg) \
+ bus_space_read_2((_sc)->sc_st, (_sc)->sc_sh, (reg))
+#define CSR_READ_1(_sc, reg) \
+ bus_space_read_1((_sc)->sc_st, (_sc)->sc_sh, (reg))
+
+/*
* TC9021 buffer fragment descriptor.
*/
struct stge_frag {
@@ -490,6 +507,10 @@ struct stge_control_data {
struct stge_rfd scd_rxdescs[STGE_NRXDESC];
};
+#define STGE_CDOFF(x) offsetof(struct stge_control_data, x)
+#define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)])
+#define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)])
+
/*
* Software state for transmit and receive jobs.
*/
@@ -578,4 +599,19 @@ struct stge_softc {
uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */
};
+#define STGE_RXCHAIN_RESET(sc) \
+do { \
+ (sc)->sc_rxtailp = &(sc)->sc_rxhead; \
+ *(sc)->sc_rxtailp = NULL; \
+ (sc)->sc_rxlen = 0; \
+} while (/*CONSTCOND*/0)
+
+#define STGE_RXCHAIN_LINK(sc, m) \
+do { \
+ *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \
+ (sc)->sc_rxtailp = &(m)->m_next; \
+} while (/*CONSTCOND*/0)
+
+#define STGE_TIMEOUT 1000
+
#endif /* _DEV_PCI_IF_STGEREG_H_ */
