Module Name: src
Committed By: msaitoh
Date: Sat Jan 25 08:13:39 UTC 2020
Modified Files:
src/sys/dev/pci: pci_subr.c pcireg.h
Log Message:
Add PCIe 4.0 stuff a little:
- 10-bit Tag Requester/Completer.
- Add Data link Feature extended capability.
- Add Physical Layer 16.0 GT/s extended capability. Not decode yet.
To generate a diff of this commit:
cvs rdiff -u -r1.220 -r1.221 src/sys/dev/pci/pci_subr.c
cvs rdiff -u -r1.149 -r1.150 src/sys/dev/pci/pcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pci_subr.c
diff -u src/sys/dev/pci/pci_subr.c:1.220 src/sys/dev/pci/pci_subr.c:1.221
--- src/sys/dev/pci/pci_subr.c:1.220 Sat Jan 25 07:59:14 2020
+++ src/sys/dev/pci/pci_subr.c Sat Jan 25 08:13:39 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.220 2020/01/25 07:59:14 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.221 2020/01/25 08:13:39 msaitoh Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.220 2020/01/25 07:59:14 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.221 2020/01/25 08:13:39 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -2165,6 +2165,8 @@ pci_conf_print_pcie_cap(const pcireg_t *
printf("Reserved\n");
break;
}
+ onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP);
+ onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ);
printf(" OBFF Supported: ");
switch (__SHIFTOUT(reg, PCIE_DCAP2_OBFF)) {
case 0x0:
@@ -2217,6 +2219,7 @@ pci_conf_print_pcie_cap(const pcireg_t *
onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC);
onoff("Emergency Power Reduction Request", reg,
PCIE_DCSR2_EMGPWRRED_REQ);
+ onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ);
printf(" OBFF: ");
switch (__SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) {
case 0x0:
@@ -4165,6 +4168,24 @@ pci_conf_print_ptm_cap(const pcireg_t *r
/* XXX pci_conf_print_rtr_cap */
/* XXX pci_conf_print_desigvndsp_cap */
/* XXX pci_conf_print_vf_resizbar_cap */
+
+static void
+pci_conf_print_dlf_cap(const pcireg_t *regs, int extcapoff)
+{
+ pcireg_t reg;
+
+ printf("\n Data link Feature Register\n");
+ reg = regs[o2i(extcapoff + PCI_DLF_CAP)];
+ printf(" Capability register: 0x%08x\n", reg);
+ onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL);
+ onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG);
+
+ reg = regs[o2i(extcapoff + PCI_DLF_STAT)];
+ printf(" Status register: 0x%08x\n", reg);
+ onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL);
+ onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID);
+}
+
/* XXX pci_conf_print_hierarchyid_cap */
/* XXX pci_conf_print_npem_cap */
@@ -4251,8 +4272,8 @@ static struct {
NULL },
{ PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs",
NULL },
- { 0x25, "unknown", NULL },
- { 0x26, "unknown", NULL },
+ { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap },
+ { PCI_EXTCAP_PYSLAY_16GT, "Physical Layer 16.0 GT/s", NULL },
{ 0x27, "unknown", NULL },
{ PCI_EXTCAP_HIERARCHYID, "Hierarchy ID",
NULL },
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.149 src/sys/dev/pci/pcireg.h:1.150
--- src/sys/dev/pci/pcireg.h:1.149 Wed Jan 22 02:51:38 2020
+++ src/sys/dev/pci/pcireg.h Sat Jan 25 08:13:39 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.149 2020/01/22 02:51:38 msaitoh Exp $ */
+/* $NetBSD: pcireg.h,v 1.150 2020/01/25 08:13:39 msaitoh Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -1097,6 +1097,8 @@ typedef u_int8_t pci_revision_t;
#define PCIE_DCAP2_LTR_MEC __BIT(11) /* LTR Mechanism Supported */
#define PCIE_DCAP2_TPH_COMP __BITS(13, 12) /* TPH Completer Supported */
#define PCIE_DCAP2_LNSYSCLS __BITS(15, 14) /* LN System CLS */
+#define PCIE_DCAP2_TBT_COMP __BIT(16) /* 10-bit Tag Completer Supp. */
+#define PCIE_DCAP2_TBT_REQ __BIT(17) /* 10-bit Tag Requester Supp. */
#define PCIE_DCAP2_OBFF __BITS(19, 18) /* Optimized Buffer Flush/Fill*/
#define PCIE_DCAP2_EXTFMT_FLD __BIT(20) /* Extended Fmt Field Support */
#define PCIE_DCAP2_EETLP_PREF __BIT(21) /* End-End TLP Prefix Support */
@@ -1114,6 +1116,7 @@ typedef u_int8_t pci_revision_t;
#define PCIE_DCSR2_IDO_COMP __BIT(9) /* IDO Completion Enable */
#define PCIE_DCSR2_LTR_MEC __BIT(10) /* LTR Mechanism Enable */
#define PCIE_DCSR2_EMGPWRRED_REQ __BIT(11) /* Emergency Power Reduc. Req */
+#define PCIE_DCSR2_TBT_REQ __BIT(12) /* 10-bit Tag Requester Ena. */
#define PCIE_DCSR2_OBFF_EN __BITS(14, 13) /* OBFF Enable */
#define PCIE_DCSR2_EETLP __BIT(15) /* End-End TLP Prefix Blcking */
#define PCIE_LCAP2 0x2c /* Link Capabilities 2 Register */
@@ -1525,6 +1528,8 @@ struct pci_rom {
#define PCI_EXTCAP_RTR 0x0022 /* Readiness Time Reporting */
#define PCI_EXTCAP_DESIGVNDSP 0x0023 /* Designated Vendor-Specific */
#define PCI_EXTCAP_VF_RESIZBAR 0x0024 /* VF Resizable BAR */
+#define PCI_EXTCAP_DLF 0x0025 /* Data link Feature */
+#define PCI_EXTCAP_PYSLAY_16GT 0x0026 /* Physical Layer 16.0 GT/s */
#define PCI_EXTCAP_HIERARCHYID 0x0028 /* Hierarchy ID */
#define PCI_EXTCAP_NPEM 0x0029 /* Native PCIe Enclosure Management */
@@ -2151,6 +2156,23 @@ struct pci_rom {
*/
/*
+ * Extended capability ID: 0x0025
+ * Data link Feature
+ */
+#define PCI_DLF_CAP 0x04 /* Capability register */
+#define PCI_DLF_LFEAT __BITS(22, 0) /* Local DLF supported */
+#define PCI_DLF_LFEAT_SCLFCTL __BIT(0) /* Scaled Flow Control */
+#define PCI_DLF_CAP_XCHG __BIT(31) /* DLF Exchange enable */
+#define PCI_DLF_STAT 0x08 /* Status register */
+ /* Bit 22:0 is the same as PCI_DLF_CAP_LINKFEAT */
+#define PCI_DLF_STAT_RMTVALID __BIT(31) /* Remote DLF supported Valid */
+
+/*
+ * Extended capability ID: 0x0026
+ * Physical Layer 16.0 GT/s
+ */
+
+/*
* Extended capability ID: 0x0028
* Hierarchy ID
*/
