Module Name:    src
Committed By:   maxv
Date:           Fri Jan 31 09:23:58 UTC 2020

Modified Files:
        src/sys/arch/aarch64/aarch64: trap.c
        src/sys/arch/aarch64/include: armreg.h pte.h

Log Message:
BTI definitions.


To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/aarch64/aarch64/trap.c
cvs rdiff -u -r1.34 -r1.35 src/sys/arch/aarch64/include/armreg.h
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/aarch64/include/pte.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.24 src/sys/arch/aarch64/aarch64/trap.c:1.25
--- src/sys/arch/aarch64/aarch64/trap.c:1.24	Mon Jan  6 08:36:08 2020
+++ src/sys/arch/aarch64/aarch64/trap.c	Fri Jan 31 09:23:58 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.24 2020/01/06 08:36:08 skrll Exp $ */
+/* $NetBSD: trap.c,v 1.25 2020/01/31 09:23:58 maxv Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.24 2020/01/06 08:36:08 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.25 2020/01/31 09:23:58 maxv Exp $");
 
 #include "opt_arm_intr_impl.h"
 #include "opt_compat_netbsd32.h"
@@ -94,6 +94,8 @@ const char * const trap_names[] = {
 	[ESR_EC_WFX]		= "WFI or WFE instruction execution",
 	[ESR_EC_ILL_STATE]	= "Illegal Execution State",
 
+	[ESR_EC_BTE_A64]	= "Branch Target Exception",
+
 	[ESR_EC_SYS_REG]	= "MSR/MRS/SYS instruction",
 	[ESR_EC_SVC_A64]	= "SVC Instruction Execution",
 	[ESR_EC_HVC_A64]	= "HVC Instruction Execution",

Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.34 src/sys/arch/aarch64/include/armreg.h:1.35
--- src/sys/arch/aarch64/include/armreg.h:1.34	Tue Jan 28 18:02:30 2020
+++ src/sys/arch/aarch64/include/armreg.h	Fri Jan 31 09:23:58 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.34 2020/01/28 18:02:30 maxv Exp $ */
+/* $NetBSD: armreg.h,v 1.35 2020/01/31 09:23:58 maxv Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -547,6 +547,7 @@ AARCH64REG_WRITE_INLINE(esr_el1)
 #define	 ESR_EC_FP_ACCESS	 0x07	// AXX: Access to SIMD/FP Registers
 #define	 ESR_EC_FPID		 0x08	// A32: MCR/MRC access to CP10 !EC=7
 #define	 ESR_EC_CP14_RRT	 0x0c	// A32: MRRC access to CP14
+#define	 ESR_EC_BTE_A64		 0x0d	// A64: Branch Target Exception (V8.5)
 #define	 ESR_EC_ILL_STATE	 0x0e	// AXX: Illegal Execution State
 #define	 ESR_EC_SVC_A32		 0x11	// A32: SVC Instruction Execution
 #define	 ESR_EC_HVC_A32		 0x12	// A32: HVC Instruction Execution
@@ -778,6 +779,7 @@ AARCH64REG_WRITE_INLINE(spsr_el1)
 #define	SPSR_IT4 		__BIT(12)	// A32: IT[4]
 #define	SPSR_IT3 		__BIT(11)	// A32: IT[3]
 #define	SPSR_IT2 		__BIT(10)	// A32: IT[2]
+#define	SPSR_A64_BTYPE 		__BIT(11,10)	// A64: BTYPE
 #define	SPSR_A64_D 		__BIT(9)	// A64: Debug Exception Mask
 #define	SPSR_A32_E 		__BIT(9)	// A32: BE Endian Mode
 #define	SPSR_A	 		__BIT(8)	// Async abort (SError) Mask

Index: src/sys/arch/aarch64/include/pte.h
diff -u src/sys/arch/aarch64/include/pte.h:1.10 src/sys/arch/aarch64/include/pte.h:1.11
--- src/sys/arch/aarch64/include/pte.h:1.10	Wed Sep 11 18:23:31 2019
+++ src/sys/arch/aarch64/include/pte.h	Fri Jan 31 09:23:58 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.10 2019/09/11 18:23:31 skrll Exp $ */
+/* $NetBSD: pte.h,v 1.11 2020/01/31 09:23:58 maxv Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -65,6 +65,7 @@ typedef uint64_t pt_entry_t;	/* L3(4k) t
 #define LX_BLKPAG_PXN		__BIT(53)	/* Privileged Execute Never */
 #define LX_BLKPAG_CONTIG	__BIT(52)	/* Hint of TLB cache */
 #define LX_BLKPAG_DBM		__BIT(51)	/* Dirty Bit Modifier (V8.1) */
+#define LX_BLKPAG_GP		__BIT(50)	/* Guarded Page (V8.5) */
 #define LX_TBL_PA		__BITS(47, 12)
 #define LX_BLKPAG_OA		__BITS(47, 12)
 #define LX_BLKPAG_NG		__BIT(11)	/* Not Global */

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