Module Name: src Committed By: martin Date: Fri Jan 31 11:25:09 UTC 2020
Modified Files: src/sys/external/bsd/drm2/dist/drm/i915 [netbsd-9]: i915_reg.h intel_pm.c src/sys/external/bsd/drm2/dist/drm/radeon [netbsd-9]: cikd.h evergreend.h nid.h r600d.h radeon_mode.h radeon_r600.c radeon_reg.h radeon_rv770_smc.c radeon_si_smc.c radeon_uvd_v1_0.c radeon_uvd_v2_2.c radeon_uvd_v4_2.c rv730d.h rv770d.h sid.h sumod.h src/sys/external/bsd/drm2/dist/include/drm [netbsd-9]: drm_fixed.h Log Message: Pull up following revision(s) (requested by msaitoh in ticket #677): sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c: revision 1.2 sys/external/bsd/drm2/dist/drm/i915/intel_pm.c: revision 1.18 sys/external/bsd/drm2/dist/drm/radeon/nid.h: revision 1.3 sys/external/bsd/drm2/dist/drm/i915/intel_pm.c: revision 1.19 sys/external/bsd/drm2/dist/drm/radeon/rv770d.h: revision 1.3 sys/external/bsd/drm2/dist/drm/radeon/cikd.h: revision 1.3 sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c: revision 1.2 sys/external/bsd/drm2/dist/include/drm/drm_fixed.h: revision 1.3 sys/external/bsd/drm2/dist/drm/radeon/sumod.h: revision 1.3 sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h: revision 1.3 sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h: revision 1.5 sys/external/bsd/drm2/dist/drm/radeon/r600d.h: revision 1.3 sys/external/bsd/drm2/dist/drm/radeon/r600d.h: revision 1.4 sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c: revision 1.2 sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c: revision 1.3 sys/external/bsd/drm2/dist/drm/radeon/radeon_r600.c: revision 1.2 sys/external/bsd/drm2/dist/drm/radeon/evergreend.h: revision 1.3 sys/external/bsd/drm2/dist/drm/radeon/evergreend.h: revision 1.4 sys/external/bsd/drm2/dist/drm/i915/i915_reg.h: revision 1.10 sys/external/bsd/drm2/dist/drm/i915/i915_reg.h: revision 1.8 sys/external/bsd/drm2/dist/drm/i915/i915_reg.h: revision 1.11 sys/external/bsd/drm2/dist/drm/i915/i915_reg.h: revision 1.13 sys/external/bsd/drm2/dist/drm/radeon/rv730d.h: revision 1.3 sys/external/bsd/drm2/dist/drm/radeon/radeon_rv770_smc.c: revision 1.2 sys/external/bsd/drm2/dist/drm/radeon/sid.h: revision 1.3 sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c: revision 1.2 sys/external/bsd/drm2/dist/drm/radeon/sid.h: revision 1.4 Use unsigned to avoid undefined behavior. Found by kUBSan. To generate a diff of this commit: cvs rdiff -u -r1.7.2.1 -r1.7.2.2 \ src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h cvs rdiff -u -r1.17.2.1 -r1.17.2.2 \ src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c cvs rdiff -u -r1.2 -r1.2.4.1 src/sys/external/bsd/drm2/dist/drm/radeon/cikd.h \ src/sys/external/bsd/drm2/dist/drm/radeon/evergreend.h \ src/sys/external/bsd/drm2/dist/drm/radeon/nid.h \ src/sys/external/bsd/drm2/dist/drm/radeon/r600d.h \ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h \ src/sys/external/bsd/drm2/dist/drm/radeon/rv730d.h \ src/sys/external/bsd/drm2/dist/drm/radeon/rv770d.h \ src/sys/external/bsd/drm2/dist/drm/radeon/sid.h \ src/sys/external/bsd/drm2/dist/drm/radeon/sumod.h cvs rdiff -u -r1.4 -r1.4.4.1 \ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h cvs rdiff -u -r1.1 -r1.1.8.1 \ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_r600.c \ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_rv770_smc.c \ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c \ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c \ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c \ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c cvs rdiff -u -r1.2 -r1.2.4.1 \ src/sys/external/bsd/drm2/dist/include/drm/drm_fixed.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h diff -u src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h:1.7.2.1 src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h:1.7.2.2 --- src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h:1.7.2.1 Thu Dec 12 21:00:32 2019 +++ src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: i915_reg.h,v 1.7.2.1 2019/12/12 21:00:32 martin Exp $ */ +/* $NetBSD: i915_reg.h,v 1.7.2.2 2020/01/31 11:25:09 martin Exp $ */ /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. * All Rights Reserved. @@ -1652,7 +1652,7 @@ enum skl_disp_power_wells { #define ERROR_GEN6 0x040a0 #define GEN7_ERR_INT 0x44040 -#define ERR_INT_POISON (1<<31) +#define ERR_INT_POISON (1U<<31) #define ERR_INT_MMIO_UNCLAIMED (1<<13) #define ERR_INT_PIPE_CRC_DONE_C (1<<8) #define ERR_INT_FIFO_UNDERRUN_C (1<<6) @@ -1792,7 +1792,7 @@ enum skl_disp_power_wells { #define FW_BLC_SELF 0x020e0 /* 915+ only */ #define FW_BLC_SELF_EN_MASK (1<<31) #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ -#define FW_BLC_SELF_EN (1<<15) /* 945 only */ +#define FW_BLC_SELF_EN (1U<<15) /* 945 only */ #define MM_BURST_LENGTH 0x00700000 #define MM_FIFO_WATERMARK 0x0001F000 #define LM_BURST_LENGTH 0x00000700 @@ -2039,7 +2039,7 @@ enum skl_disp_power_wells { #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ #define FBC_LL_BASE 0x03204 /* 4k page aligned */ #define FBC_CONTROL 0x03208 -#define FBC_CTL_EN (1<<31) +#define FBC_CTL_EN __BIT(31) #define FBC_CTL_PERIODIC (1<<30) #define FBC_CTL_INTERVAL_SHIFT (16) #define FBC_CTL_UNCOMPRESSIBLE (1<<14) @@ -2232,7 +2232,7 @@ enum skl_disp_power_wells { #define VGA1_PD_P1_DIV_2 (1 << 13) #define VGA1_PD_P1_SHIFT 8 #define VGA1_PD_P1_MASK (0x1f << 8) -#define DPLL_VCO_ENABLE (1 << 31) +#define DPLL_VCO_ENABLE __BIT(31) #define DPLL_SDVO_HIGH_SPEED (1 << 30) #define DPLL_DVO_2X_MODE (1 << 30) #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) @@ -3182,7 +3182,7 @@ enum skl_disp_power_wells { #define PCH_ADPA 0xe1100 #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) -#define ADPA_DAC_ENABLE (1<<31) +#define ADPA_DAC_ENABLE __BIT(31) #define ADPA_DAC_DISABLE 0 #define ADPA_PIPE_SELECT_MASK (1<<30) #define ADPA_PIPE_A_SELECT 0 @@ -3344,7 +3344,7 @@ enum skl_disp_power_wells { #define PIPE_A_SCRAMBLE_RESET (1 << 0) /* Gen 3 SDVO bits: */ -#define SDVO_ENABLE (1 << 31) +#define SDVO_ENABLE __BIT(31) #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) #define SDVO_PIPE_SEL_MASK (1 << 30) #define SDVO_PIPE_B_SELECT (1 << 30) @@ -3435,7 +3435,7 @@ enum skl_disp_power_wells { * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ -#define LVDS_PORT_EN (1 << 31) +#define LVDS_PORT_EN (1U << 31) /* Selects pipe B for LVDS data. Must be set on pre-965. */ #define LVDS_PIPEB_SELECT (1 << 30) #define LVDS_PIPE_MASK (1 << 30) @@ -3488,7 +3488,7 @@ enum skl_disp_power_wells { #define VIDEO_DIP_VSC_DATA_SIZE 36 #define VIDEO_DIP_CTL 0x61170 /* Pre HSW: */ -#define VIDEO_DIP_ENABLE (1 << 31) +#define VIDEO_DIP_ENABLE (1U << 31) #define VIDEO_DIP_PORT(port) ((port) << 29) #define VIDEO_DIP_PORT_MASK (3 << 29) #define VIDEO_DIP_ENABLE_GCP (1 << 25) @@ -3547,7 +3547,7 @@ enum skl_disp_power_wells { /* Panel fitting */ #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230) -#define PFIT_ENABLE (1 << 31) +#define PFIT_ENABLE __BIT(31) #define PFIT_PIPE_MASK (3 << 29) #define PFIT_PIPE_SHIFT 29 #define VERT_INTERP_DISABLE (0 << 10) @@ -3595,7 +3595,7 @@ enum skl_disp_power_wells { /* Backlight control */ #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ -#define BLM_PWM_ENABLE (1 << 31) +#define BLM_PWM_ENABLE __BIT(31) #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ #define BLM_PIPE_SELECT (1 << 29) #define BLM_PIPE_SELECT_IVB (3 << 29) @@ -3652,7 +3652,7 @@ enum skl_disp_power_wells { /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ #define BLC_PWM_PCH_CTL1 0xc8250 -#define BLM_PCH_PWM_ENABLE (1 << 31) +#define BLM_PCH_PWM_ENABLE __BIT(31) #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) #define BLM_PCH_POLARITY (1 << 29) #define BLC_PWM_PCH_CTL2 0xc8254 @@ -3690,7 +3690,7 @@ enum skl_disp_power_wells { /* TV port control */ #define TV_CTL 0x68000 /* Enables the TV encoder */ -# define TV_ENC_ENABLE (1 << 31) +# define TV_ENC_ENABLE (1U << 31) /* Sources the TV encoder input from pipe B instead of A. */ # define TV_ENC_PIPEB_SELECT (1 << 30) /* Outputs composite video (DAC A only) */ @@ -3889,7 +3889,7 @@ enum skl_disp_power_wells { #define TV_H_CTL_2 0x68034 /* Enables the colorburst (needed for non-component color) */ -# define TV_BURST_ENA (1 << 31) +# define TV_BURST_ENA (1U << 31) /* Offset of the colorburst from the start of hsync, in pixels minus one. */ # define TV_HBURST_START_SHIFT 16 # define TV_HBURST_START_MASK 0x1fff0000 @@ -3934,7 +3934,7 @@ enum skl_disp_power_wells { #define TV_V_CTL_3 0x68044 /* Enables generation of the equalization signal */ -# define TV_EQUAL_ENA (1 << 31) +# define TV_EQUAL_ENA (1U << 31) /* Length of vsync, in half lines */ # define TV_VEQ_LEN_MASK 0x007f0000 # define TV_VEQ_LEN_SHIFT 16 @@ -4008,7 +4008,7 @@ enum skl_disp_power_wells { #define TV_SC_CTL_1 0x68060 /* Turns on the first subcarrier phase generation DDA */ -# define TV_SC_DDA1_EN (1 << 31) +# define TV_SC_DDA1_EN (1U << 31) /* Turns on the first subcarrier phase generation DDA */ # define TV_SC_DDA2_EN (1 << 30) /* Turns on the first subcarrier phase generation DDA */ @@ -4071,7 +4071,7 @@ enum skl_disp_power_wells { * If set, the rest of the registers are ignored, and the calculated values can * be read back from the register. */ -# define TV_AUTO_SCALE (1 << 31) +# define TV_AUTO_SCALE (1U << 31) /* * Disables the vertical filter. * @@ -4173,7 +4173,7 @@ enum skl_disp_power_wells { #define VLV_DP_C (VLV_DISPLAY_BASE + DP_C) #define CHV_DP_D (VLV_DISPLAY_BASE + DP_D) -#define DP_PORT_EN (1 << 31) +#define DP_PORT_EN __BIT(31) #define DP_PIPEB_SELECT (1 << 30) #define DP_PIPE_MASK (1 << 30) #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) @@ -4590,7 +4590,7 @@ enum skl_disp_power_wells { /* pnv/gen4/g4x/vlv/chv */ #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) #define DSPFW_SR_SHIFT 23 -#define DSPFW_SR_MASK (0x1ff<<23) +#define DSPFW_SR_MASK (0x1ffU<<23) #define DSPFW_CURSORB_SHIFT 16 #define DSPFW_CURSORB_MASK (0x3f<<16) #define DSPFW_PLANEB_SHIFT 8 @@ -5059,7 +5059,7 @@ enum skl_disp_power_wells { /* Sprite A control */ #define _DVSACNTR 0x72180 -#define DVS_ENABLE (1<<31) +#define DVS_ENABLE __BIT(31) #define DVS_GAMMA_ENABLE (1<<30) #define DVS_PIXFORMAT_MASK (3<<25) #define DVS_FORMAT_YUV422 (0<<25) @@ -5466,7 +5466,7 @@ enum skl_disp_power_wells { /* VBIOS regs */ #define VGACNTRL 0x71400 -# define VGA_DISP_DISABLE (1 << 31) +# define VGA_DISP_DISABLE __BIT(31) # define VGA_2X_MODE (1 << 30) # define VGA_PIPE_B_SELECT (1 << 29) @@ -6102,7 +6102,7 @@ enum skl_disp_power_wells { #define SDEIER 0xc400c #define SERR_INT 0xc4040 -#define SERR_INT_POISON (1<<31) +#define SERR_INT_POISON (1U<<31) #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) @@ -6378,7 +6378,7 @@ enum skl_disp_power_wells { #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */ #define TRANS_DISABLE (0<<31) -#define TRANS_ENABLE (1<<31) +#define TRANS_ENABLE __BIT(31) #define TRANS_STATE_MASK (1<<30) #define TRANS_STATE_DISABLE (0<<30) #define TRANS_STATE_ENABLE (1<<30) @@ -6403,7 +6403,7 @@ enum skl_disp_power_wells { #define _TRANSA_CHICKEN2 0xf0064 #define _TRANSB_CHICKEN2 0xf1064 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) -#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) +#define TRANS_CHICKEN2_TIMING_OVERRIDE __BIT(31) #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) @@ -6439,7 +6439,7 @@ enum skl_disp_power_wells { #define _FDI_TXB_CTL 0x61100 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) #define FDI_TX_DISABLE (0<<31) -#define FDI_TX_ENABLE (1<<31) +#define FDI_TX_ENABLE __BIT(31) #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) @@ -6488,7 +6488,7 @@ enum skl_disp_power_wells { #define _FDI_RXA_CTL 0xf000c #define _FDI_RXB_CTL 0xf100c #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) -#define FDI_RX_ENABLE (1<<31) +#define FDI_RX_ENABLE __BIT(31) /* train, dp width same as FDI_TX */ #define FDI_FS_ERRC_ENABLE (1<<27) #define FDI_FE_ERRC_ENABLE (1<<26) @@ -6593,11 +6593,11 @@ enum skl_disp_power_wells { #define PANEL_POWER_OFF (0 << 0) #define PANEL_POWER_ON (1 << 0) #define PCH_PP_ON_DELAYS 0xc7208 -#define PANEL_PORT_SELECT_MASK (3 << 30) -#define PANEL_PORT_SELECT_LVDS (0 << 30) -#define PANEL_PORT_SELECT_DPA (1 << 30) -#define PANEL_PORT_SELECT_DPC (2 << 30) -#define PANEL_PORT_SELECT_DPD (3 << 30) +#define PANEL_PORT_SELECT_MASK (3U << 30) +#define PANEL_PORT_SELECT_LVDS (0U << 30) +#define PANEL_PORT_SELECT_DPA (1U << 30) +#define PANEL_PORT_SELECT_DPC (2U << 30) +#define PANEL_PORT_SELECT_DPD (3U << 30) #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) #define PANEL_POWER_UP_DELAY_SHIFT 16 #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) @@ -6665,7 +6665,7 @@ enum skl_disp_power_wells { #define TRANS_DP_CTL_B 0xe1300 #define TRANS_DP_CTL_C 0xe2300 #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) -#define TRANS_DP_OUTPUT_ENABLE (1<<31) +#define TRANS_DP_OUTPUT_ENABLE __BIT(31) #define TRANS_DP_PORT_SEL_B (0<<29) #define TRANS_DP_PORT_SEL_C (1<<29) #define TRANS_DP_PORT_SEL_D (2<<29) Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c:1.17.2.1 src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c:1.17.2.2 --- src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c:1.17.2.1 Thu Dec 12 21:00:32 2019 +++ src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: intel_pm.c,v 1.17.2.1 2019/12/12 21:00:32 martin Exp $ */ +/* $NetBSD: intel_pm.c,v 1.17.2.2 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright © 2012 Intel Corporation @@ -28,7 +28,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.17.2.1 2019/12/12 21:00:32 martin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.17.2.2 2020/01/31 11:25:09 martin Exp $"); #include <linux/bitops.h> #include <linux/cpufreq.h> @@ -297,7 +297,7 @@ static void chv_set_memory_pm5(struct dr } #define FW_WM(value, plane) \ - (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) + (((u32)(value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) { @@ -5058,7 +5058,7 @@ static void gen6_enable_rps(struct drm_d DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); - if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ + if (!ret && (pcu_mbox & __BIT(31))) { /* OC supported */ DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", (dev_priv->rps.max_freq_softlimit & 0xff) * 50, (pcu_mbox & 0xff) * 50); Index: src/sys/external/bsd/drm2/dist/drm/radeon/cikd.h diff -u src/sys/external/bsd/drm2/dist/drm/radeon/cikd.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/cikd.h:1.2.4.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/cikd.h:1.2 Mon Aug 27 04:58:35 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/cikd.h Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: cikd.h,v 1.2 2018/08/27 04:58:35 riastradh Exp $ */ +/* $NetBSD: cikd.h,v 1.2.4.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2012 Advanced Micro Devices, Inc. @@ -809,7 +809,7 @@ # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) -# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) +# define IH_WPTR_OVERFLOW_CLEAR (1U << 31) #define IH_RB_BASE 0x3e04 #define IH_RB_RPTR 0x3e08 #define IH_RB_WPTR 0x3e0c @@ -1308,7 +1308,7 @@ #define RB_BLKSZ(x) ((x) << 8) #define BUF_SWAP_32BIT (2 << 16) #define RB_NO_UPDATE (1 << 27) -#define RB_RPTR_WR_ENA (1 << 31) +#define RB_RPTR_WR_ENA (1U << 31) #define CP_RB0_RPTR_ADDR 0xC10C #define RB_RPTR_SWAP_32BIT (2 << 0) @@ -1357,7 +1357,7 @@ #define CP_CPF_DEBUG 0xC200 #define CP_PQ_WPTR_POLL_CNTL 0xC20C -#define WPTR_POLL_EN (1 << 31) +#define WPTR_POLL_EN (1U << 31) #define CP_ME1_PIPE0_INT_CNTL 0xC214 #define CP_ME1_PIPE1_INT_CNTL 0xC218 @@ -1518,7 +1518,7 @@ #define DOORBELL_SOURCE (1 << 28) #define DOORBELL_SCHD_HIT (1 << 29) #define DOORBELL_EN (1 << 30) -#define DOORBELL_HIT (1 << 31) +#define DOORBELL_HIT (1U << 31) #define CP_HQD_PQ_WPTR 0xC954 #define CP_HQD_PQ_CONTROL 0xC958 #define QUEUE_SIZE(x) ((x) << 0) @@ -1530,7 +1530,7 @@ #define UNORD_DISPATCH (1 << 28) #define ROQ_PQ_IB_FLIP (1 << 29) #define PRIV_STATE (1 << 30) -#define KMD_QUEUE (1 << 31) +#define KMD_QUEUE (1U << 31) #define CP_HQD_IB_BASE_ADDR 0xC95Cu #define CP_HQD_IB_BASE_ADDR_HI 0xC960u @@ -1634,7 +1634,7 @@ #define SE_INDEX(x) ((x) << 16) #define SH_BROADCAST_WRITES (1 << 29) #define INSTANCE_BROADCAST_WRITES (1 << 30) -#define SE_BROADCAST_WRITES (1 << 31) +#define SE_BROADCAST_WRITES (1U << 31) #define VGT_ESGS_RING_SIZE 0x30900 #define VGT_GSVS_RING_SIZE 0x30904 @@ -1661,8 +1661,8 @@ #define CGTS_OVERRIDE (1 << 21) #define CGTS_LS_OVERRIDE (1 << 22) #define ON_MONITOR_ADD_EN (1 << 23) -#define ON_MONITOR_ADD(x) ((x) << 24) -#define ON_MONITOR_ADD_MASK (0xff << 24) +#define ON_MONITOR_ADD(x) ((uint32_t)(x) << 24) +#define ON_MONITOR_ADD_MASK (0xffU << 24) #define CGTS_TCC_DISABLE 0x3c00c #define CGTS_USER_TCC_DISABLE 0x3c010 @@ -1674,10 +1674,10 @@ /* * PM4 */ -#define PACKET_TYPE0 0 -#define PACKET_TYPE1 1 -#define PACKET_TYPE2 2 -#define PACKET_TYPE3 3 +#define PACKET_TYPE0 0U +#define PACKET_TYPE1 1U +#define PACKET_TYPE2 2U +#define PACKET_TYPE3 3U #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) Index: src/sys/external/bsd/drm2/dist/drm/radeon/evergreend.h diff -u src/sys/external/bsd/drm2/dist/drm/radeon/evergreend.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/evergreend.h:1.2.4.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/evergreend.h:1.2 Mon Aug 27 04:58:36 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/evergreend.h Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: evergreend.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */ +/* $NetBSD: evergreend.h,v 1.2.4.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2010 Advanced Micro Devices, Inc. @@ -109,7 +109,7 @@ #define IBIAS(x) ((x) << 20) #define IBIAS_MASK (0x3ff << 20) #define RESET (1 << 30) -#define PDNB (1 << 31) +#define PDNB (1U << 31) #define MPLL_AD_FUNC_CNTL_2 0x628 #define BYPASS (1 << 19) #define BIAS_GEN_PDNB (1 << 24) @@ -184,7 +184,7 @@ # define MRDCKC0_BYPASS (1 << 28) # define MRDCKC1_BYPASS (1 << 29) # define MRDCKD0_BYPASS (1 << 30) -# define MRDCKD1_BYPASS (1 << 31) +# define MRDCKD1_BYPASS (1U << 31) #define CG_AT 0x6d4 # define CG_R(x) ((x) << 0) @@ -415,7 +415,7 @@ #define INSTANCE_INDEX(x) ((x) << 0) #define SE_INDEX(x) ((x) << 16) #define INSTANCE_BROADCAST_WRITES (1 << 30) -#define SE_BROADCAST_WRITES (1 << 31) +#define SE_BROADCAST_WRITES (1U << 31) #define RLC_GFX_INDEX 0x3fC4 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 #define WRITE_DIS (1 << 0) @@ -479,7 +479,7 @@ #define RB_BUFSZ(x) ((x) << 0) #define RB_BLKSZ(x) ((x) << 8) #define RB_NO_UPDATE (1 << 27) -#define RB_RPTR_WR_ENA (1 << 31) +#define RB_RPTR_WR_ENA (1U << 31) #define BUF_SWAP_32BIT (2 << 16) #define CP_RB_RPTR 0x8700 #define CP_RB_RPTR_ADDR 0xC10C @@ -816,7 +816,7 @@ # define PIN1_AUDIO_ENABLED (1 << 25) # define PIN2_AUDIO_ENABLED (1 << 26) # define PIN3_AUDIO_ENABLED (1 << 27) -# define AUDIO_ENABLED (1 << 31) +# define AUDIO_ENABLED (1U << 31) #define GC_USER_SHADER_PIPE_CONFIG 0x8954 @@ -1047,7 +1047,7 @@ #define PS_PRIO(x) ((x) << 24) #define VS_PRIO(x) ((x) << 26) #define GS_PRIO(x) ((x) << 28) -#define ES_PRIO(x) ((x) << 30) +#define ES_PRIO(x) ((u32)(x) << 30) #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 #define NUM_PS_GPRS(x) ((x) << 0) #define NUM_VS_GPRS(x) ((x) << 16) @@ -1252,7 +1252,7 @@ # define TIME_STAMP_INT_ENABLE (1 << 26) # define IB2_INT_ENABLE (1 << 29) # define IB1_INT_ENABLE (1 << 30) -# define RB_INT_ENABLE (1 << 31) +# define RB_INT_ENABLE (1U << 31) #define CP_INT_STATUS 0xc128 # define SCRATCH_INT_STAT (1 << 25) # define TIME_STAMP_INT_STAT (1 << 26) @@ -1415,7 +1415,7 @@ #define CAYMAN_DMA1_CNTL 0xd82c /* async DMA packets */ -#define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \ +#define DMA_PACKET(cmd, sub_cmd, n) ((((uint32_t)(cmd) & 0xF) << 28) | \ (((sub_cmd) & 0xFF) << 20) |\ (((n) & 0xFFFFF) << 0)) #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28) Index: src/sys/external/bsd/drm2/dist/drm/radeon/nid.h diff -u src/sys/external/bsd/drm2/dist/drm/radeon/nid.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/nid.h:1.2.4.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/nid.h:1.2 Mon Aug 27 04:58:36 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/nid.h Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: nid.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */ +/* $NetBSD: nid.h,v 1.2.4.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2010 Advanced Micro Devices, Inc. @@ -869,7 +869,7 @@ #define AUX_SW_DATA_RW (1 << 0) #define AUX_SW_DATA_MASK(x) (((x) & 0xff) << 8) #define AUX_SW_DATA_INDEX(x) (((x) & 0x1f) << 16) -#define AUX_SW_AUTOINCREMENT_DISABLE (1 << 31) +#define AUX_SW_AUTOINCREMENT_DISABLE (1U << 31) #define LB_SYNC_RESET_SEL 0x6b28 #define LB_SYNC_RESET_SEL_MASK (3 << 0) @@ -1319,7 +1319,7 @@ #define DMA_IB_CNTL 0xd024 # define DMA_IB_ENABLE (1 << 0) # define DMA_IB_SWAP_ENABLE (1 << 4) -# define CMD_VMID_FORCE (1 << 31) +# define CMD_VMID_FORCE (1U << 31) #define DMA_IB_RPTR 0xd028 #define DMA_CNTL 0xd02c # define TRAP_ENABLE (1 << 0) @@ -1335,7 +1335,7 @@ #define DMA_TILING_CONFIG 0xd0b8 #define DMA_MODE 0xd0bc -#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ +#define DMA_PACKET(cmd, t, s, n) ((((uint32_t)(cmd) & 0xF) << 28) | \ (((t) & 0x1) << 23) | \ (((s) & 0x1) << 22) | \ (((n) & 0xFFFFF) << 0)) Index: src/sys/external/bsd/drm2/dist/drm/radeon/r600d.h diff -u src/sys/external/bsd/drm2/dist/drm/radeon/r600d.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/r600d.h:1.2.4.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/r600d.h:1.2 Mon Aug 27 04:58:36 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/r600d.h Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: r600d.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */ +/* $NetBSD: r600d.h,v 1.2.4.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2009 Advanced Micro Devices, Inc. @@ -198,7 +198,7 @@ #define RB_BUFSZ(x) ((x) << 0) #define RB_BLKSZ(x) ((x) << 8) #define RB_NO_UPDATE (1 << 27) -#define RB_RPTR_WR_ENA (1 << 31) +#define RB_RPTR_WR_ENA (1U << 31) #define BUF_SWAP_32BIT (2 << 16) #define CP_RB_RPTR 0x8700 #define CP_RB_RPTR_ADDR 0xC10C @@ -292,7 +292,7 @@ # define GRBM_READ_TIMEOUT(x) ((x) << 0) #define GRBM_STATUS 0x8010 #define CMDFIFO_AVAIL_MASK 0x0000001F -#define GUI_ACTIVE (1<<31) +#define GUI_ACTIVE (1U<<31) #define GRBM_STATUS2 0x8014 #define GRBM_SOFT_RESET 0x8020 #define SOFT_RESET_CP (1<<0) @@ -644,7 +644,7 @@ #define DMA_MODE 0xd0bc /* async DMA packets */ -#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ +#define DMA_PACKET(cmd, t, s, n) ((((u32)(cmd) & 0xF) << 28) | \ (((t) & 0x1) << 23) | \ (((s) & 0x1) << 22) | \ (((n) & 0xFFFF) << 0)) @@ -665,7 +665,7 @@ # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) -# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) +# define IH_WPTR_OVERFLOW_CLEAR (1U << 31) #define IH_RB_BASE 0x3e04 #define IH_RB_RPTR 0x3e08 #define IH_RB_WPTR 0x3e0c @@ -720,7 +720,7 @@ # define TIME_STAMP_INT_ENABLE (1 << 26) # define IB2_INT_ENABLE (1 << 29) # define IB1_INT_ENABLE (1 << 30) -# define RB_INT_ENABLE (1 << 31) +# define RB_INT_ENABLE (1U << 31) #define CP_INT_STATUS 0xc128 # define SCRATCH_INT_STAT (1 << 25) # define TIME_STAMP_INT_STAT (1 << 26) @@ -935,7 +935,7 @@ # define JACK_DETECTION_ENABLE (1 << 4) # define UNSOLICITED_RESPONSE_ENABLE (1 << 8) # define CODEC_HOT_PLUG_ENABLE (1 << 12) -# define AUDIO_ENABLED (1 << 31) +# define AUDIO_ENABLED (1U << 31) /* DCE3 adds */ # define PIN0_JACK_DETECTION_ENABLE (1 << 4) # define PIN1_JACK_DETECTION_ENABLE (1 << 5) Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h:1.2.4.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h:1.2 Mon Aug 27 04:58:36 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_reg.h Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: radeon_reg.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */ +/* $NetBSD: radeon_reg.h,v 1.2.4.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and @@ -3715,10 +3715,10 @@ #define RADEON_CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) #define R100_CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) #define R600_CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) -#define RADEON_PACKET_TYPE0 0 -#define RADEON_PACKET_TYPE1 1 -#define RADEON_PACKET_TYPE2 2 -#define RADEON_PACKET_TYPE3 3 +#define RADEON_PACKET_TYPE0 0U +#define RADEON_PACKET_TYPE1 1U +#define RADEON_PACKET_TYPE2 2U +#define RADEON_PACKET_TYPE3 3U #define RADEON_PACKET3_NOP 0x10 Index: src/sys/external/bsd/drm2/dist/drm/radeon/rv730d.h diff -u src/sys/external/bsd/drm2/dist/drm/radeon/rv730d.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/rv730d.h:1.2.4.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/rv730d.h:1.2 Mon Aug 27 04:58:36 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/rv730d.h Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: rv730d.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */ +/* $NetBSD: rv730d.h,v 1.2.4.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2011 Advanced Micro Devices, Inc. @@ -150,7 +150,7 @@ #define POWERMODE2(x) ((x) << 16) #define POWERMODE2_MASK (0xff << 16) #define POWERMODE3(x) ((x) << 24) -#define POWERMODE3_MASK (0xff << 24) +#define POWERMODE3_MASK (0xffU << 24) #define MC_ARB_DRAM_TIMING_1 0x27f0 #define MC_ARB_DRAM_TIMING_2 0x27f4 Index: src/sys/external/bsd/drm2/dist/drm/radeon/rv770d.h diff -u src/sys/external/bsd/drm2/dist/drm/radeon/rv770d.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/rv770d.h:1.2.4.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/rv770d.h:1.2 Mon Aug 27 04:58:36 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/rv770d.h Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: rv770d.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */ +/* $NetBSD: rv770d.h,v 1.2.4.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2009 Advanced Micro Devices, Inc. @@ -563,7 +563,7 @@ #define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 #define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 #define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC -#define ES_PRIO(x) ((x) << 30) +#define ES_PRIO(x) ((u32)(x) << 30) #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 #define NUM_PS_GPRS(x) ((x) << 0) #define NUM_VS_GPRS(x) ((x) << 16) @@ -661,7 +661,7 @@ #define DMA_RB_WPTR 0xd00c /* async DMA packets */ -#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ +#define DMA_PACKET(cmd, t, s, n) ((((u32)(cmd) & 0xF) << 28) | \ (((t) & 0x1) << 23) | \ (((s) & 0x1) << 22) | \ (((n) & 0xFFFF) << 0)) Index: src/sys/external/bsd/drm2/dist/drm/radeon/sid.h diff -u src/sys/external/bsd/drm2/dist/drm/radeon/sid.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/sid.h:1.2.4.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/sid.h:1.2 Mon Aug 27 04:58:36 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/sid.h Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: sid.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */ +/* $NetBSD: sid.h,v 1.2.4.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2011 Advanced Micro Devices, Inc. @@ -224,7 +224,7 @@ #define FDO_PWM_MODE_MASK (7 << 11) #define FDO_PWM_MODE_SHIFT 11 #define TACH_PWM_RESP_RATE(x) ((x) << 25) -#define TACH_PWM_RESP_RATE_MASK (0x7f << 25) +#define TACH_PWM_RESP_RATE_MASK (0x7fU << 25) #define TACH_PWM_RESP_RATE_SHIFT 25 #define CG_TACH_CTRL 0x770 @@ -530,7 +530,7 @@ #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 #define TRAIN_DONE_D0 (1 << 30) -#define TRAIN_DONE_D1 (1 << 31) +#define TRAIN_DONE_D1 (1U << 31) #define MC_SEQ_SUP_CNTL 0x28c8 #define RUN_MASK (1 << 0) @@ -657,7 +657,7 @@ # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) -# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) +# define IH_WPTR_OVERFLOW_CLEAR (1U << 31) #define IH_RB_BASE 0x3e04 #define IH_RB_RPTR 0x3e08 #define IH_RB_WPTR 0x3e0c @@ -781,10 +781,10 @@ # define DESCRIPTION17(x) (((x) & 0xff) << 8) #define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 -# define AUDIO_ENABLED (1 << 31) +# define AUDIO_ENABLED (1U << 31) #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 -#define PORT_CONNECTIVITY_MASK (3 << 30) +#define PORT_CONNECTIVITY_MASK (3U << 30) #define PORT_CONNECTIVITY_SHIFT 30 #define DC_LB_MEMORY_SPLIT 0x6b0c @@ -1003,7 +1003,7 @@ #define SE_INDEX(x) ((x) << 16) #define SH_BROADCAST_WRITES (1 << 29) #define INSTANCE_BROADCAST_WRITES (1 << 30) -#define SE_BROADCAST_WRITES (1 << 31) +#define SE_BROADCAST_WRITES (1U << 31) #define GRBM_INT_CNTL 0x8060 # define RDERR_INT_ENABLE (1 << 0) @@ -1249,7 +1249,7 @@ #define RB_BLKSZ(x) ((x) << 8) #define BUF_SWAP_32BIT (2 << 16) #define RB_NO_UPDATE (1 << 27) -#define RB_RPTR_WR_ENA (1 << 31) +#define RB_RPTR_WR_ENA (1U << 31) #define CP_RB0_RPTR_ADDR 0xC10C #define CP_RB0_RPTR_ADDR_HI 0xC110 @@ -1523,7 +1523,7 @@ # define LC_XMIT_N_FTS_MASK (0xff << 0) # define LC_XMIT_N_FTS_SHIFT 0 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) -# define LC_N_FTS_MASK (0xff << 24) +# define LC_N_FTS_MASK (0xffU << 24) #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ # define LC_GEN2_EN_STRAP (1 << 0) # define LC_GEN3_EN_STRAP (1 << 1) @@ -1850,7 +1850,7 @@ #define DMA_PGFSM_CONFIG 0xd0d8 #define DMA_PGFSM_WRITE 0xd0dc -#define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ +#define DMA_PACKET(cmd, b, t, s, n) ((((uint32_t)(cmd) & 0xF) << 28) | \ (((b) & 0x1) << 26) | \ (((t) & 0x1) << 23) | \ (((s) & 0x1) << 22) | \ Index: src/sys/external/bsd/drm2/dist/drm/radeon/sumod.h diff -u src/sys/external/bsd/drm2/dist/drm/radeon/sumod.h:1.2 src/sys/external/bsd/drm2/dist/drm/radeon/sumod.h:1.2.4.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/sumod.h:1.2 Mon Aug 27 04:58:36 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/sumod.h Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: sumod.h,v 1.2 2018/08/27 04:58:36 riastradh Exp $ */ +/* $NetBSD: sumod.h,v 1.2.4.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2012 Advanced Micro Devices, Inc. @@ -197,7 +197,7 @@ # define SCLK_FSTATE_3_DIV(x) ((x) << 24) # define SCLK_FSTATE_3_DIV_MASK (0x7f << 24) # define SCLK_FSTATE_3_DIV_SHIFT 24 -# define SCLK_FSTATE_3_VLD (1 << 31) +# define SCLK_FSTATE_3_VLD (1U << 31) #define CG_SCLK_DPM_CTRL_2 0x688 #define CG_GCOOR 0x68c # define PHC(x) ((x) << 0) @@ -243,7 +243,7 @@ # define DPM_SCLK_ENABLE (1 << 18) # define GNB_SLOW_FSTATE_0_MASK (1 << 23) # define GNB_SLOW_FSTATE_0_SHIFT 23 -# define FORCE_NB_PSTATE_1 (1 << 31) +# define FORCE_NB_PSTATE_1 (1U << 31) #define CG_SSP 0x6e8 # define SST(x) ((x) << 0) @@ -263,7 +263,7 @@ # define DC_HDC_MASK (0x3fff << 14) # define DC_HDC_SHIFT 14 # define DC_HU(x) ((x) << 28) -# define DC_HU_MASK (0xf << 28) +# define DC_HU_MASK (0xfU << 28) # define DC_HU_SHIFT 28 #define CG_SCLK_DPM_CTRL_5 0x720 # define SCLK_FSTATE_BOOTUP(x) ((x) << 0) @@ -281,7 +281,7 @@ # define CG_R_MASK (0xffff << 0) # define CG_R_SHIFT 0 # define CG_L(x) ((x) << 16) -# define CG_L_MASK (0xffff << 16) +# define CG_L_MASK (0xffffU << 16) # define CG_L_SHIFT 16 #define CG_AT_1 0x72c #define CG_AT_2 0x730 @@ -351,7 +351,7 @@ # define HS(x) ((x) << 4) # define HS_MASK (0xfff << 4) # define HS_SHIFT 4 -# define ENABLE_DS (1 << 31) +# define ENABLE_DS (1U << 31) #define DEEP_SLEEP_CNTL2 0x81c # define LB_UFP_EN (1 << 0) # define INOUT_C(x) ((x) << 4) @@ -363,7 +363,7 @@ #define CG_SCLK_DPM_CTRL_11 0x830 #define HW_REV 0x5564 -# define ATI_REV_ID_MASK (0xf << 28) +# define ATI_REV_ID_MASK (0xfU << 28) # define ATI_REV_ID_SHIFT 28 /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h:1.4 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h:1.4.4.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h:1.4 Mon Aug 27 15:13:05 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_mode.h Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: radeon_mode.h,v 1.4 2018/08/27 15:13:05 riastradh Exp $ */ +/* $NetBSD: radeon_mode.h,v 1.4.4.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and @@ -693,7 +693,7 @@ struct atom_voltage_table /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */ #define USE_REAL_VBLANKSTART (1 << 30) -#define GET_DISTANCE_TO_VBLANKSTART (1 << 31) +#define GET_DISTANCE_TO_VBLANKSTART (1U << 31) extern void radeon_add_atom_connector(struct drm_device *dev, Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_r600.c diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_r600.c:1.1 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_r600.c:1.1.8.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_r600.c:1.1 Mon Aug 27 14:38:20 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_r600.c Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: radeon_r600.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ +/* $NetBSD: radeon_r600.c,v 1.1.8.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2008 Advanced Micro Devices, Inc. @@ -28,7 +28,7 @@ * Jerome Glisse */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: radeon_r600.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: radeon_r600.c,v 1.1.8.1 2020/01/31 11:25:09 martin Exp $"); #include <linux/bitops.h> #include <linux/slab.h> @@ -2224,13 +2224,13 @@ static void r600_gpu_init(struct radeon_ sq_config &= ~(PS_PRIO(3) | VS_PRIO(3) | GS_PRIO(3) | - ES_PRIO(3)); + ES_PRIO(3U)); sq_config |= (DX9_CONSTS | VC_ENABLE | PS_PRIO(0) | VS_PRIO(1) | GS_PRIO(2) | - ES_PRIO(3)); + ES_PRIO(3U)); if ((rdev->family) == CHIP_R600) { sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | @@ -2319,15 +2319,15 @@ static void r600_gpu_init(struct radeon_ WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | S1_X(0x2) | S1_Y(0x2) | S2_X(0xa) | S2_Y(0x6) | - S3_X(0x6) | S3_Y(0xa))); + S3_X(0x6) | S3_Y(0xaU))); WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | S1_X(0x4) | S1_Y(0xc) | S2_X(0x1) | S2_Y(0x6) | - S3_X(0xa) | S3_Y(0xe))); + S3_X(0xa) | S3_Y(0xeU))); WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | S5_X(0x0) | S5_Y(0x0) | S6_X(0xb) | S6_Y(0x4) | - S7_X(0x7) | S7_Y(0x8))); + S7_X(0x7) | S7_Y(0x8U))); WREG32(VGT_STRMOUT_EN, 0); tmp = rdev->config.r600.max_pipes * 16; Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_rv770_smc.c diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_rv770_smc.c:1.1 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_rv770_smc.c:1.1.8.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_rv770_smc.c:1.1 Mon Aug 27 14:38:20 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_rv770_smc.c Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: radeon_rv770_smc.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ +/* $NetBSD: radeon_rv770_smc.c,v 1.1.8.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2011 Advanced Micro Devices, Inc. @@ -25,7 +25,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: radeon_rv770_smc.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: radeon_rv770_smc.c,v 1.1.8.1 2020/01/31 11:25:09 martin Exp $"); #include <linux/firmware.h> #include "drmP.h" @@ -316,7 +316,7 @@ int rv770_copy_bytes_to_smc(struct radeo spin_lock_irqsave(&rdev->smc_idx_lock, flags); while (byte_count >= 4) { /* SMC address space is BE */ - data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; + data = ((u32)src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; ret = rv770_set_smc_sram_address(rdev, addr, limit); if (ret) Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c:1.1 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c:1.1.8.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c:1.1 Mon Aug 27 14:38:20 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_si_smc.c Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: radeon_si_smc.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ +/* $NetBSD: radeon_si_smc.c,v 1.1.8.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2011 Advanced Micro Devices, Inc. @@ -25,7 +25,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: radeon_si_smc.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: radeon_si_smc.c,v 1.1.8.1 2020/01/31 11:25:09 martin Exp $"); #include <linux/firmware.h> #include "drmP.h" @@ -67,7 +67,7 @@ int si_copy_bytes_to_smc(struct radeon_d spin_lock_irqsave(&rdev->smc_idx_lock, flags); while (byte_count >= 4) { /* SMC address space is BE */ - data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; + data = ((u32)src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; ret = si_set_smc_sram_address(rdev, addr, limit); if (ret) @@ -271,7 +271,7 @@ int si_load_smc_ucode(struct radeon_devi WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); while (ucode_size >= 4) { /* SMC address space is BE */ - data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; + data = ((u32)src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; WREG32(SMC_IND_DATA_0, data); Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c:1.1 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c:1.1.8.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c:1.1 Mon Aug 27 14:38:20 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v1_0.c Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: radeon_uvd_v1_0.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ +/* $NetBSD: radeon_uvd_v1_0.c,v 1.1.8.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2013 Advanced Micro Devices, Inc. @@ -25,7 +25,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v1_0.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v1_0.c,v 1.1.8.1 2020/01/31 11:25:09 martin Exp $"); #include <linux/firmware.h> #include <drm/drmP.h> @@ -144,7 +144,7 @@ int uvd_v1_0_resume(struct radeon_device /* bits 32-39 */ addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; - WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); + WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1U << 31)); WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); @@ -366,7 +366,7 @@ int uvd_v1_0_start(struct radeon_device /* programm the 4GB memory segment for rptr and ring buffer */ WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | - (0x7 << 16) | (0x1 << 31)); + (0x7 << 16) | (0x1U << 31)); /* Initialize the ring buffer's read and write pointers */ WREG32(UVD_RBC_RB_RPTR, 0x0); Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c:1.1 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c:1.1.8.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c:1.1 Mon Aug 27 14:38:20 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v2_2.c Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: radeon_uvd_v2_2.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ +/* $NetBSD: radeon_uvd_v2_2.c,v 1.1.8.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2013 Advanced Micro Devices, Inc. @@ -25,7 +25,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v2_2.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v2_2.c,v 1.1.8.1 2020/01/31 11:25:09 martin Exp $"); #include <linux/firmware.h> #include <drm/drmP.h> @@ -136,7 +136,7 @@ int uvd_v2_2_resume(struct radeon_device /* bits 32-39 */ addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; - WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); + WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1U << 31)); /* tell firmware which hardware it is running on */ switch (rdev->family) { Index: src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c diff -u src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c:1.1 src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c:1.1.8.1 --- src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c:1.1 Mon Aug 27 14:38:20 2018 +++ src/sys/external/bsd/drm2/dist/drm/radeon/radeon_uvd_v4_2.c Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: radeon_uvd_v4_2.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $ */ +/* $NetBSD: radeon_uvd_v4_2.c,v 1.1.8.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2013 Advanced Micro Devices, Inc. @@ -25,7 +25,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v4_2.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v4_2.c,v 1.1.8.1 2020/01/31 11:25:09 martin Exp $"); #include <linux/firmware.h> #include <drm/drmP.h> @@ -67,7 +67,7 @@ int uvd_v4_2_resume(struct radeon_device /* bits 32-39 */ addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; - WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); + WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1U << 31)); return 0; } Index: src/sys/external/bsd/drm2/dist/include/drm/drm_fixed.h diff -u src/sys/external/bsd/drm2/dist/include/drm/drm_fixed.h:1.2 src/sys/external/bsd/drm2/dist/include/drm/drm_fixed.h:1.2.4.1 --- src/sys/external/bsd/drm2/dist/include/drm/drm_fixed.h:1.2 Mon Aug 27 04:58:37 2018 +++ src/sys/external/bsd/drm2/dist/include/drm/drm_fixed.h Fri Jan 31 11:25:09 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: drm_fixed.h,v 1.2 2018/08/27 04:58:37 riastradh Exp $ */ +/* $NetBSD: drm_fixed.h,v 1.2.4.1 2020/01/31 11:25:09 martin Exp $ */ /* * Copyright 2009 Red Hat Inc. @@ -34,7 +34,7 @@ typedef union dfixed { } fixed20_12; -#define dfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */ +#define dfixed_const(A) (((u32)(A) << 12))/* + ((B + 0.000122)*4096)) */ #define dfixed_const_half(A) (u32)(((A) << 12) + 2048) #define dfixed_const_666(A) (u32)(((A) << 12) + 2731) #define dfixed_const_8(A) (u32)(((A) << 12) + 3277)