Module Name: src
Committed By: skrll
Date: Sat Feb 15 17:01:01 UTC 2020
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Fix two comments
To generate a diff of this commit:
cvs rdiff -u -r1.106 -r1.107 src/sys/arch/mips/mips/mipsX_subr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/mipsX_subr.S
diff -u src/sys/arch/mips/mips/mipsX_subr.S:1.106 src/sys/arch/mips/mips/mipsX_subr.S:1.107
--- src/sys/arch/mips/mips/mipsX_subr.S:1.106 Sat Feb 15 16:56:15 2020
+++ src/sys/arch/mips/mips/mipsX_subr.S Sat Feb 15 17:01:00 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsX_subr.S,v 1.106 2020/02/15 16:56:15 skrll Exp $ */
+/* $NetBSD: mipsX_subr.S,v 1.107 2020/02/15 17:01:00 skrll Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@@ -1960,7 +1960,7 @@ MIPSX(kern_tlbi_odd):
_SLL k0, k0, WIRED_SHIFT # get rid of wired bit
_SRL k0, k0, WIRED_SHIFT
#endif
- _MTC0 k0, MIPS_COP_0_TLB_LO1 # save PTE entry
+ _MTC0 k0, MIPS_COP_0_TLB_LO1 # load PTE entry
COP0_SYNC
and k0, k0, MIPS3_PG_V # check for valid entry
#ifdef MIPS3
@@ -1981,7 +1981,7 @@ MIPSX(kern_tlbi_odd):
sltiu k1, k1, MIPS3_TLB_WIRED_UPAGES # Luckily this is MIPS3_PG_G
or k1, k1, k0
#endif
- _MTC0 k0, MIPS_COP_0_TLB_LO0 # save PTE entry
+ _MTC0 k0, MIPS_COP_0_TLB_LO0 # load PTE entry
COP0_SYNC
#ifdef MIPS3
nop # required for QED5230
