Module Name: src
Committed By: msaitoh
Date: Fri Mar 27 09:47:03 UTC 2020
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
Add special handling for model 0x0f stepping >=2 or mode 0x0e to get Tjmax.
To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/x86/x86/coretemp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/coretemp.c
diff -u src/sys/arch/x86/x86/coretemp.c:1.36 src/sys/arch/x86/x86/coretemp.c:1.37
--- src/sys/arch/x86/x86/coretemp.c:1.36 Wed Jul 11 03:36:32 2018
+++ src/sys/arch/x86/x86/coretemp.c Fri Mar 27 09:47:03 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: coretemp.c,v 1.36 2018/07/11 03:36:32 msaitoh Exp $ */
+/* $NetBSD: coretemp.c,v 1.37 2020/03/27 09:47:03 msaitoh Exp $ */
/*-
* Copyright (c) 2011 The NetBSD Foundation, Inc.
@@ -61,7 +61,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.36 2018/07/11 03:36:32 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.37 2020/03/27 09:47:03 msaitoh Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -271,6 +271,19 @@ coretemp_tjmax(device_t self)
sc->sc_tjmax = 100;
if ((model == 0x0f && stepping >= 2) || (model == 0x0e)) {
+ /*
+ * Check MSR_IA32_PLATFORM_ID(0x17) bit 28. It's not documented
+ * in the datasheet, but the following page describes the
+ * detail:
+ * http://software.intel.com/en-us/articles/
+ * mobile-intel-core2-processor-detection-table/
+ * Was: http://softwarecommunity.intel.com/Wiki/Mobility/
+ * 720.htm
+ */
+ if (rdmsr_safe(MSR_IA32_PLATFORM_ID, &msr) != 0)
+ goto notee;
+ if ((model < 0x17) && ((msr & __BIT(28)) == 0))
+ goto notee;
if (rdmsr_safe(MSR_IA32_EXT_CONFIG, &msr) == EFAULT)
return;
@@ -290,6 +303,7 @@ coretemp_tjmax(device_t self)
} else
sc->sc_tjmax = 90;
} else {
+notee:
/*
* Attempt to get Tj(max) from IA32_TEMPERATURE_TARGET,
* but only consider the interval [70, 110] C as valid.
