Module Name: src
Committed By: jdolecek
Date: Mon May 4 15:55:57 UTC 2020
Modified Files:
src/sys/arch/amd64/include: types.h
src/sys/arch/i386/include: types.h
src/sys/arch/x86/pci: msipic.c msipic.h pci_machdep.c
src/sys/arch/xen/include: evtchn.h
src/sys/arch/xen/x86: pintr.c xen_intr.c
src/sys/arch/xen/xen: evtchn.c
Log Message:
add support for using MSI for XenPV Dom0
use PHYSDEVOP_map_pirq to get the pirq/gsi for MSI/MSI-X, switch also INTx
to use it instead of PHYSDEVOP_alloc_irq_vector
MSI confirmed working with single-vector MSI for wm(4), ahcisata(4), bge(4)
XXX added some provision for MSI-X, but it doesn't actually work (no interrupts
delivered), needs some further investigation; disable MSI-X for XENPV
via flag in x86/pci/pci_machdep.c
To generate a diff of this commit:
cvs rdiff -u -r1.67 -r1.68 src/sys/arch/amd64/include/types.h
cvs rdiff -u -r1.90 -r1.91 src/sys/arch/i386/include/types.h
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/x86/pci/msipic.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/x86/pci/msipic.h
cvs rdiff -u -r1.86 -r1.87 src/sys/arch/x86/pci/pci_machdep.c
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/xen/include/evtchn.h
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/xen/x86/pintr.c
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/xen/x86/xen_intr.c
cvs rdiff -u -r1.91 -r1.92 src/sys/arch/xen/xen/evtchn.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/amd64/include/types.h
diff -u src/sys/arch/amd64/include/types.h:1.67 src/sys/arch/amd64/include/types.h:1.68
--- src/sys/arch/amd64/include/types.h:1.67 Sat Apr 25 15:26:16 2020
+++ src/sys/arch/amd64/include/types.h Mon May 4 15:55:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: types.h,v 1.67 2020/04/25 15:26:16 bouyer Exp $ */
+/* $NetBSD: types.h,v 1.68 2020/05/04 15:55:56 jdolecek Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -100,6 +100,9 @@ typedef unsigned char __cpu_simple_lock
#define __HAVE_MM_MD_DIRECT_MAPPED_IO
#define __HAVE_MM_MD_DIRECT_MAPPED_PHYS
#define __HAVE_UCAS_FULL
+#if !defined(NO_PCI_MSI_MSIX)
+#define __HAVE_PCI_MSI_MSIX
+#endif
#ifdef _KERNEL_OPT
#define __HAVE_RAS
@@ -116,9 +119,6 @@ typedef unsigned char __cpu_simple_lock
#define __HAVE_DIRECT_MAP 1
#endif
#define __HAVE_CPU_UAREA_ROUTINES 1
-#if !defined(NO_PCI_MSI_MSIX)
-#define __HAVE_PCI_MSI_MSIX
-#endif
#endif
#endif
Index: src/sys/arch/i386/include/types.h
diff -u src/sys/arch/i386/include/types.h:1.90 src/sys/arch/i386/include/types.h:1.91
--- src/sys/arch/i386/include/types.h:1.90 Mon Sep 23 23:06:26 2019
+++ src/sys/arch/i386/include/types.h Mon May 4 15:55:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: types.h,v 1.90 2019/09/23 23:06:26 kamil Exp $ */
+/* $NetBSD: types.h,v 1.91 2020/05/04 15:55:56 jdolecek Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -133,13 +133,9 @@ typedef __register_t register_t;
#define __HAVE_TLS_VARIANT_II
#define __HAVE_COMMON___TLS_GET_ADDR
#define __HAVE_UCAS_FULL
-
-#if defined(_KERNEL)
-#define __HAVE_RAS
-
-#if !defined(XEN) && !defined(NO_PCI_MSI_MSIX)
+#if !defined(NO_PCI_MSI_MSIX)
#define __HAVE_PCI_MSI_MSIX
#endif
-#endif
+#define __HAVE_RAS
#endif /* _I386_MACHTYPES_H_ */
Index: src/sys/arch/x86/pci/msipic.c
diff -u src/sys/arch/x86/pci/msipic.c:1.22 src/sys/arch/x86/pci/msipic.c:1.23
--- src/sys/arch/x86/pci/msipic.c:1.22 Mon May 4 09:34:37 2020
+++ src/sys/arch/x86/pci/msipic.c Mon May 4 15:55:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: msipic.c,v 1.22 2020/05/04 09:34:37 jdolecek Exp $ */
+/* $NetBSD: msipic.c,v 1.23 2020/05/04 15:55:56 jdolecek Exp $ */
/*
* Copyright (c) 2015 Internet Initiative Japan Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.22 2020/05/04 09:34:37 jdolecek Exp $");
+__KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1.23 2020/05/04 15:55:56 jdolecek Exp $");
#include "opt_intrdebug.h"
@@ -70,12 +70,9 @@ __KERNEL_RCSID(0, "$NetBSD: msipic.c,v 1
* is managed by below "dev_seqs".
*/
struct msipic {
- int mp_bus;
- int mp_dev;
- int mp_fun;
+ struct msipic_pci_info mp_i;
int mp_devid; /* The device id for the MSI/MSI-X device. */
- int mp_veccnt; /* The number of MSI/MSI-X vectors. */
char mp_pic_name[MSIPICNAMEBUF]; /* The MSI/MSI-X device's name. */
@@ -256,7 +253,7 @@ msipic_construct_common_msi_pic(const st
pic->pic_msipic = msipic;
msipic->mp_pic = pic;
pci_decompose_tag(pa->pa_pc, pa->pa_tag,
- &msipic->mp_bus, &msipic->mp_dev, &msipic->mp_fun);
+ &msipic->mp_i.mp_bus, &msipic->mp_i.mp_dev, &msipic->mp_i.mp_fun);
memcpy(&msipic->mp_pa, pa, sizeof(msipic->mp_pa));
msipic->mp_devid = devid;
/*
@@ -311,6 +308,17 @@ msipic_get_devid(struct pic *pic)
return pic->pic_msipic->mp_devid;
}
+/*
+ * Return the PCI bus/dev/func info for the device.
+ */
+const struct msipic_pci_info *
+msipic_get_pci_info(struct pic *pic)
+{
+ KASSERT(msipic_is_msi_pic(pic));
+
+ return &pic->pic_msipic->mp_i;
+}
+
#define MSI_MSICTL_ENABLE 1
#define MSI_MSICTL_DISABLE 0
static void
@@ -366,7 +374,10 @@ msi_addroute(struct pic *pic, struct cpu
pci_chipset_tag_t pc;
struct pci_attach_args *pa;
pcitag_t tag;
- pcireg_t addr, data, ctl;
+#ifndef XENPV
+ pcireg_t addr, data;
+#endif
+ pcireg_t ctl;
int off, err __diagused;
pc = NULL;
@@ -375,6 +386,8 @@ msi_addroute(struct pic *pic, struct cpu
err = pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL);
KASSERT(err != 0);
+ ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
+#ifndef XENPV
/*
* See Intel 64 and IA-32 Architectures Software Developer's Manual
* Volume 3 10.11 Message Signalled Interrupts.
@@ -398,7 +411,6 @@ msi_addroute(struct pic *pic, struct cpu
* spec, so it's OK just to write it regardless of the value of the
* upper 16bit.
*/
- ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_LO, addr);
pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_HI, 0);
@@ -407,6 +419,7 @@ msi_addroute(struct pic *pic, struct cpu
pci_conf_write(pc, tag, off + PCI_MSI_MADDR, addr);
pci_conf_write(pc, tag, off + PCI_MSI_MDATA, data);
}
+#endif /* !XENPV */
ctl |= PCI_MSI_CTL_MSI_ENABLE;
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
}
@@ -536,7 +549,10 @@ msix_addroute(struct pic *pic, struct cp
bus_space_tag_t bstag;
bus_space_handle_t bshandle;
uint64_t entry_base;
- pcireg_t addr, data, ctl;
+#ifndef XENPV
+ pcireg_t addr, data;
+#endif
+ pcireg_t ctl;
int off, err __diagused;
if (msix_vec < 0) {
@@ -556,8 +572,11 @@ msix_addroute(struct pic *pic, struct cp
ctl &= ~PCI_MSIX_CTL_ENABLE;
pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
+ bstag = pic->pic_msipic->mp_bstag;
+ bshandle = pic->pic_msipic->mp_bshandle;
entry_base = PCI_MSIX_TABLE_ENTRY_SIZE * msix_vec;
+#ifndef XENPV
/*
* See Intel 64 and IA-32 Architectures Software Developer's Manual
* Volume 3 10.11 Message Signalled Interrupts.
@@ -572,14 +591,13 @@ msix_addroute(struct pic *pic, struct cp
data = __SHIFTIN(idt_vec, LAPIC_VECTOR_MASK)
| LAPIC_TRIGMODE_EDGE | LAPIC_DLMODE_FIXED;
- bstag = pic->pic_msipic->mp_bstag;
- bshandle = pic->pic_msipic->mp_bshandle;
bus_space_write_4(bstag, bshandle,
entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_LO, addr);
bus_space_write_4(bstag, bshandle,
entry_base + PCI_MSIX_TABLE_ENTRY_ADDR_HI, 0);
bus_space_write_4(bstag, bshandle,
entry_base + PCI_MSIX_TABLE_ENTRY_DATA, data);
+#endif /* !XENPV */
bus_space_write_4(bstag, bshandle,
entry_base + PCI_MSIX_TABLE_ENTRY_VECTCTL, 0);
BUS_SPACE_WRITE_FLUSH(bstag, bshandle);
@@ -734,6 +752,7 @@ msipic_construct_msix_pic(const struct p
msix_pic->pic_msipic->mp_bstag = bstag;
msix_pic->pic_msipic->mp_bshandle = bshandle;
msix_pic->pic_msipic->mp_bssize = bssize;
+ msix_pic->pic_msipic->mp_i.mp_table_base = memaddr + table_offset;
return msix_pic;
}
@@ -785,7 +804,7 @@ msipic_set_msi_vectors(struct pic *msi_p
pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl);
}
- msi_pic->pic_msipic->mp_veccnt = count;
+ msi_pic->pic_msipic->mp_i.mp_veccnt = count;
return 0;
}
Index: src/sys/arch/x86/pci/msipic.h
diff -u src/sys/arch/x86/pci/msipic.h:1.2 src/sys/arch/x86/pci/msipic.h:1.3
--- src/sys/arch/x86/pci/msipic.h:1.2 Fri May 8 04:27:48 2015
+++ src/sys/arch/x86/pci/msipic.h Mon May 4 15:55:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: msipic.h,v 1.2 2015/05/08 04:27:48 knakahara Exp $ */
+/* $NetBSD: msipic.h,v 1.3 2020/05/04 15:55:56 jdolecek Exp $ */
/*
* Copyright (c) 2015 Internet Initiative Japan Inc.
@@ -41,6 +41,14 @@ int msipic_set_msi_vectors(struct pic *
bool msipic_is_msi_pic(struct pic *);
int msipic_get_devid(struct pic *);
+struct msipic_pci_info {
+ int mp_bus, mp_dev, mp_fun;
+ int mp_veccnt; /* The number of MSI/MSI-X vectors. */
+ uint32_t mp_table_base; /* MSI-X table location in memory space */
+};
+
+const struct msipic_pci_info *msipic_get_pci_info(struct pic *);
+
void msipic_init(void);
#endif /* _X86_PCI_MSIPIC_H_ */
Index: src/sys/arch/x86/pci/pci_machdep.c
diff -u src/sys/arch/x86/pci/pci_machdep.c:1.86 src/sys/arch/x86/pci/pci_machdep.c:1.87
--- src/sys/arch/x86/pci/pci_machdep.c:1.86 Fri May 24 14:28:48 2019
+++ src/sys/arch/x86/pci/pci_machdep.c Mon May 4 15:55:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_machdep.c,v 1.86 2019/05/24 14:28:48 nonaka Exp $ */
+/* $NetBSD: pci_machdep.c,v 1.87 2020/05/04 15:55:56 jdolecek Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@@ -73,7 +73,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.86 2019/05/24 14:28:48 nonaka Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.87 2020/05/04 15:55:56 jdolecek Exp $");
#include <sys/types.h>
#include <sys/param.h>
@@ -554,6 +554,15 @@ pci_attach_hook(device_t parent, device_
pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
}
}
+
+#ifdef XENPV
+ /*
+ * XXX MSI-X doesn't work for XenPV yet - setup seems to be correct,
+ * XXX but no interrupts are actually delivered.
+ */
+ pba->pba_flags &= ~PCI_FLAGS_MSIX_OKAY;
+#endif
+
#endif /* __HAVE_PCI_MSI_MSIX */
}
Index: src/sys/arch/xen/include/evtchn.h
diff -u src/sys/arch/xen/include/evtchn.h:1.30 src/sys/arch/xen/include/evtchn.h:1.31
--- src/sys/arch/xen/include/evtchn.h:1.30 Sat Apr 25 15:26:17 2020
+++ src/sys/arch/xen/include/evtchn.h Mon May 4 15:55:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: evtchn.h,v 1.30 2020/04/25 15:26:17 bouyer Exp $ */
+/* $NetBSD: evtchn.h,v 1.31 2020/05/04 15:55:56 jdolecek Exp $ */
/*
*
@@ -29,8 +29,6 @@
#ifndef _XEN_EVENTS_H_
#define _XEN_EVENTS_H_
-#define NR_PIRQS 256
-
extern struct evtsource *evtsource[];
void events_default_setup(void);
Index: src/sys/arch/xen/x86/pintr.c
diff -u src/sys/arch/xen/x86/pintr.c:1.13 src/sys/arch/xen/x86/pintr.c:1.14
--- src/sys/arch/xen/x86/pintr.c:1.13 Sat Apr 25 15:26:17 2020
+++ src/sys/arch/xen/x86/pintr.c Mon May 4 15:55:56 2020
@@ -103,7 +103,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pintr.c,v 1.13 2020/04/25 15:26:17 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pintr.c,v 1.14 2020/05/04 15:55:56 jdolecek Exp $");
#include "opt_multiprocessor.h"
#include "opt_xen.h"
@@ -126,6 +126,10 @@ __KERNEL_RCSID(0, "$NetBSD: pintr.c,v 1.
#include <xen/evtchn.h>
#include <xen/intr.h>
+#ifdef __HAVE_PCI_MSI_MSIX
+#include <x86/pci/msipic.h>
+#endif
+
#include "acpica.h"
#include "ioapic.h"
#include "opt_mpbios.h"
@@ -143,9 +147,8 @@ struct intrstub x2apic_level_stubs[MAX_I
#include <machine/i82093var.h>
#endif /* NIOAPIC */
+// XXX NR_EVENT_CHANNELS is 2048, use some sparse structure?
int irq2port[NR_EVENT_CHANNELS] = {0}; /* actually port + 1, so that 0 is invaid */
-static int irq2vect[256] = {0};
-static int vect2irq[256] = {0};
#if NACPICA > 0
#include <machine/mpconfig.h>
@@ -160,29 +163,6 @@ static int vect2irq[256] = {0};
#endif
#if defined(DOM0OPS) || NPCI > 0
-int
-xen_vec_alloc(int gsi)
-{
- KASSERT(gsi < 255);
-
- if (irq2port[gsi] == 0) {
- struct physdev_irq irq_op;
- irq_op.irq = gsi;
- if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector,
- &irq_op) < 0) {
- panic("PHYSDEVOP_ASSIGN_VECTOR gsi %d", gsi);
- }
- KASSERT(irq2vect[gsi] == 0 ||
- irq2vect[gsi] == irq_op.vector);
- irq2vect[gsi] = irq_op.vector;
- KASSERT(vect2irq[irq_op.vector] == 0 ||
- vect2irq[irq_op.vector] == gsi);
- vect2irq[irq_op.vector] = gsi;
- }
-
- return (irq2vect[gsi]);
-}
-
/*
* This function doesn't "allocate" anything. It merely translates our
* understanding of PIC to the XEN 'gsi' namespace. In the case of
@@ -193,6 +173,8 @@ xen_vec_alloc(int gsi)
int
xen_pic_to_gsi(struct pic *pic, int pin)
{
+ struct physdev_map_pirq map_irq;
+ int ret;
int gsi;
KASSERT(pic != NULL);
@@ -202,19 +184,59 @@ xen_pic_to_gsi(struct pic *pic, int pin)
* If so, legacy_irq should identity map correctly to gsi.
*/
gsi = pic->pic_vecbase + pin;
+ KASSERT(gsi < NR_EVENT_CHANNELS);
switch (pic->pic_type) {
case PIC_I8259:
KASSERT(gsi < 16);
- break;
+ /* FALLTHROUGH */
case PIC_IOAPIC:
+ {
+ KASSERT(gsi < 255);
+
+ memset(&map_irq, 0, sizeof(map_irq));
+ map_irq.domid = DOMID_SELF;
+ map_irq.type = MAP_PIRQ_TYPE_GSI;
+ map_irq.index = pin;
+ map_irq.pirq = gsi;
+ ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
+ if (ret != 0)
+ panic("physdev_op(PHYSDEVOP_map_pirq) fail");
break;
- default: /* XXX: MSI Support */
- panic("XXX: MSI(X) Support");
+ }
+ case PIC_MSI:
+ case PIC_MSIX:
+#ifdef __HAVE_PCI_MSI_MSIX
+ {
+ const struct msipic_pci_info *i = msipic_get_pci_info(pic);
+
+ memset(&map_irq, 0, sizeof(map_irq));
+ map_irq.domid = DOMID_SELF;
+ map_irq.type = MAP_PIRQ_TYPE_MSI_SEG;
+ map_irq.index = -1;
+ map_irq.pirq = -1;
+ map_irq.bus = i->mp_bus;
+ map_irq.devfn = (i->mp_dev << 3) | i->mp_fun;
+ KASSERT(i->mp_veccnt > 0);
+ map_irq.entry_nr = i->mp_veccnt;
+ if (pic->pic_type == PIC_MSI && i->mp_veccnt > 1) {
+ map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI;
+ } else if (pic->pic_type == PIC_MSIX) {
+ map_irq.table_base = i->mp_table_base;
+ }
+ ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
+ if (ret != 0)
+ panic("physdev_op(PHYSDEVOP_map_pirq) fail");
+ KASSERT(map_irq.entry_nr == i->mp_veccnt);
+ gsi = map_irq.pirq;
+ break;
+ }
+#endif
+ default:
+ panic("unknown pic_type %d", pic->pic_type);
break;
}
- KASSERT(gsi < 255);
return gsi;
}
Index: src/sys/arch/xen/x86/xen_intr.c
diff -u src/sys/arch/xen/x86/xen_intr.c:1.24 src/sys/arch/xen/x86/xen_intr.c:1.25
--- src/sys/arch/xen/x86/xen_intr.c:1.24 Sat Apr 25 15:26:17 2020
+++ src/sys/arch/xen/x86/xen_intr.c Mon May 4 15:55:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: xen_intr.c,v 1.24 2020/04/25 15:26:17 bouyer Exp $ */
+/* $NetBSD: xen_intr.c,v 1.25 2020/05/04 15:55:56 jdolecek Exp $ */
/*-
* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: xen_intr.c,v 1.24 2020/04/25 15:26:17 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: xen_intr.c,v 1.25 2020/05/04 15:55:56 jdolecek Exp $");
#include "opt_multiprocessor.h"
@@ -156,7 +156,7 @@ xen_intr_establish_xname(int legacy_irq,
#if (NPCI > 0 || NISA > 0) && defined(XENPV) /* XXX: support PVHVM pirq */
struct pintrhand *pih;
int gsi;
- int vector, evtchn;
+ int evtchn;
KASSERTMSG(legacy_irq == -1 || (0 <= legacy_irq && legacy_irq < NUM_XEN_IRQS),
"bad legacy IRQ value: %d", legacy_irq);
@@ -164,17 +164,17 @@ xen_intr_establish_xname(int legacy_irq,
"non-legacy IRQon i8259 ");
gsi = xen_pic_to_gsi(pic, pin);
+ KASSERTMSG(gsi < NR_EVENT_CHANNELS, "gsi %d >= NR_EVENT_CHANNELS %u",
+ gsi, (int)NR_EVENT_CHANNELS);
intrstr = intr_create_intrid(gsi, pic, pin, intrstr_buf,
sizeof(intrstr_buf));
- vector = xen_vec_alloc(gsi);
-
if (irq2port[gsi] == 0) {
extern struct cpu_info phycpu_info_primary; /* XXX */
struct cpu_info *ci = &phycpu_info_primary;
- pic->pic_addroute(pic, ci, pin, vector, type);
+ pic->pic_addroute(pic, ci, pin, gsi, type);
evtchn = bind_pirq_to_evtch(gsi);
KASSERT(evtchn > 0);
Index: src/sys/arch/xen/xen/evtchn.c
diff -u src/sys/arch/xen/xen/evtchn.c:1.91 src/sys/arch/xen/xen/evtchn.c:1.92
--- src/sys/arch/xen/xen/evtchn.c:1.91 Sat Apr 25 15:26:18 2020
+++ src/sys/arch/xen/xen/evtchn.c Mon May 4 15:55:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: evtchn.c,v 1.91 2020/04/25 15:26:18 bouyer Exp $ */
+/* $NetBSD: evtchn.c,v 1.92 2020/05/04 15:55:56 jdolecek Exp $ */
/*
* Copyright (c) 2006 Manuel Bouyer.
@@ -54,7 +54,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: evtchn.c,v 1.91 2020/04/25 15:26:18 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: evtchn.c,v 1.92 2020/05/04 15:55:56 jdolecek Exp $");
#include "opt_xen.h"
#include "isa.h"
@@ -80,6 +80,8 @@ __KERNEL_RCSID(0, "$NetBSD: evtchn.c,v 1
#include <xen/evtchn.h>
#include <xen/xenfunc.h>
+#define NR_PIRQS NR_EVENT_CHANNELS
+
/*
* This lock protects updates to the following mapping and reference-count
* arrays. The lock does not need to be acquired to read the mapping tables.
@@ -193,7 +195,7 @@ struct pic xen_pic = {
int debug_port = -1;
-// #define IRQ_DEBUG 4
+/* #define IRQ_DEBUG 4 */
/* http://mail-index.netbsd.org/port-amd64/2004/02/22/0000.html */
#ifdef MULTIPROCESSOR
