Module Name: src
Committed By: skrll
Date: Thu May 28 12:41:15 UTC 2020
Modified Files:
src/sys/arch/aarch64/include: armreg.h
Log Message:
Add some new CTR_EL0 bits
To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/aarch64/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/include/armreg.h
diff -u src/sys/arch/aarch64/include/armreg.h:1.47 src/sys/arch/aarch64/include/armreg.h:1.48
--- src/sys/arch/aarch64/include/armreg.h:1.47 Mon May 25 05:17:05 2020
+++ src/sys/arch/aarch64/include/armreg.h Thu May 28 12:41:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.47 2020/05/25 05:17:05 ryo Exp $ */
+/* $NetBSD: armreg.h,v 1.48 2020/05/28 12:41:15 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -108,6 +108,9 @@ reg_##regname##_write(uint64_t __val)
*/
AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register
+#define CTR_EL0_TMIN_LINE __BITS(37,32) // Tag MIN LINE size
+#define CTR_EL0_DIC __BIT(29) // Instruction cache requirement
+#define CTR_EL0_IDC __BIT(28) // Data Cache clean requirement
#define CTR_EL0_CWG_LINE __BITS(27,24) // Cacheback Writeback Granule
#define CTR_EL0_ERG_LINE __BITS(23,20) // Exclusives Reservation Granule
#define CTR_EL0_DMIN_LINE __BITS(19,16) // Dcache MIN LINE size (log2 - 2)
