Module Name: src
Committed By: skrll
Date: Wed Jun 3 15:38:02 UTC 2020
Modified Files:
src/sys/dev/usb: ohci.c ohcireg.h
Log Message:
Convert ohcireg.h to __BITS. NFCI.
To generate a diff of this commit:
cvs rdiff -u -r1.309 -r1.310 src/sys/dev/usb/ohci.c
cvs rdiff -u -r1.27 -r1.28 src/sys/dev/usb/ohcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/usb/ohci.c
diff -u src/sys/dev/usb/ohci.c:1.309 src/sys/dev/usb/ohci.c:1.310
--- src/sys/dev/usb/ohci.c:1.309 Tue May 26 07:03:22 2020
+++ src/sys/dev/usb/ohci.c Wed Jun 3 15:38:02 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: ohci.c,v 1.309 2020/05/26 07:03:22 skrll Exp $ */
+/* $NetBSD: ohci.c,v 1.310 2020/06/03 15:38:02 skrll Exp $ */
/*
* Copyright (c) 1998, 2004, 2005, 2012, 2016, 2020 The NetBSD Foundation, Inc.
@@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.309 2020/05/26 07:03:22 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.310 2020/06/03 15:38:02 skrll Exp $");
#ifdef _KERNEL_OPT
#include "opt_usb.h"
@@ -607,9 +607,12 @@ ohci_reset_std_chain(ohci_softc_t *sc, s
usb_syncmem(dma, 0, len,
rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
- const uint32_t tdflags = HTOO32(
- (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
- OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
+ const uint32_t tdflags = HTOO32(
+ OHCI_TD_SET_DP(rd ? OHCI_TD_DP_IN : OHCI_TD_DP_OUT) |
+ OHCI_TD_SET_CC(OHCI_TD_NOCC) |
+ OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_CARRY) |
+ OHCI_TD_SET_DI(OHCI_TD_NOINTR)
+ );
size_t curoffs = 0;
for (size_t j = 1; len != 0;) {
@@ -803,7 +806,7 @@ ohci_init(ohci_softc_t *sc)
"ohcixfer", NULL, IPL_USB, NULL, NULL, NULL);
rev = OREAD4(sc, OHCI_REVISION);
- aprint_normal("OHCI version %d.%d%s\n",
+ aprint_normal("OHCI version %" __PRIuBITS ".%" __PRIuBITS "%s\n",
OHCI_REV_HI(rev), OHCI_REV_LO(rev),
OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
@@ -927,16 +930,21 @@ ohci_init(ohci_softc_t *sc)
if ((ctl & OHCI_IR) == 0) {
aprint_error_dev(sc->sc_dev,
"SMM does not respond, resetting\n");
- OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
+ OWRITE4(sc, OHCI_CONTROL,
+ OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc);
goto reset;
}
#if 0
-/* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */
- } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
+ /*
+ * Don't bother trying to reuse the BIOS init, we'll reset it
+ * anyway.
+ */
+ } else if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_RESET) {
/* BIOS started controller. */
DPRINTF("BIOS active", 0, 0, 0, 0);
- if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
- OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc);
+ if (OHCI_GET_HCFS(ctl) != OHCI_HCFS_OPERATIONAL) {
+ OWRITE4(sc, OHCI_CONTROL,
+ OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc);
usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
}
#endif
@@ -952,7 +960,7 @@ ohci_init(ohci_softc_t *sc)
* without it some controllers do not start.
*/
DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0);
- OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
+ OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET) | rwc);
usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
/* We now own the host controller and the bus has been reset. */
@@ -987,7 +995,8 @@ ohci_init(ohci_softc_t *sc)
ctl = OREAD4(sc, OHCI_CONTROL);
ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
- OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc;
+ OHCI_CBSR_SET(OHCI_RATIO_1_4) |
+ OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL) | rwc;
/* And finally start it! */
OWRITE4(sc, OHCI_CONTROL, ctl);
@@ -996,8 +1005,8 @@ ohci_init(ohci_softc_t *sc)
* registers that should be set earlier, but that the
* controller ignores when in the SUSPEND state.
*/
- ival = OHCI_GET_IVAL(fm);
- fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
+ ival = OHCI_FM_GET_IVAL(fm);
+ fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FM_FIT) ^ OHCI_FM_FIT;
fm |= OHCI_FSMPS(ival) | ival;
OWRITE4(sc, OHCI_FM_INTERVAL, fm);
per = OHCI_PERIODIC(ival); /* 90% periodic */
@@ -1005,19 +1014,19 @@ ohci_init(ohci_softc_t *sc)
if (sc->sc_flags & OHCIF_SUPERIO) {
/* no overcurrent protection */
- desca |= OHCI_NOCP;
+ desca |= OHCI_RHD_NOCP;
/*
* Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning
* that
* - ports are always power switched
* - don't wait for powered root hub port
*/
- desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS);
+ desca &= ~(OHCI_RHD_POTPGT_MASK | OHCI_RHD_NPS);
}
/* Fiddle the No OverCurrent Protection bit to avoid chip bug. */
- OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP);
- OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
+ OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_RHD_NOCP);
+ OWRITE4(sc, OHCI_RH_STATUS, OHCI_RHS_LPSC); /* Enable port power */
usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY);
OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca);
@@ -1028,7 +1037,8 @@ ohci_init(ohci_softc_t *sc)
sc->sc_noport = 0;
for (i = 0; i < 10 && sc->sc_noport == 0; i++) {
usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY);
- sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
+ sc->sc_noport =
+ OHCI_RHD_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
}
#ifdef OHCI_DEBUG
@@ -1122,7 +1132,7 @@ ohci_shutdown(device_t self, int flags)
DPRINTF("stopping the HC", 0, 0, 0, 0);
OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
- OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
+ OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET));
return true;
}
@@ -1149,10 +1159,10 @@ ohci_resume(device_t dv, const pmf_qual_
ctl = sc->sc_control;
else
ctl = OREAD4(sc, OHCI_CONTROL);
- ctl |= OHCI_HCFS_RESUME;
+ ctl |= OHCI_SET_HCFS(OHCI_HCFS_RESUME);
OWRITE4(sc, OHCI_CONTROL, ctl);
usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
- ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
+ ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_SET_HCFS(OHCI_HCFS_OPERATIONAL);
OWRITE4(sc, OHCI_CONTROL, ctl);
usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
sc->sc_control = sc->sc_intre = 0;
@@ -1184,7 +1194,7 @@ ohci_suspend(device_t dv, const pmf_qual
sc->sc_intre = OREAD4(sc,
OHCI_INTERRUPT_ENABLE);
}
- ctl |= OHCI_HCFS_SUSPEND;
+ ctl |= OHCI_SET_HCFS(OHCI_HCFS_SUSPEND);
OWRITE4(sc, OHCI_CONTROL, ctl);
usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
@@ -1337,7 +1347,7 @@ ohci_intr1(ohci_softc_t *sc)
DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0);
printf("%s: unrecoverable error, controller halted\n",
device_xname(sc->sc_dev));
- OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
+ OWRITE4(sc, OHCI_CONTROL, OHCI_SET_HCFS(OHCI_HCFS_RESET));
/* XXX what else */
}
if (eintrs & OHCI_RHSC) {
@@ -1595,7 +1605,7 @@ ohci_softintr(void *v)
== OHCI_CC_NOT_ACCESSED)
len = 0;
else
- len = OHCI_ITD_PSW_LENGTH(len);
+ len = OHCI_ITD_PSW_SIZE(len);
xfer->ux_frlengths[i] = len;
actlen += len;
}
@@ -1928,9 +1938,9 @@ ohci_dump_td(ohci_softc_t *sc, ohci_soft
DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0);
DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx",
!!(flags & OHCI_TD_R),
- __SHIFTOUT(flags, OHCI_TD_DP_MASK),
+ OHCI_TD_GET_DP(flags),
OHCI_TD_GET_DI(flags),
- __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK));
+ OHCI_TD_GET_TOGGLE(flags));
DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags),
OHCI_TD_GET_CC(flags), 0, 0);
DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx",
@@ -1994,10 +2004,10 @@ ohci_dump_ed(ohci_softc_t *sc, ohci_soft
OHCI_ED_GET_MAXP(flags),
0);
DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd",
- __SHIFTOUT(flags, OHCI_ED_DIR_MASK),
- !!(flags & OHCI_ED_SPEED),
- !!(flags & OHCI_ED_SKIP),
- !!(flags & OHCI_ED_FORMAT_ISO));
+ OHCI_ED_GET_DIR(flags),
+ __SHIFTOUT(flags, OHCI_ED_SPEED),
+ __SHIFTOUT(flags, OHCI_ED_SKIP),
+ OHCI_ED_GET_FORMAT(flags));
DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp),
0, 0, 0);
DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd",
@@ -2060,11 +2070,11 @@ ohci_open(struct usbd_pipe *pipe)
opipe->tail.itd = sitd;
tdphys = sitd->physaddr;
- fmt = OHCI_ED_FORMAT_ISO;
+ fmt = OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_ISO);
if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
- fmt |= OHCI_ED_DIR_IN;
+ fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_IN);
else
- fmt |= OHCI_ED_DIR_OUT;
+ fmt |= OHCI_ED_SET_DIR(OHCI_ED_DIR_OUT);
} else {
std = ohci_alloc_std(sc);
if (std == NULL)
@@ -2072,7 +2082,9 @@ ohci_open(struct usbd_pipe *pipe)
opipe->tail.td = std;
tdphys = std->physaddr;
- fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD;
+ fmt =
+ OHCI_ED_SET_FORMAT(OHCI_ED_FORMAT_GEN) |
+ OHCI_ED_SET_DIR(OHCI_ED_DIR_TD);
}
sed->ed.ed_flags = HTOO32(
OHCI_ED_SET_FA(addr) |
@@ -2416,11 +2428,11 @@ ohci_roothub_ctrl(struct usbd_bus *bus,
v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
hubd.bNbrPorts = sc->sc_noport;
USETW(hubd.wHubCharacteristics,
- (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
- v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
+ (v & OHCI_RHD_NPS ? UHD_PWR_NO_SWITCH :
+ v & OHCI_RHD_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
/* XXX overcurrent */
);
- hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
+ hubd.bPwrOn2PwrGood = OHCI_RHD_GET_POTPGT(v);
v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
hubd.DeviceRemovable[i++] = (uint8_t)v;
@@ -2714,11 +2726,11 @@ ohci_device_ctrl_start(struct usbd_xfer
sed = opipe->sed;
KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr,
- "address ED %d pipe %d\n",
+ "address ED %" __PRIuBITS " pipe %d\n",
OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr);
KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) ==
UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize),
- "MPL ED %d pipe %d\n",
+ "MPL ED %" __PRIuBITS " pipe %d\n",
OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)),
UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize));
@@ -2744,7 +2756,7 @@ ohci_device_ctrl_start(struct usbd_xfer
std = ox->ox_stds[0];
/* Start toggle at 1 and then use the carried toggle. */
std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK);
- std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1);
+ std->td.td_flags |= HTOO32(OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1));
usb_syncmem(&std->dma,
std->offs + offsetof(ohci_td_t, td_flags),
sizeof(std->td.td_flags),
@@ -2760,8 +2772,12 @@ ohci_device_ctrl_start(struct usbd_xfer
memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req));
usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
- setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC |
- OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
+ setup->td.td_flags = HTOO32(
+ OHCI_TD_SET_DP(OHCI_TD_DP_SETUP) |
+ OHCI_TD_SET_CC(OHCI_TD_NOCC) |
+ OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_0) |
+ OHCI_TD_SET_DI(OHCI_TD_NOINTR)
+ );
setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0));
setup->td.td_nexttd = HTOO32(next->physaddr);
setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1);
@@ -2776,8 +2792,11 @@ ohci_device_ctrl_start(struct usbd_xfer
BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
stat->td.td_flags = HTOO32(
- (isread ? OHCI_TD_OUT : OHCI_TD_IN) |
- OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
+ OHCI_TD_SET_DP(isread ? OHCI_TD_DP_OUT : OHCI_TD_DP_IN) |
+ OHCI_TD_SET_CC(OHCI_TD_NOCC) |
+ OHCI_TD_SET_TOGGLE(OHCI_TD_TOGGLE_1) |
+ OHCI_TD_SET_DI(1)
+ );
stat->td.td_cbp = 0;
stat->td.td_nexttd = HTOO32(tail->physaddr);
stat->td.td_be = 0;
@@ -2992,7 +3011,7 @@ ohci_device_bulk_start(struct usbd_xfer
KASSERT(opipe->tail.td == tail);
/* We want interrupt at the end of the transfer. */
- last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
+ last->td.td_flags &= HTOO32(~OHCI_TD_DI_MASK);
last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
last->td.td_nexttd = HTOO32(tail->physaddr);
last->nexttd = tail;
@@ -3191,7 +3210,7 @@ ohci_device_intr_start(struct usbd_xfer
KASSERT(opipe->tail.td == tail);
/* We want interrupt at the end of the transfer. */
- last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
+ last->td.td_flags &= HTOO32(~OHCI_TD_DI_MASK);
last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
last->td.td_nexttd = HTOO32(tail->physaddr);
@@ -3536,10 +3555,11 @@ ohci_device_isoc_enter(struct usbd_xfer
/* Fill current ITD */
sitd->itd.itd_flags = HTOO32(
- OHCI_ITD_NOCC |
- OHCI_ITD_SET_SF(isoc->next) |
- OHCI_ITD_SET_DI(6) | /* delay intr a little */
- OHCI_ITD_SET_FC(ncur));
+ OHCI_ITD_SET_CC(OHCI_ITD_NOCC) |
+ OHCI_ITD_SET_SF(isoc->next) |
+ OHCI_ITD_SET_DI(6) | /* delay intr a little */
+ OHCI_ITD_SET_FC(ncur)
+ );
sitd->itd.itd_bp0 = HTOO32(bp0);
sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
sitd->itd.itd_be = HTOO32(end);
@@ -3574,10 +3594,11 @@ ohci_device_isoc_enter(struct usbd_xfer
/* Fixup last used ITD */
sitd->itd.itd_flags = HTOO32(
- OHCI_ITD_NOCC |
- OHCI_ITD_SET_SF(isoc->next) |
- OHCI_ITD_SET_DI(0) |
- OHCI_ITD_SET_FC(ncur));
+ OHCI_ITD_SET_CC(OHCI_ITD_NOCC) |
+ OHCI_ITD_SET_SF(isoc->next) |
+ OHCI_ITD_SET_DI(0) |
+ OHCI_ITD_SET_FC(ncur)
+ );
sitd->itd.itd_bp0 = HTOO32(bp0);
sitd->itd.itd_nextitd = HTOO32(tail->physaddr);
sitd->itd.itd_be = HTOO32(end);
Index: src/sys/dev/usb/ohcireg.h
diff -u src/sys/dev/usb/ohcireg.h:1.27 src/sys/dev/usb/ohcireg.h:1.28
--- src/sys/dev/usb/ohcireg.h:1.27 Sat Apr 23 10:15:32 2016
+++ src/sys/dev/usb/ohcireg.h Wed Jun 3 15:38:02 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: ohcireg.h,v 1.27 2016/04/23 10:15:32 skrll Exp $ */
+/* $NetBSD: ohcireg.h,v 1.28 2020/06/03 15:38:02 skrll Exp $ */
/* $FreeBSD: src/sys/dev/usb/ohcireg.h,v 1.8 1999/11/17 22:33:40 n_hibma Exp $ */
/*
@@ -43,79 +43,91 @@
/*** OHCI registers */
#define OHCI_REVISION 0x00 /* OHCI revision # */
-#define OHCI_REV_LO(rev) ((rev)&0xf)
-#define OHCI_REV_HI(rev) (((rev)>>4)&0xf)
-#define OHCI_REV_LEGACY(rev) ((rev) & 0x100)
+#define OHCI_REV_LO_MASK __BITS(3,0)
+#define OHCI_REV_HI_MASK __BITS(7,4)
+#define OHCI_REV_LO(rev) __SHIFTOUT((rev), OHCI_REV_LO_MASK)
+#define OHCI_REV_HI(rev) __SHIFTOUT((rev), OHCI_REV_HI_MASK)
+#define OHCI_REV_LEGACY_MASK __BIT(8)
+#define OHCI_REV_LEGACY(rev) __SHIFTOUT((rev), OHCI_REV_LEGACY_MASK)
#define OHCI_CONTROL 0x04
-#define OHCI_CBSR_MASK 0x00000003 /* Control/Bulk Service Ratio */
-#define OHCI_RATIO_1_1 0x00000000
-#define OHCI_RATIO_1_2 0x00000001
-#define OHCI_RATIO_1_3 0x00000002
-#define OHCI_RATIO_1_4 0x00000003
-#define OHCI_PLE 0x00000004 /* Periodic List Enable */
-#define OHCI_IE 0x00000008 /* Isochronous Enable */
-#define OHCI_CLE 0x00000010 /* Control List Enable */
-#define OHCI_BLE 0x00000020 /* Bulk List Enable */
-#define OHCI_HCFS_MASK 0x000000c0 /* HostControllerFunctionalState */
-#define OHCI_HCFS_RESET 0x00000000
-#define OHCI_HCFS_RESUME 0x00000040
-#define OHCI_HCFS_OPERATIONAL 0x00000080
-#define OHCI_HCFS_SUSPEND 0x000000c0
-#define OHCI_IR 0x00000100 /* Interrupt Routing */
-#define OHCI_RWC 0x00000200 /* Remote Wakeup Connected */
-#define OHCI_RWE 0x00000400 /* Remote Wakeup Enabled */
+#define OHCI_CBSR_MASK __BITS(1,0) /* Control/Bulk Service Ratio */
+#define OHCI_CBSR_SET(x) __SHIFTIN((x), OHCI_CBSR_MASK)
+#define OHCI_RATIO_1_1 0
+#define OHCI_RATIO_1_2 1
+#define OHCI_RATIO_1_3 2
+#define OHCI_RATIO_1_4 3
+#define OHCI_PLE __BIT(2) /* Periodic List Enable */
+#define OHCI_IE __BIT(3) /* Isochronous Enable */
+#define OHCI_CLE __BIT(4) /* Control List Enable */
+#define OHCI_BLE __BIT(5) /* Bulk List Enable */
+#define OHCI_HCFS_MASK __BITS(7,6) /* HostControllerFunctionalState */
+#define OHCI_SET_HCFS(x) __SHIFTIN((x), OHCI_HCFS_MASK)
+#define OHCI_GET_HCFS(x) __SHIFTOUT((x), OHCI_HCFS_MASK)
+#define OHCI_HCFS_RESET 0
+#define OHCI_HCFS_RESUME 1
+#define OHCI_HCFS_OPERATIONAL 2
+#define OHCI_HCFS_SUSPEND 3
+#define OHCI_IR __BIT(8) /* Interrupt Routing */
+#define OHCI_RWC __BIT(9) /* Remote Wakeup Connected */
+#define OHCI_RWE __BIT(10) /* Remote Wakeup Enabled */
#define OHCI_COMMAND_STATUS 0x08
-#define OHCI_HCR 0x00000001 /* Host Controller Reset */
-#define OHCI_CLF 0x00000002 /* Control List Filled */
-#define OHCI_BLF 0x00000004 /* Bulk List Filled */
-#define OHCI_OCR 0x00000008 /* Ownership Change Request */
-#define OHCI_SOC_MASK 0x00030000 /* Scheduling Overrun Count */
+#define OHCI_HCR __BIT(0) /* Host Controller Reset */
+#define OHCI_CLF __BIT(1) /* Control List Filled */
+#define OHCI_BLF __BIT(2) /* Bulk List Filled */
+#define OHCI_OCR __BIT(3) /* Ownership Change Request */
+#define OHCI_SOC_MASK __BITS(17,16) /* Scheduling Overrun Count */
#define OHCI_INTERRUPT_STATUS 0x0c
-#define OHCI_SO 0x00000001 /* Scheduling Overrun */
-#define OHCI_WDH 0x00000002 /* Writeback Done Head */
-#define OHCI_SF 0x00000004 /* Start of Frame */
-#define OHCI_RD 0x00000008 /* Resume Detected */
-#define OHCI_UE 0x00000010 /* Unrecoverable Error */
-#define OHCI_FNO 0x00000020 /* Frame Number Overflow */
-#define OHCI_RHSC 0x00000040 /* Root Hub Status Change */
-#define OHCI_OC 0x40000000 /* Ownership Change */
-#define OHCI_MIE 0x80000000 /* Master Interrupt Enable */
+#define OHCI_SO __BIT(0) /* Scheduling Overrun */
+#define OHCI_WDH __BIT(1) /* Writeback Done Head */
+#define OHCI_SF __BIT(2) /* Start of Frame */
+#define OHCI_RD __BIT(3) /* Resume Detected */
+#define OHCI_UE __BIT(4) /* Unrecoverable Error */
+#define OHCI_FNO __BIT(5) /* Frame Number Overflow */
+#define OHCI_RHSC __BIT(6) /* Root Hub Status Change */
+#define OHCI_OC __BIT(30) /* Ownership Change */
+#define OHCI_MIE __BIT(31) /* Master Interrupt Enable */
#define OHCI_INTERRUPT_ENABLE 0x10
#define OHCI_INTERRUPT_DISABLE 0x14
#define OHCI_HCCA 0x18
#define OHCI_PERIOD_CURRENT_ED 0x1c
+#define OHCI_PERIOD_CURRENT_ED 0x1c
#define OHCI_CONTROL_HEAD_ED 0x20
#define OHCI_CONTROL_CURRENT_ED 0x24
#define OHCI_BULK_HEAD_ED 0x28
#define OHCI_BULK_CURRENT_ED 0x2c
#define OHCI_DONE_HEAD 0x30
#define OHCI_FM_INTERVAL 0x34
-#define OHCI_GET_IVAL(s) ((s) & 0x3fff)
-#define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff)
-#define OHCI_FIT 0x80000000
+#define OHCI_FM_IVAL_MASK __BITS(13,0)
+#define OHCI_FM_GET_IVAL(x) __SHIFTOUT((x), OHCI_FM_IVAL_MASK)
+#define OHCI_FM_FSMPS_MASK __BITS(30,16)
+#define OHCI_FM_GET_FSMPS(x) __SHIFTOUT((x), OHCI_FM_FSMPS_MASK)
+#define OHCI_FM_SET_FSMPS(x) __SHIFTIN((x), OHCI_FM_FSMPS_MASK)
+#define OHCI_FM_FIT __BIT(31)
#define OHCI_FM_REMAINING 0x38
#define OHCI_FM_NUMBER 0x3c
#define OHCI_PERIODIC_START 0x40
#define OHCI_LS_THRESHOLD 0x44
#define OHCI_RH_DESCRIPTOR_A 0x48
-#define OHCI_GET_NDP(s) ((s) & 0xff)
-#define OHCI_PSM 0x0100 /* Power Switching Mode */
-#define OHCI_NPS 0x0200 /* No Power Switching */
-#define OHCI_DT 0x0400 /* Device Type */
-#define OHCI_OCPM 0x0800 /* Overcurrent Protection Mode */
-#define OHCI_NOCP 0x1000 /* No Overcurrent Protection */
-#define OHCI_GET_POTPGT(s) ((s) >> 24)
-#define OHCI_POTPGT_MASK 0xff000000
+#define OHCI_RHD_NDP_MASK __BITS(7,0)
+#define OHCI_RHD_GET_NDP(x) __SHIFTOUT((x), OHCI_RHD_NDP_MASK)
+#define OHCI_RHD_PSM __BIT(8) /* Power Switching Mode */
+#define OHCI_RHD_NPS __BIT(9) /* No Power Switching */
+#define OHCI_RHD_DT __BIT(10) /* Device Type */
+#define OHCI_RHD_OCPM __BIT(11) /* Overcurrent Protection Mode */
+#define OHCI_RHD_NOCP __BIT(12) /* No Overcurrent Protection */
+#define OHCI_RHD_POTPGT_MASK __BITS(31,24)
+#define OHCI_RHD_GET_POTPGT(x) __SHIFTOUT((x), OHCI_RHD_POTPGT_MASK)
+#define OHCI_RHD_SET_POTPGT(x) __SHIFTIN((x), OHCI_RHD_POTPGT_MASK)
#define OHCI_RH_DESCRIPTOR_B 0x4c
#define OHCI_RH_STATUS 0x50
-#define OHCI_LPS 0x00000001 /* Local Power Status */
-#define OHCI_OCI 0x00000002 /* OverCurrent Indicator */
-#define OHCI_DRWE 0x00008000 /* Device Remote Wakeup Enable */
-#define OHCI_LPSC 0x00010000 /* Local Power Status Change */
-#define OHCI_CCIC 0x00020000 /* OverCurrent Indicator Change */
-#define OHCI_CRWE 0x80000000 /* Clear Remote Wakeup Enable */
-#define OHCI_RH_PORT_STATUS(n) (0x50 + (n)*4) /* 1 based indexing */
+#define OHCI_RHS_LPS __BIT(0) /* Local Power Status */
+#define OHCI_RHS_OCI __BIT(1) /* OverCurrent Indicator */
+#define OHCI_RHS_DRWE __BIT(15) /* Device Remote Wakeup Enable */
+#define OHCI_RHS_LPSC __BIT(16) /* Local Power Status Change */
+#define OHCI_RHS_CCIC __BIT(17) /* OverCurrent Indicator Change */
+#define OHCI_RHS_CRWE __BIT(31) /* Clear Remote Wakeup Enable */
+#define OHCI_RH_PORT_STATUS(n) (0x50 + (n)*4) /* 1 based indexing */
#define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE)
#define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | OHCI_RD | OHCI_UE | \
@@ -143,27 +155,33 @@ struct ohci_hcca {
typedef struct {
volatile uint32_t ed_flags;
-#define OHCI_ED_GET_FA(s) ((s) & 0x7f)
-#define OHCI_ED_ADDRMASK 0x0000007f
-#define OHCI_ED_SET_FA(s) (s)
-#define OHCI_ED_GET_EN(s) (((s) >> 7) & 0xf)
-#define OHCI_ED_SET_EN(s) ((s) << 7)
-#define OHCI_ED_DIR_MASK 0x00001800
-#define OHCI_ED_DIR_TD 0x00000000
-#define OHCI_ED_DIR_OUT 0x00000800
-#define OHCI_ED_DIR_IN 0x00001000
-#define OHCI_ED_SPEED 0x00002000
-#define OHCI_ED_SKIP 0x00004000
-#define OHCI_ED_FORMAT_GEN 0x00000000
-#define OHCI_ED_FORMAT_ISO 0x00008000
-#define OHCI_ED_GET_MAXP(s) (((s) >> 16) & 0x07ff)
-#define OHCI_ED_SET_MAXP(s) ((s) << 16)
-#define OHCI_ED_MAXPMASK (0x7ff << 16)
+#define OHCI_ED_ADDR_MASK __BITS(6,0)
+#define OHCI_ED_GET_FA(x) __SHIFTOUT((x), OHCI_ED_ADDR_MASK)
+#define OHCI_ED_SET_FA(x) __SHIFTIN((x), OHCI_ED_ADDR_MASK)
+#define OHCI_ED_EN_MASK __BITS(10,7)
+#define OHCI_ED_GET_EN(x) __SHIFTOUT((x), OHCI_ED_EN_MASK)
+#define OHCI_ED_SET_EN(x) __SHIFTIN((x), OHCI_ED_EN_MASK)
+#define OHCI_ED_DIR_MASK __BITS(12,11)
+#define OHCI_ED_GET_DIR(x) __SHIFTOUT((x), OHCI_ED_DIR_MASK)
+#define OHCI_ED_SET_DIR(x) __SHIFTIN((x), OHCI_ED_DIR_MASK)
+#define OHCI_ED_DIR_TD 0
+#define OHCI_ED_DIR_OUT 1
+#define OHCI_ED_DIR_IN 2
+#define OHCI_ED_SPEED __BIT(13)
+#define OHCI_ED_SKIP __BIT(14)
+#define OHCI_ED_FORMAT_MASK __BIT(15)
+#define OHCI_ED_GET_FORMAT(x) __SHIFTOUT((x), OHCI_ED_FORMAT_MASK)
+#define OHCI_ED_SET_FORMAT(x) __SHIFTIN((x), OHCI_ED_FORMAT_MASK)
+#define OHCI_ED_FORMAT_GEN 0
+#define OHCI_ED_FORMAT_ISO 1
+#define OHCI_ED_MAXP_MASK __BITS(26,16)
+#define OHCI_ED_GET_MAXP(x) __SHIFTOUT((x), OHCI_ED_MAXP_MASK)
+#define OHCI_ED_SET_MAXP(x) __SHIFTIN((x), OHCI_ED_MAXP_MASK)
volatile ohci_physaddr_t ed_tailp;
volatile ohci_physaddr_t ed_headp;
-#define OHCI_HALTED 0x00000001
-#define OHCI_TOGGLECARRY 0x00000002
-#define OHCI_HEADMASK 0xfffffffc
+#define OHCI_HALTED __BIT(0)
+#define OHCI_TOGGLECARRY __BIT(1)
+#define OHCI_HEADMASK __BITS(31,2)
volatile ohci_physaddr_t ed_nexted;
} ohci_ed_t;
/* #define OHCI_ED_SIZE 16 */
@@ -171,22 +189,31 @@ typedef struct {
typedef struct {
volatile uint32_t td_flags;
-#define OHCI_TD_R 0x00040000 /* Buffer Rounding */
-#define OHCI_TD_DP_MASK 0x00180000 /* Direction / PID */
-#define OHCI_TD_SETUP 0x00000000
-#define OHCI_TD_OUT 0x00080000
-#define OHCI_TD_IN 0x00100000
-#define OHCI_TD_GET_DI(x) (((x) >> 21) & 7) /* Delay Interrupt */
-#define OHCI_TD_SET_DI(x) ((x) << 21)
-#define OHCI_TD_NOINTR 0x00e00000
-#define OHCI_TD_INTR_MASK 0x00e00000
-#define OHCI_TD_TOGGLE_CARRY 0x00000000
-#define OHCI_TD_TOGGLE_0 0x02000000
-#define OHCI_TD_TOGGLE_1 0x03000000
-#define OHCI_TD_TOGGLE_MASK 0x03000000
-#define OHCI_TD_GET_EC(x) (((x) >> 26) & 3) /* Error Count */
-#define OHCI_TD_GET_CC(x) ((x) >> 28) /* Condition Code */
-#define OHCI_TD_NOCC 0xf0000000
+#define OHCI_TD_R __BIT(18) /* Buffer Rounding */
+#define OHCI_TD_DP_MASK __BITS(20,19) /* Direction / PID */
+#define OHCI_TD_GET_DP(x) __SHIFTOUT((x), OHCI_TD_DP_MASK)
+#define OHCI_TD_SET_DP(x) __SHIFTIN((x), OHCI_TD_DP_MASK)
+#define OHCI_TD_DP_SETUP 0
+#define OHCI_TD_DP_OUT 1
+#define OHCI_TD_DP_IN 2
+#define OHCI_TD_DI_MASK __BITS(23,21) /* Delay Interrupt */
+#define OHCI_TD_GET_DI(x) __SHIFTOUT((x), OHCI_TD_DI_MASK)
+#define OHCI_TD_SET_DI(x) __SHIFTIN((x), OHCI_TD_DI_MASK)
+#define OHCI_TD_NOINTR __SHIFTOUT_MASK(OHCI_TD_DI_MASK)
+#define OHCI_TD_TOGGLE_MASK __BITS(25,24) /* Toggle */
+#define OHCI_TD_GET_TOGGLE(x) __SHIFTOUT((x), OHCI_TD_TOGGLE_MASK)
+#define OHCI_TD_SET_TOGGLE(x) __SHIFTIN((x), OHCI_TD_TOGGLE_MASK)
+#define OHCI_TD_TOGGLE_CARRY 0
+#define OHCI_TD_TOGGLE_0 2
+#define OHCI_TD_TOGGLE_1 3
+#define OHCI_TD_EC_MASK __BITS(27,26) /* Error Count */
+#define OHCI_TD_GET_EC(x) __SHIFTOUT((x), OHCI_TD_EC_MASK)
+#define OHCI_TD_CC_MASK __BITS(31,28) /* Condition Code */
+#define OHCI_TD_GET_CC(x) __SHIFTOUT((x), OHCI_TD_CC_MASK)
+#define OHCI_TD_SET_CC(x) __SHIFTIN((x), OHCI_TD_CC_MASK)
+
+#define OHCI_TD_NOCC __SHIFTOUT_MASK(OHCI_TD_CC_MASK)
+
volatile ohci_physaddr_t td_cbp; /* Current Buffer Pointer */
volatile ohci_physaddr_t td_nexttd; /* Next TD */
volatile ohci_physaddr_t td_be; /* Buffer End */
@@ -197,24 +224,31 @@ typedef struct {
#define OHCI_ITD_NOFFSET 8
typedef struct {
volatile uint32_t itd_flags;
-#define OHCI_ITD_GET_SF(x) ((x) & 0x0000ffff)
-#define OHCI_ITD_SET_SF(x) ((x) & 0xffff)
-#define OHCI_ITD_GET_DI(x) (((x) >> 21) & 7) /* Delay Interrupt */
-#define OHCI_ITD_SET_DI(x) ((x) << 21)
-#define OHCI_ITD_NOINTR 0x00e00000
-#define OHCI_ITD_GET_FC(x) ((((x) >> 24) & 7)+1) /* Frame Count */
-#define OHCI_ITD_SET_FC(x) (((x)-1) << 24)
-#define OHCI_ITD_GET_CC(x) ((x) >> 28) /* Condition Code */
-#define OHCI_ITD_NOCC 0xf0000000
- volatile ohci_physaddr_t itd_bp0; /* Buffer Page 0 */
- volatile ohci_physaddr_t itd_nextitd; /* Next ITD */
- volatile ohci_physaddr_t itd_be; /* Buffer End */
+#define OHCI_ITD_SF_MASK __BITS(15,0)
+#define OHCI_ITD_GET_SF(x) __SHIFTOUT((x), OHCI_ITD_SF_MASK)
+#define OHCI_ITD_SET_SF(x) __SHIFTIN((x), OHCI_ITD_SF_MASK)
+#define OHCI_ITD_DI_MASK __BITS(23,21) /* Delay Interrupt */
+#define OHCI_ITD_GET_DI(x) __SHIFTOUT((x), OHCI_ITD_DI_MASK)
+#define OHCI_ITD_SET_DI(x) __SHIFTIN((x), OHCI_ITD_DI_MASK)
+#define OHCI_ITD_FC_MASK __BITS(26,24) /* Frame Count */
+#define OHCI_ITD_GET_FC(x) (__SHIFTOUT((x), OHCI_ITD_FC_MASK) + 1)
+#define OHCI_ITD_SET_FC(x) __SHIFTIN(((x) - 1), OHCI_ITD_FC_MASK)
+#define OHCI_ITD_CC_MASK __BITS(31,28) /* Condition Code */
+#define OHCI_ITD_GET_CC(x) __SHIFTOUT((x), OHCI_ITD_CC_MASK)
+#define OHCI_ITD_SET_CC(x) __SHIFTIN((x), OHCI_ITD_CC_MASK)
+#define OHCI_ITD_NOCC __SHIFTOUT_MASK(OHCI_ITD_CC_MASK)
+ volatile ohci_physaddr_t itd_bp0; /* Buffer Page 0 */
+ volatile ohci_physaddr_t itd_nextitd; /* Next ITD */
+ volatile ohci_physaddr_t itd_be; /* Buffer End */
volatile uint16_t itd_offset[OHCI_ITD_NOFFSET];/* Buffer offsets */
-#define itd_pswn itd_offset /* Packet Status Word*/
-#define OHCI_ITD_PAGE_SELECT 0x00001000
+#define itd_pswn itd_offset /* Packet Status Word*/
+#define OHCI_ITD_PAGE_SELECT __BIT(12)
#define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff))
-#define OHCI_ITD_PSW_LENGTH(x) ((x) & 0xfff) /* Transfer length */
-#define OHCI_ITD_PSW_GET_CC(x) ((x) >> 12) /* Condition Code */
+
+#define OHCI_ITD_PSW_SIZE_MASK __BITS(10,0) /* Transfer length */
+#define OHCI_ITD_PSW_SIZE(x) __SHIFTOUT((x), OHCI_ITD_PSW_SIZE_MASK)
+#define OHCI_ITD_PSW_CC_MASK __BITS(15,12) /* Condition Code */
+#define OHCI_ITD_PSW_GET_CC(x) __SHIFTOUT((x), OHCI_ITD_PSW_CC_MASK)
} ohci_itd_t;
/* #define OHCI_ITD_SIZE 32 */
#define OHCI_ITD_ALIGN 32
