Module Name: src
Committed By: msaitoh
Date: Wed Jun 10 03:39:03 UTC 2020
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add SRBDS_CTRL bit.
To generate a diff of this commit:
cvs rdiff -u -r1.166 -r1.167 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.166 src/sys/arch/x86/include/specialreg.h:1.167
--- src/sys/arch/x86/include/specialreg.h:1.166 Mon Jun 1 08:32:39 2020
+++ src/sys/arch/x86/include/specialreg.h Wed Jun 10 03:39:03 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.166 2020/06/01 08:32:39 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.167 2020/06/10 03:39:03 msaitoh Exp $ */
/*
* Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -478,6 +478,7 @@
#define CPUID_SEF_AVX512_4FMAPS __BIT(3)
#define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOV */
#define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8)
+#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */
#define CPUID_SEF_MD_CLEAR __BIT(10)
#define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
#define CPUID_SEF_SERIALIZE __BIT(14)
@@ -494,7 +495,7 @@
#define CPUID_SEF_FLAGS2 "\20" \
"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
"\5" "FSREP_MOV" \
- "\11" "VP2INTERSECT" "\13" "MD_CLEAR" \
+ "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" \
"\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \
"\21" "TSXLDTRK" \
"\25" "CET_IBT" \
