Module Name: src
Committed By: tsutsui
Date: Sun Jun 14 14:16:49 UTC 2020
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Use 32 byte cacheline ops (not 16 byte ones) for R5000 picache. PR/55138
Commented "I think this is bad copy&paste" from skrll@.
No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.
To generate a diff of this commit:
cvs rdiff -u -r1.66 -r1.67 src/sys/arch/mips/mips/cache.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/cache.c
diff -u src/sys/arch/mips/mips/cache.c:1.66 src/sys/arch/mips/mips/cache.c:1.67
--- src/sys/arch/mips/mips/cache.c:1.66 Sun Jun 14 12:58:01 2020
+++ src/sys/arch/mips/mips/cache.c Sun Jun 14 14:16:49 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.c,v 1.66 2020/06/14 12:58:01 simonb Exp $ */
+/* $NetBSD: cache.c,v 1.67 2020/06/14 14:16:49 tsutsui Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.66 2020/06/14 12:58:01 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.67 2020/06/14 14:16:49 tsutsui Exp $");
#include "opt_cputype.h"
#include "opt_mips_cache.h"
@@ -495,11 +495,11 @@ primary_cache_is_2way:
case 32:
/* used internally by mipsNN_picache_sync_range */
mco->mco_intern_icache_sync_range =
- cache_r4k_icache_hit_inv_16;
+ cache_r4k_icache_hit_inv_32;
/* used internally by mipsNN_picache_sync_range_index */
mco->mco_intern_icache_sync_range_index =
- cache_r4k_icache_index_inv_16;
+ cache_r4k_icache_index_inv_32;
break;
default:
