Module Name: src
Committed By: simonb
Date: Thu Jun 18 13:52:08 UTC 2020
Modified Files:
src/sys/arch/mips/cavium: octeonreg.h octeonvar.h
src/sys/arch/mips/cavium/dev: if_cnmac.c octeon_asxvar.h
octeon_cop2reg.h octeon_cop2var.h octeon_fau.c octeon_faureg.h
octeon_fauvar.h octeon_fpa.c octeon_fpareg.h octeon_fpavar.h
octeon_gmx.c octeon_gmxreg.h octeon_gmxvar.h octeon_ipd.c
octeon_ipdreg.h octeon_ipdvar.h octeon_l2creg.h octeon_mpireg.h
octeon_pip.c octeon_pipreg.h octeon_pipvar.h octeon_pko.c
octeon_pkoreg.h octeon_pkovar.h octeon_pow.c octeon_powreg.h
octeon_powvar.h octeon_rnm.c octeon_rnmreg.h octeon_smi.c
octeon_smireg.h octeon_smivar.h octeon_twsi.c octeon_twsireg.h
octeon_uart.c
Log Message:
General code cleanup:
- use generic macros for building IO and IOBDMA addresses instead
of many different variations of the same theme.
- use #define's for CVMSEG addresses instead of magic numbers.
- use __BIT/__BITS/__SHIFTIN/__SHIFTOUT in most places, instead of
foo_SHIFT defines or (worse) shifting by magic numbers.
No functional changes.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/cavium/octeonreg.h
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/mips/cavium/octeonvar.h
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/mips/cavium/dev/if_cnmac.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/cavium/dev/octeon_asxvar.h \
src/sys/arch/mips/cavium/dev/octeon_fau.c \
src/sys/arch/mips/cavium/dev/octeon_fauvar.h \
src/sys/arch/mips/cavium/dev/octeon_ipdvar.h \
src/sys/arch/mips/cavium/dev/octeon_pipvar.h \
src/sys/arch/mips/cavium/dev/octeon_pko.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/cavium/dev/octeon_cop2reg.h \
src/sys/arch/mips/cavium/dev/octeon_cop2var.h \
src/sys/arch/mips/cavium/dev/octeon_faureg.h \
src/sys/arch/mips/cavium/dev/octeon_fpareg.h \
src/sys/arch/mips/cavium/dev/octeon_gmxreg.h \
src/sys/arch/mips/cavium/dev/octeon_ipdreg.h \
src/sys/arch/mips/cavium/dev/octeon_l2creg.h \
src/sys/arch/mips/cavium/dev/octeon_mpireg.h \
src/sys/arch/mips/cavium/dev/octeon_pipreg.h \
src/sys/arch/mips/cavium/dev/octeon_pkoreg.h \
src/sys/arch/mips/cavium/dev/octeon_powreg.h \
src/sys/arch/mips/cavium/dev/octeon_smireg.h \
src/sys/arch/mips/cavium/dev/octeon_twsi.c \
src/sys/arch/mips/cavium/dev/octeon_twsireg.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/cavium/dev/octeon_fpa.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/cavium/dev/octeon_fpavar.h \
src/sys/arch/mips/cavium/dev/octeon_gmxvar.h \
src/sys/arch/mips/cavium/dev/octeon_pip.c \
src/sys/arch/mips/cavium/dev/octeon_powvar.h \
src/sys/arch/mips/cavium/dev/octeon_smivar.h
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/mips/cavium/dev/octeon_gmx.c \
src/sys/arch/mips/cavium/dev/octeon_rnm.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/cavium/dev/octeon_ipd.c \
src/sys/arch/mips/cavium/dev/octeon_pkovar.h \
src/sys/arch/mips/cavium/dev/octeon_rnmreg.h \
src/sys/arch/mips/cavium/dev/octeon_smi.c
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/cavium/dev/octeon_pow.c \
src/sys/arch/mips/cavium/dev/octeon_uart.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/cavium/octeonreg.h
diff -u src/sys/arch/mips/cavium/octeonreg.h:1.1 src/sys/arch/mips/cavium/octeonreg.h:1.2
--- src/sys/arch/mips/cavium/octeonreg.h:1.1 Mon Jun 15 07:48:12 2020
+++ src/sys/arch/mips/cavium/octeonreg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeonreg.h,v 1.1 2020/06/15 07:48:12 simonb Exp $ */
+/* $NetBSD: octeonreg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*-
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -35,6 +35,52 @@
#define OCTEON_PLL_REF_CLK 50000000 /* defined as 50MHz */
+/* ---- virtual addressing */
+
+/* CVMSEG virtual addresses */
+#define OCTEON_CVMSEG_LM UINT64_C(0xffffffffffff8000)
+#define OCTEON_CVMSEG_IO UINT64_C(0xffffffffffffa000)
+
+#define OCTEON_IOBDMA_GLOBAL_ADDR UINT64_C(0xffffffffffffa200)
+#define OCTEON_IOBDMA_LOCAL_ADDR UINT64_C(0xffffffffffffb200)
+#define OCTEON_LMTDMA_GLOBAL_ADDR UINT64_C(0xffffffffffffa400)
+#define OCTEON_LMTDMA_LOCAL_ADDR UINT64_C(0xffffffffffffb400)
+/* use globally ordered by default */
+#define OCTEON_IOBDMA_ADDR OCTEON_IOBDMA_GLOBAL_ADDR
+#define OCTEON_LMTDMA_ADDR OCTEON_LMTDMA_GLOBAL_ADDR
+
+/* ---- physical addressing */
+
+/*
+ * Cavium Octeon has a 49 bit physical address space.
+ *
+ * Bit 48 == 0 defines a L2 or DRAM address
+ * Bit 48 == 1 defines an IO address
+ *
+ * For IO addresses:
+ * Bits 47-43: Major DID - directs request to correct hardware block
+ * Bits 42-40: Sub DID - directs request within the hardware block
+ * Bits 39-38: reserved - 0
+ * Bits 37-36: reserved - 0 (on Octeon and Octeon Plus)
+ * Bits 37-36: Node - selects node/chip (Octeon II)
+ * Bits 35- 0: IO bus device address with the DID
+ */
+#define OCTEON_ADDR_IO __BIT(48)
+#define OCTEON_ADDR_MAJOR_DID __BITS(47,43)
+#define OCTEON_ADDR_SUB_DID __BITS(42,40)
+#define OCTEON_ADDR_NODE __BITS(37,36)
+#define OCTEON_ADDR_OFFSET __BITS(35,0)
+
+#define OCTEON_ADDR_DID(major, sub) ( \
+ __SHIFTIN((major), OCTEON_ADDR_MAJOR_DID) | \
+ __SHIFTIN((sub), OCTEON_ADDR_SUB_DID))
+
+/* used to build addresses for load/store operations */
+#define OCTEON_ADDR_IO_DID(major, sub) \
+ (OCTEON_ADDR_IO | OCTEON_ADDR_DID((major), (sub)))
+
+
+/* ---- core specific registers */
/* OCTEON II */
#define MIO_RST_BOOT UINT64_C(0x1180000001600)
@@ -63,4 +109,23 @@
#define RST_COLD_DATA(n) (UINT64_C(0x11800060017c0) + (n) * 0x8)
+/* ---- IOBDMA */
+
+/* 4.7 IOBDMA Operations */
+#define IOBDMA_SCRADDR __BITS(63,56)
+#define IOBDMA_LEN __BITS(55,48)
+/* IOBDMA_MAJOR_DID same as OCTEON_MAJOR_DID */
+/* IOBDMA_SUB_DID same as OCTEON_SUB_DID */
+/* reserved 39:38 */
+#define IOBDMA_NODE __BITS(37,36) /* Octeon 3 only */
+#define IOBDMA_OFFSET __BITS(35,0)
+/* technically __BITS(2,0) are reserved as 0, address must be 64-bit aligned */
+
+#define IOBDMA_CREATE(major, sub, scr, len, offset) ( \
+ OCTEON_ADDR_DID((major), (sub)) | \
+ __SHIFTIN((scr), IOBDMA_SCRADDR) | \
+ __SHIFTIN((len), IOBDMA_LEN) | \
+ __SHIFTIN((offset), IOBDMA_OFFSET))
+
+
#endif /* !_OCTEONREG_H_ */
Index: src/sys/arch/mips/cavium/octeonvar.h
diff -u src/sys/arch/mips/cavium/octeonvar.h:1.10 src/sys/arch/mips/cavium/octeonvar.h:1.11
--- src/sys/arch/mips/cavium/octeonvar.h:1.10 Mon Jun 15 07:48:12 2020
+++ src/sys/arch/mips/cavium/octeonvar.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeonvar.h,v 1.10 2020/06/15 07:48:12 simonb Exp $ */
+/* $NetBSD: octeonvar.h,v 1.11 2020/06/18 13:52:08 simonb Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -38,6 +38,8 @@
#include <mips/locore.h>
#include <dev/pci/pcivar.h>
+#include <mips/cavium/octeonreg.h>
+
/* XXX elsewhere */
#define _ASM_PROLOGUE \
" .set push \n" \
@@ -338,21 +340,20 @@ octeon_xkphys_write_8(paddr_t address, u
static __inline void
octeon_iobdma_write_8(uint64_t value)
{
- uint64_t addr = UINT64_C(0xffffffffffffa200);
- octeon_xkphys_write_8(addr, value);
+ octeon_xkphys_write_8(OCTEON_IOBDMA_ADDR, value);
}
static __inline uint64_t
octeon_cvmseg_read_8(size_t offset)
{
- return octeon_xkphys_read_8(UINT64_C(0xffffffffffff8000) + offset);
+ return octeon_xkphys_read_8(OCTEON_CVMSEG_LM + offset);
}
static __inline void
octeon_cvmseg_write_8(size_t offset, uint64_t value)
{
- octeon_xkphys_write_8(UINT64_C(0xffffffffffff8000) + offset, value);
+ octeon_xkphys_write_8(OCTEON_CVMSEG_LM + offset, value);
}
/* XXX */
Index: src/sys/arch/mips/cavium/dev/if_cnmac.c
diff -u src/sys/arch/mips/cavium/dev/if_cnmac.c:1.21 src/sys/arch/mips/cavium/dev/if_cnmac.c:1.22
--- src/sys/arch/mips/cavium/dev/if_cnmac.c:1.21 Wed Jun 10 07:34:19 2020
+++ src/sys/arch/mips/cavium/dev/if_cnmac.c Thu Jun 18 13:52:08 2020
@@ -1,8 +1,8 @@
-/* $NetBSD: if_cnmac.c,v 1.21 2020/06/10 07:34:19 simonb Exp $ */
+/* $NetBSD: if_cnmac.c,v 1.22 2020/06/18 13:52:08 simonb Exp $ */
#include <sys/cdefs.h>
#if 0
-__KERNEL_RCSID(0, "$NetBSD: if_cnmac.c,v 1.21 2020/06/10 07:34:19 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_cnmac.c,v 1.22 2020/06/18 13:52:08 simonb Exp $");
#endif
#include "opt_octeon.h"
@@ -63,18 +63,15 @@ __KERNEL_RCSID(0, "$NetBSD: if_cnmac.c,v
#include <mips/cpuregs.h>
-#include <mips/cavium/dev/octeon_asxreg.h>
+#include <mips/cavium/octeonreg.h>
+#include <mips/cavium/include/iobusvar.h>
+
#include <mips/cavium/dev/octeon_ciureg.h>
-#include <mips/cavium/dev/octeon_npireg.h>
#include <mips/cavium/dev/octeon_gmxreg.h>
-#include <mips/cavium/dev/octeon_ipdreg.h>
#include <mips/cavium/dev/octeon_pipreg.h>
#include <mips/cavium/dev/octeon_powreg.h>
#include <mips/cavium/dev/octeon_faureg.h>
#include <mips/cavium/dev/octeon_fpareg.h>
-#include <mips/cavium/dev/octeon_bootbusreg.h>
-#include <mips/cavium/include/iobusvar.h>
-#include <mips/cavium/octeonvar.h>
#include <mips/cavium/dev/octeon_fpavar.h>
#include <mips/cavium/dev/octeon_gmxvar.h>
#include <mips/cavium/dev/octeon_fauvar.h>
Index: src/sys/arch/mips/cavium/dev/octeon_asxvar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_asxvar.h:1.2 src/sys/arch/mips/cavium/dev/octeon_asxvar.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_asxvar.h:1.2 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_asxvar.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_asxvar.h,v 1.2 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_asxvar.h,v 1.3 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -53,4 +53,4 @@ int octasx_enable(struct octasx_softc
int octasx_clk_set(struct octasx_softc *, int, int);
uint64_t octasx_int_summary(struct octasx_softc *sc);
-#endif
+#endif /* _OCTEON_ASXVAR_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_fau.c
diff -u src/sys/arch/mips/cavium/dev/octeon_fau.c:1.2 src/sys/arch/mips/cavium/dev/octeon_fau.c:1.3
--- src/sys/arch/mips/cavium/dev/octeon_fau.c:1.2 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_fau.c Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_fau.c,v 1.2 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_fau.c,v 1.3 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_fau.c,v 1.2 2020/05/31 06:27:06 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_fau.c,v 1.3 2020/06/18 13:52:08 simonb Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -49,26 +49,18 @@ static inline void octfau_op_store_paddr
static inline int64_t
octfau_op_load(uint64_t args)
{
- paddr_t addr;
+ paddr_t addr = OCTEON_ADDR_IO_DID(FAU_MAJOR_DID, FAU_SUB_DID) |
+ __SHIFTIN(args, OCTEON_ADDR_OFFSET);
- addr =
- ((uint64_t)1 << 48) |
- ((uint64_t)(CN30XXFAU_MAJORDID & 0x1f) << 43) |
- ((uint64_t)(CN30XXFAU_SUBDID & 0x7) << 40) |
- ((uint64_t)(args & 0xfffffffffULL) << 0);
return octeon_read_csr(addr);
}
static inline void
octfau_op_store(uint64_t args, int64_t value)
{
- paddr_t addr;
+ paddr_t addr = OCTEON_ADDR_IO_DID(FAU_MAJOR_DID, FAU_SUB_DID) |
+ __SHIFTIN(args, OCTEON_ADDR_OFFSET);
- addr =
- ((uint64_t)1 << 48) |
- ((uint64_t)(CN30XXFAU_MAJORDID & 0x1f) << 43) |
- ((uint64_t)(CN30XXFAU_SUBDID & 0x7) << 40) |
- ((uint64_t)(args & 0xfffffffffULL) << 0);
octeon_write_csr(addr, value);
}
@@ -85,12 +77,11 @@ octfau_op_store(uint64_t args, int64_t v
static inline int64_t
octfau_op_load_paddr(int incval, int tagwait, int reg)
{
- uint64_t args;
+ uint64_t args =
+ __SHIFTIN(incval, POW_LOAD_INCVAL) |
+ __SHIFTIN(tagwait, POW_LOAD_TAGWAIT) |
+ __SHIFTIN(reg, POW_LOAD_REG);
- args =
- ((uint64_t)(incval & 0x3fffff) << 14) |
- ((uint64_t)(tagwait & 0x1) << 13) |
- ((uint64_t)(reg & 0x7ff) << 0);
return octfau_op_load(args);
}
@@ -101,11 +92,8 @@ octfau_op_load_paddr(int incval, int tag
static inline void
octfau_op_store_paddr(int noadd, int reg, int64_t value)
{
- uint64_t args;
+ uint64_t args = POW_STORE_NOADD | __SHIFTIN(reg, POW_STORE_REG);
- args =
- ((uint64_t)(noadd & 0x1) << 13) |
- ((uint64_t)(reg & 0x7ff) << 0);
octfau_op_store(args, value);
}
@@ -114,6 +102,7 @@ octfau_op_store_paddr(int noadd, int reg
void
octfau_op_init(struct octfau_desc *fd, size_t scroff, size_t regno)
{
+
fd->fd_scroff = scroff;
fd->fd_regno = regno;
}
@@ -121,6 +110,7 @@ octfau_op_init(struct octfau_desc *fd, s
uint64_t
octfau_op_save(struct octfau_desc *fd)
{
+
OCTEON_SYNCIOBDMA/* XXX */;
return octeon_cvmseg_read_8(fd->fd_scroff);
}
@@ -128,12 +118,14 @@ octfau_op_save(struct octfau_desc *fd)
void
octfau_op_restore(struct octfau_desc *fd, uint64_t backup)
{
+
octeon_cvmseg_write_8(fd->fd_scroff, backup);
}
int64_t
octfau_op_inc_8(struct octfau_desc *fd, int64_t v)
{
+
octfau_op_iobdma_store_data(fd->fd_scroff, v, 0, OCT_FAU_OP_SIZE_64/* XXX */,
fd->fd_regno);
OCTEON_SYNCIOBDMA/* XXX */;
@@ -143,6 +135,7 @@ octfau_op_inc_8(struct octfau_desc *fd,
int64_t
octfau_op_incwait_8(struct octfau_desc *fd, int v)
{
+
octfau_op_iobdma_store_data(fd->fd_scroff, v, 1, OCT_FAU_OP_SIZE_64/* XXX */,
fd->fd_regno);
/* XXX */
@@ -154,11 +147,13 @@ octfau_op_incwait_8(struct octfau_desc *
void
octfau_op_add_8(struct octfau_desc *fd, int64_t v)
{
+
octfau_op_store_paddr(0, fd->fd_regno, v);
}
void
octfau_op_set_8(struct octfau_desc *fd, int64_t v)
{
+
octfau_op_store_paddr(1, fd->fd_regno, v);
}
Index: src/sys/arch/mips/cavium/dev/octeon_fauvar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_fauvar.h:1.2 src/sys/arch/mips/cavium/dev/octeon_fauvar.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_fauvar.h:1.2 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_fauvar.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_fauvar.h,v 1.2 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_fauvar.h,v 1.3 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -29,6 +29,8 @@
#ifndef _OCTEON_FAUVAR_H_
#define _OCTEON_FAUVAR_H_
+#include <mips/cavium/octeonreg.h>
+
/* ---- API */
struct octfau_desc {
@@ -89,14 +91,9 @@ typedef enum {
static inline void
octfau_op_iobdma(int index, uint64_t args)
{
- uint64_t value;
+ uint64_t value = IOBDMA_CREATE(FAU_MAJOR_DID, FAU_SUB_DID,
+ index, POW_IOBDMA_LEN, args);
- value =
- ((uint64_t)(index & 0xff) << 56) |
- ((uint64_t)1 << 48) |
- ((uint64_t)(CN30XXFAU_MAJORDID & 0x1f) << 43) |
- ((uint64_t)(CN30XXFAU_SUBDID & 0x7) << 40) |
- ((uint64_t)args & 0xfffffffffULL);
octeon_iobdma_write_8(value);
}
@@ -108,24 +105,21 @@ static inline void
octfau_op_iobdma_store_data(int scraddr, int incval, int tagwait,
int size, int reg)
{
- uint64_t args;
+ uint64_t args =
+ __SHIFTIN(incval, POW_IOBDMA_INCVAL) |
+ __SHIFTIN(tagwait, POW_IOBDMA_TAGWAIT) |
+ __SHIFTIN(size, POW_IOBDMA_SIZE) |
+ __SHIFTIN(reg, POW_IOBDMA_REG);
- args =
- ((uint64_t)(incval & 0x3fffff) << 14) |
- ((uint64_t)(tagwait & 0x1) << 13) |
- ((uint64_t)(size & 0x3) << 11) |
- ((uint64_t)(reg & 0x7ff) << 0);
- /*
- * `scraddr' parameter of IOBDMA operation is actually `index';
- */
- octfau_op_iobdma((int)((uint32_t)scraddr >> 3) /* XXX */, args);
+ /* `scraddr' parameter of IOBDMA operation is actually `index' */
+ octfau_op_iobdma(scraddr / sizeof(uint64_t), args);
}
static inline void
octfau_op_inc_fetch_8(struct octfau_desc *fd, int64_t v)
{
- octfau_op_iobdma_store_data(fd->fd_scroff, v, 0, OCT_FAU_OP_SIZE_64/* XXX */,
- fd->fd_regno);
+ octfau_op_iobdma_store_data(fd->fd_scroff, v, 0,
+ OCT_FAU_OP_SIZE_64/* XXX */, fd->fd_regno);
}
static inline int64_t
Index: src/sys/arch/mips/cavium/dev/octeon_ipdvar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_ipdvar.h:1.2 src/sys/arch/mips/cavium/dev/octeon_ipdvar.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_ipdvar.h:1.2 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_ipdvar.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_ipdvar.h,v 1.2 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_ipdvar.h,v 1.3 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -69,4 +69,4 @@ uint64_t octipd_int_summary(struct octi
void octipd_int_enable(struct octipd_softc *, int);
#endif /* CNMAC_DEBUG */
-#endif
+#endif /* _OCTEON_IPDVAR_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_pipvar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_pipvar.h:1.2 src/sys/arch/mips/cavium/dev/octeon_pipvar.h:1.3
--- src/sys/arch/mips/cavium/dev/octeon_pipvar.h:1.2 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pipvar.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pipvar.h,v 1.2 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_pipvar.h,v 1.3 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -75,5 +75,4 @@ void octpip_int_enable(struct octpip_so
uint64_t octpip_int_summary(struct octpip_softc *);
#endif /* CNMAC_DEBUG */
-
-#endif
+#endif /* _OCTEON_PIPVAR_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_pko.c
diff -u src/sys/arch/mips/cavium/dev/octeon_pko.c:1.2 src/sys/arch/mips/cavium/dev/octeon_pko.c:1.3
--- src/sys/arch/mips/cavium/dev/octeon_pko.c:1.2 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pko.c Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pko.c,v 1.2 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_pko.c,v 1.3 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_pko.c,v 1.2 2020/05/31 06:27:06 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_pko.c,v 1.3 2020/06/18 13:52:08 simonb Exp $");
#include "opt_octeon.h"
@@ -37,12 +37,11 @@ __KERNEL_RCSID(0, "$NetBSD: octeon_pko.c
#include <mips/locore.h>
#include <mips/cavium/octeonvar.h>
#include <mips/cavium/dev/octeon_faureg.h>
+#include <mips/cavium/dev/octeon_fpareg.h>
#include <mips/cavium/dev/octeon_fpavar.h>
#include <mips/cavium/dev/octeon_pkoreg.h>
#include <mips/cavium/dev/octeon_pkovar.h>
-static inline void octpko_op_store(uint64_t, uint64_t);
-
#ifdef CNMAC_DEBUG
void octpko_intr_evcnt_attach(struct octpko_softc *);
void octpko_intr_rml(void *);
Index: src/sys/arch/mips/cavium/dev/octeon_cop2reg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_cop2reg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_cop2reg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_cop2reg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_cop2reg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_cop2reg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_cop2reg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2008 Internet Initiative Japan, Inc.
@@ -33,8 +33,8 @@
* DMFC2 / DMTC2 instructions
*/
-#ifndef _CN30XXCOP2REG_H_
-#define _CN30XXCOP2REG_H_
+#ifndef _OCTEON_COP2REG_H_
+#define _OCTEON_COP2REG_H_
/* 3DES */
@@ -125,4 +125,4 @@
#define CVM_MT_KAS_KEY 0x0080 /* Load Key into KASUMI Unit */
#define CVM_MT_KAS_RESULT 0x0098 /* Load Result into KASUMI Unit */
-#endif /* _CN30XXCOP2REG_H_ */
+#endif /* _OCTEON_COP2REG_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_cop2var.h
diff -u src/sys/arch/mips/cavium/dev/octeon_cop2var.h:1.1 src/sys/arch/mips/cavium/dev/octeon_cop2var.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_cop2var.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_cop2var.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_cop2var.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_cop2var.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* TODO:
@@ -12,8 +12,8 @@
* direction argument (int dir, 0 => encrypt, 1 => decrypt) then branch.
*/
-#ifndef _CN30XXCOP2VAR_H_
-#define _CN30XXCOP2VAR_H_
+#ifndef _OCTEON_COP2VAR_H_
+#define _OCTEON_COP2VAR_H_
#ifdef __OCTEON_USEUN__
#define CNASM_ULD(r, o, b) "uld %["#r"], "#o"(%["#b"]) \n\t"
@@ -1035,4 +1035,4 @@ octeon_cop2_crc_reflect(XXX)
/* XXX */
-#endif /* _CN30XXCOP2VAR_H_ */
+#endif /* _OCTEON_COP2VAR_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_faureg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_faureg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_faureg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_faureg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_faureg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_faureg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_faureg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -33,9 +33,30 @@
#ifndef _OCTEON_FAUREG_H_
#define _OCTEON_FAUREG_H_
+
+#define FAU_MAJOR_DID 0x1e
+#define FAU_SUB_DID 0
+
/* ---- operations */
-#define CN30XXFAU_MAJORDID 0x1e
-#define CN30XXFAU_SUBDID 0
+/* -- load operations */
+#define POW_LOAD_INCVAL __BITS(35,14)
+#define POW_LOAD_TAGWAIT __BIT(13)
+/* reserved __BiTS(12,11) */
+#define POW_LOAD_REG __BITS(10,0)
+
+/* -- iobdma store operations */
+
+#define POW_IOBDMA_LEN 1 /* always 1 for POW */
+#define POW_IOBDMA_INCVAL POW_LOAD_INCVAL
+#define POW_IOBDMA_TAGWAIT POW_LOAD_TAGWAIT
+#define POW_IOBDMA_SIZE __BITS(12,11)
+#define POW_IOBDMA_REG POW_LOAD_REG
+
+/* -- store operations */
+/* reserved __BiTS(35,14) */
+#define POW_STORE_NOADD __BIT(13)
+/* reserved __BiTS(12,11) */
+#define POW_STORE_REG __BITS(10,0)
#endif /* _OCTEON_FAUREG_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_fpareg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_fpareg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_fpareg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_fpareg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_fpareg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_fpareg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_fpareg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -308,38 +308,11 @@
* Free Pool Unit Operations
*/
-#define FPA_MAJORDID 0x5 /* 0b00101 */
-
-#define FPA_OPS_MAJORDID UINT64_C(0x0000f80000000000)
-#define FPA_OPS_MAJORDID_SHIFT 43
-#define FPA_OPS_SUBDID UINT64_C(0x0000070000000000)
-#define FPA_OPS_SUBDID_SHIFT 40
-#define FPA_OPS_XXX_39_0 UINT64_C(0x000000ffffffffff)
-
-/* Load Operations */
-
-#define FPA_OPS_LOAD_1 UINT64_C(0x0001000000000000)
-#define FPA_OPS_LOAD_MAJORDID UINT64_C(0x0000f80000000000)
-#define FPA_OPS_LOAD_SUBDID UINT64_C(0x0000070000000000)
-#define FPA_OPS_LOAD_XXX_39_0 UINT64_C(0x000000ffffffffff)
-
-/* IOBDMA Operations */
-
-#define FPA_OPS_IOBDMA_SRCADDR UINT64_C(0xff00000000000000)
-#define FPA_OPS_IOBDMA_LEN UINT64_C(0x00ff000000000000)
-#define FPA_OPS_IOBDMA_LEN_SHIFT 48
-#define FPA_OPS_IOBDMA_MAJORDID UINT64_C(0x0000f80000000000)
-#define FPA_OPS_IOBDMA_SUBDIR UINT64_C(0x0000070000000000)
-#define FPA_OPS_IOBDMA_XXX_39_0 UINT64_C(0x000000ffffffffff)
+#define FPA_MAJOR_DID 0x5
/* Store Operations */
+#define FPA_OPS_STORE_ADDR UINT64_C(0x000000ffffffffff)
-#define FPA_OPS_STORE_1 UINT64_C(0x0001000000000000)
-#define FPA_OPS_STORE_MAJORDID UINT64_C(0x0000f80000000000)
-#define FPA_OPS_STORE_SUBDID UINT64_C(0x0000070000000000)
-#define FPA_OPS_STORE_XXX_39_0 UINT64_C(0x000000ffffffffff)
-
-#define FPA_OPS_STORE_DATA_XXX_63_9 UINT64_C(0xfffffffffffffe00)
#define FPA_OPS_STORE_DATA_DWBCOUNT UINT64_C(0x00000000000001ff)
/* ---- bus_space(9) */
Index: src/sys/arch/mips/cavium/dev/octeon_gmxreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_gmxreg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_gmxreg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_gmxreg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_gmxreg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_gmxreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_gmxreg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -245,15 +245,13 @@
#define RXN_RX_INBND_XXX_63_4 UINT64_C(0xfffffffffffffff0)
#define RXN_RX_INBND_DUPLEX UINT64_C(0x0000000000000008)
-#define RXN_RX_INBND_DUPLEX_SHIFT 3
-#define RXN_RX_INBND_DUPLEX_HALF (0ULL << RXN_RX_INBND_DUPLEX_SHIFT)
-#define RXN_RX_INBND_DUPLEX_FULL (1ULL << RXN_RX_INBND_DUPLEX_SHIFT)
+#define RXN_RX_INBND_DUPLEX_HALF 0
+#define RXN_RX_INBND_DUPLEX_FULL 1
#define RXN_RX_INBND_SPEED UINT64_C(0x0000000000000006)
-#define RXN_RX_INBND_SPEED_SHIFT 1
-#define RXN_RX_INBND_SPEED_2_5 (0ULL << RXN_RX_INBND_SPEED_SHIFT)
-#define RXN_RX_INBND_SPEED_25 (1ULL << RXN_RX_INBND_SPEED_SHIFT)
-#define RXN_RX_INBND_SPEED_125 (2ULL << RXN_RX_INBND_SPEED_SHIFT)
-#define RXN_RX_INBND_SPEED_XXX_3 (3ULL << RXN_RX_INBND_SPEED_SHIFT)
+#define RXN_RX_INBND_SPEED_2_5 0
+#define RXN_RX_INBND_SPEED_25 1
+#define RXN_RX_INBND_SPEED_125 2
+#define RXN_RX_INBND_SPEED_XXX_3 3
#define RXN_RX_INBND_STATUS UINT64_C(0x0000000000000001)
/* GMX RX Good Packets Registers */
@@ -305,15 +303,13 @@
#define RXN_ADR_CTL_XXX_63_4 UINT64_C(0xfffffffffffffff0)
#define RXN_ADR_CTL_CAM_MODE UINT64_C(0x0000000000000008)
-#define RXN_ADR_CTL_CAM_MODE_SHIFT 3
-#define RXN_ADR_CTL_CAM_MODE_REJECT (0ULL << RXN_ADR_CTL_CAM_MODE_SHIFT)
-#define RXN_ADR_CTL_CAM_MODE_ACCEPT (1ULL << RXN_ADR_CTL_CAM_MODE_SHIFT)
+#define RXN_ADR_CTL_CAM_MODE_REJECT 0
+#define RXN_ADR_CTL_CAM_MODE_ACCEPT 1
#define RXN_ADR_CTL_MCST UINT64_C(0x0000000000000006)
-#define RXN_ADR_CTL_MCST_SHIFT 1
-#define RXN_ADR_CTL_MCST_AFCAM (0ULL << RXN_ADR_CTL_MCST_SHIFT)
-#define RXN_ADR_CTL_MCST_REJECT (1ULL << RXN_ADR_CTL_MCST_SHIFT)
-#define RXN_ADR_CTL_MCST_ACCEPT (2ULL << RXN_ADR_CTL_MCST_SHIFT)
-#define RXN_ADR_CTL_MCST_XXX_3 (3ULL << RXN_ADR_CTL_MCST_SHIFT)
+#define RXN_ADR_CTL_MCST_AFCAM 0
+#define RXN_ADR_CTL_MCST_REJECT 1
+#define RXN_ADR_CTL_MCST_ACCEPT 2
+#define RXN_ADR_CTL_MCST_XXX_3 3
#define RXN_ADR_CTL_BCST UINT64_C(0x0000000000000001)
/* Address-Filtering Control Enable Registers */
@@ -509,13 +505,10 @@
#define TX_OVR_BP_XXX_63_12 UINT64_C(0xfffffffffffff000)
#define TX_OVR_BP_XXX_11 UINT64_C(0x0000000000000800)
#define TX_OVR_BP_EN UINT64_C(0x0000000000000700)
-#define TX_OVR_BP_EN_SHIFT 8
#define TX_OVR_BP_XXX_7 UINT64_C(0x0000000000000080)
#define TX_OVR_BP_BP UINT64_C(0x0000000000000070)
-#define TX_OVR_BP_BP_SHIFT 4
#define TX_OVR_BP_XXX_3 UINT64_C(0x0000000000000008)
#define TX_OVR_BP_IGN_FULL UINT64_C(0x0000000000000007)
-#define TX_OVR_BP_IGN_FULL_SHIFT 0
/* TX Override Backpressure Register */
Index: src/sys/arch/mips/cavium/dev/octeon_ipdreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_ipdreg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_ipdreg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_ipdreg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_ipdreg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_ipdreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_ipdreg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -222,11 +222,10 @@
#define IPD_CTL_STATUS_WQE_LEND UINT64_C(0x0000000000000010)
#define IPD_CTL_STATUS_PBP_EN UINT64_C(0x0000000000000008)
#define IPD_CTL_STATUS_OPC_MODE UINT64_C(0x0000000000000006)
-#define IPD_CTL_STATUS_OPC_MODE_SHIFT 1
-#define IPD_CTL_STATUS_OPC_MODE_NONE (0ULL << IPD_CTL_STATUS_OPC_MODE_SHIFT)
-#define IPD_CTL_STATUS_OPC_MODE_ALL (1ULL << IPD_CTL_STATUS_OPC_MODE_SHIFT)
-#define IPD_CTL_STATUS_OPC_MODE_ONE (2ULL << IPD_CTL_STATUS_OPC_MODE_SHIFT)
-#define IPD_CTL_STATUS_OPC_MODE_TWO (3ULL << IPD_CTL_STATUS_OPC_MODE_SHIFT)
+#define IPD_CTL_STATUS_OPC_MODE_NONE 0
+#define IPD_CTL_STATUS_OPC_MODE_ALL 1
+#define IPD_CTL_STATUS_OPC_MODE_ONE 2
+#define IPD_CTL_STATUS_OPC_MODE_TWO 3
#define IPD_CTL_STATUS_IPD_EN UINT64_C(0x0000000000000001)
/*
Index: src/sys/arch/mips/cavium/dev/octeon_l2creg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_l2creg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_l2creg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_l2creg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_l2creg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_l2creg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_l2creg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -30,8 +30,8 @@
* L2C Registers
*/
-#ifndef _CN30XXL2CREG_H_
-#define _CN30XXL2CREG_H_
+#ifndef _OCTEON_L2CREG_H_
+#define _OCTEON_L2CREG_H_
#define L2C_CFG 0x0001180080000000ULL
#define L2T_ERR 0x0001180080000008ULL
@@ -66,4 +66,4 @@
#define L2C_BST1 0x00011800800007f0ULL
#define L2C_BST0 0x00011800800007f8ULL
-#endif /* _CN30XXL2CREG_H_ */
+#endif /* _OCTEON_L2CREG_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_mpireg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_mpireg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_mpireg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_mpireg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_mpireg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_mpireg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_mpireg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -48,7 +48,6 @@
#define MPI_CFG_XXX_63_29 UINT64_C(0xffffffffe0000000)
#define MPI_CFG_CLKDIV UINT64_C(0x000000001fff0000)
-#define MPI_CFG_CLKDIV_SHIFT 16
#define MPI_CFG_XXX_15_12 UINT64_C(0x000000000000f000)
#define MPI_CFG_CSLATE UINT64_C(0x0000000000000800)
#define MPI_CFG_TRITX UINT64_C(0x0000000000000400)
@@ -71,10 +70,8 @@
#define MPI_TX_LEAVECS UINT64_C(0x0000000000010000)
#define MPI_TX_XXX_15_13 UINT64_C(0x000000000000e000)
#define MPI_TX_TXNUM UINT64_C(0x0000000000001f00)
-#define MPI_TX_TXNUM_SHIFT 8
#define MPI_TX_XXX_7_5 UINT64_C(0x00000000000000e0)
#define MPI_TX_TOTNUM UINT64_C(0x000000000000001f)
-#define MPI_TX_TOTNUM_SHIFT 0
#define MPI_DATX_XXX_63_8 UINT64_C(0xffffffffffffff00)
#define MPI_DATX_DATA UINT64_C(0x00000000000000ff)
Index: src/sys/arch/mips/cavium/dev/octeon_pipreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_pipreg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_pipreg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_pipreg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_pipreg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pipreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_pipreg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -363,11 +363,10 @@
#define PIP_PRT_CFGN_CRC_EN UINT64_C(0x0000000000001000)
#define PIP_PRT_CFGN_11_10 UINT64_C(0x0000000000000c00)
#define PIP_PRT_CFGN_MODE UINT64_C(0x0000000000000300)
-#define PIP_PRT_CFGN_MODE_SHIFT 8
-#define PIP_PORT_CFG_MODE_NONE (0ULL << PIP_PRT_CFGN_MODE_SHIFT)
-#define PIP_PORT_CFG_MODE_L2 (1ULL << PIP_PRT_CFGN_MODE_SHIFT)
-#define PIP_PORT_CFG_MODE_IP (2ULL << PIP_PRT_CFGN_MODE_SHIFT)
-#define PIP_PORT_CFG_MODE_PCI (3ULL << PIP_PRT_CFGN_MODE_SHIFT)
+#define PIP_PORT_CFG_MODE_NONE 0
+#define PIP_PORT_CFG_MODE_L2 1
+#define PIP_PORT_CFG_MODE_IP 2
+#define PIP_PORT_CFG_MODE_PCI 3
#define PIP_PRT_CFGN_7 UINT64_C(0x0000000000000080)
#define PIP_PRT_CFGN_SKIP UINT64_C(0x000000000000007f)
@@ -394,35 +393,30 @@
#define PIP_PRT_TAGN_IP6_SRC UINT64_C(0x0000000000008000)
#define PIP_PRT_TAGN_IP4_DST UINT64_C(0x0000000000004000)
#define PIP_PRT_TAGN_TCP6_TAG UINT64_C(0x0000000000003000)
-#define PIP_PRT_TAGN_TCP6_TAG_SHIFT 12
-#define PIP_PRT_TAGN_TCP6_TAG_ORDERED (0ULL << PIP_PRT_TAGN_TCP6_TAG_SHIFT)
-#define PIP_PRT_TAGN_TCP6_TAG_ATOMIC (1ULL << PIP_PRT_TAGN_TCP6_TAG_SHIFT)
-#define PIP_PRT_TAGN_TCP6_TAG_NULL (2ULL << PIP_PRT_TAGN_TCP6_TAG_SHIFT)
-#define PIP_PRT_TAGN_TCP6_TAG_XXX_3 (3ULL << PIP_PRT_TAGN_TCP6_TAG_SHIFT)
+#define PIP_PRT_TAGN_TCP6_TAG_ORDERED 0
+#define PIP_PRT_TAGN_TCP6_TAG_ATOMIC 1
+#define PIP_PRT_TAGN_TCP6_TAG_NULL 2
+#define PIP_PRT_TAGN_TCP6_TAG_XXX_3 3
#define PIP_PRT_TAGN_TCP4_TAG UINT64_C(0x0000000000000c00)
-#define PIP_PRT_TAGN_TCP4_TAG_SHIFT 10
-#define PIP_PRT_TAGN_TCP4_TAG_ORDERED (0ULL << PIP_PRT_TAGN_TCP4_TAG_SHIFT)
-#define PIP_PRT_TAGN_TCP4_TAG_ATOMIC (1ULL << PIP_PRT_TAGN_TCP4_TAG_SHIFT)
-#define PIP_PRT_TAGN_TCP4_TAG_NULL (2ULL << PIP_PRT_TAGN_TCP4_TAG_SHIFT)
-#define PIP_PRT_TAGN_TCP4_TAG_XXX_3 (3ULL << PIP_PRT_TAGN_TCP4_TAG_SHIFT)
+#define PIP_PRT_TAGN_TCP4_TAG_ORDERED 0
+#define PIP_PRT_TAGN_TCP4_TAG_ATOMIC 1
+#define PIP_PRT_TAGN_TCP4_TAG_NULL 2
+#define PIP_PRT_TAGN_TCP4_TAG_XXX_3 3
#define PIP_PRT_TAGN_IP6_TAG UINT64_C(0x0000000000000300)
-#define PIP_PRT_TAGN_IP6_TAG_SHIFT 8
-#define PIP_PRT_TAGN_IP6_TAG_ORDERED (0ULL << PIP_PRT_TAGN_IP6_TAG_SHIFT)
-#define PIP_PRT_TAGN_IP6_TAG_ATOMIC (1ULL << PIP_PRT_TAGN_IP6_TAG_SHIFT)
-#define PIP_PRT_TAGN_IP6_TAG_NULL (2ULL << PIP_PRT_TAGN_IP6_TAG_SHIFT)
-#define PIP_PRT_TAGN_IP6_TAG_XXX_3 (3ULL << PIP_PRT_TAGN_IP6_TAG_SHIFT)
+#define PIP_PRT_TAGN_IP6_TAG_ORDERED 0
+#define PIP_PRT_TAGN_IP6_TAG_ATOMIC 1
+#define PIP_PRT_TAGN_IP6_TAG_NULL 2
+#define PIP_PRT_TAGN_IP6_TAG_XXX_3 3
#define PIP_PRT_TAGN_IP4_TAG UINT64_C(0x00000000000000c0)
-#define PIP_PRT_TAGN_IP4_TAG_SHIFT 6
-#define PIP_PRT_TAGN_IP4_TAG_ORDERED (0ULL << PIP_PRT_TAGN_IP4_TAG_SHIFT)
-#define PIP_PRT_TAGN_IP4_TAG_ATOMIC (1ULL << PIP_PRT_TAGN_IP4_TAG_SHIFT)
-#define PIP_PRT_TAGN_IP4_TAG_NULL (2ULL << PIP_PRT_TAGN_IP4_TAG_SHIFT)
-#define PIP_PRT_TAGN_IP4_TAG_XXX_3 (3ULL << PIP_PRT_TAGN_IP4_TAG_SHIFT)
+#define PIP_PRT_TAGN_IP4_TAG_ORDERED 0
+#define PIP_PRT_TAGN_IP4_TAG_ATOMIC 1
+#define PIP_PRT_TAGN_IP4_TAG_NULL 2
+#define PIP_PRT_TAGN_IP4_TAG_XXX_3 3
#define PIP_PRT_TAGN_NON_TAG UINT64_C(0x0000000000000030)
-#define PIP_PRT_TAGN_NON_TAG_SHIFT 4
-#define PIP_PRT_TAGN_NON_TAG_ORDERED (0ULL << PIP_PRT_TAGN_NON_TAG_SHIFT)
-#define PIP_PRT_TAGN_NON_TAG_ATOMIC (1ULL << PIP_PRT_TAGN_NON_TAG_SHIFT)
-#define PIP_PRT_TAGN_NON_TAG_NULL (2ULL << PIP_PRT_TAGN_NON_TAG_SHIFT)
-#define PIP_PRT_TAGN_NON_TAG_XXX_3 (3ULL << PIP_PRT_TAGN_NON_TAG_SHIFT)
+#define PIP_PRT_TAGN_NON_TAG_ORDERED 0
+#define PIP_PRT_TAGN_NON_TAG_ATOMIC 1
+#define PIP_PRT_TAGN_NON_TAG_NULL 2
+#define PIP_PRT_TAGN_NON_TAG_XXX_3 3
#define PIP_PRT_TAGN_GRP UINT64_C(0x000000000000000f)
/*
@@ -537,7 +531,6 @@
#define PIP_WQE_WORD2_IP_BUFS UINT64_C(0xff00000000000000)
#define PIP_WQE_WORD2_IP_OFFSET UINT64_C(0x00ff000000000000)
-#define PIP_WQE_WORD2_IP_OFFSET_SHIFT 48
#define PIP_WQE_WORD2_IP_VV UINT64_C(0x0000800000000000)
#define PIP_WQE_WORD2_IP_VS UINT64_C(0x0000400000000000)
#define PIP_WQE_WORD2_IP_45 UINT64_C(0x0000200000000000)
Index: src/sys/arch/mips/cavium/dev/octeon_pkoreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_pkoreg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_pkoreg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_pkoreg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_pkoreg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pkoreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_pkoreg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -33,6 +33,12 @@
#ifndef _OCTEON_PKOREG_H_
#define _OCTEON_PKOREG_H_
+/* ---- operations */
+
+#define PKO_MAJOR_DID 0x0a
+#define PKO_SUB_DID 0x02
+
+
#define PKO_REG_FLAGS 0x0001180050000000ULL
#define PKO_REG_READ_IDX 0x0001180050000008ULL
#define PKO_REG_CMD_BUF 0x0001180050000010ULL
@@ -378,19 +384,9 @@
/*
* DOORBELL_WRITE
*/
-#define PKO_DOORBELL_WRITE_IO_BIT UINT64_C(0x0001000000000000)
-#define PKO_DOORBELL_WRITE_MAJOR_DID UINT64_C(0x0000f80000000000)
-#define PKO_DOORBELL_WRITE_SUB_DID UINT64_C(0x0000070000000000)
-#define PKO_DOORBELL_WRITE_39_16 UINT64_C(0x000000ffffff0000)
#define PKO_DOORBELL_WRITE_PID UINT64_C(0x000000000003f000)
#define PKO_DOORBELL_WRITE_QID UINT64_C(0x0000000000000ff8)
-#define PKO_DOORBELL_WRITE_2_0 UINT64_C(0x0000000000000007)
#define PKO_DOORBELL_WRITE_WDC UINT64_C(0x00000000000fffff)
-/* ---- operations */
-
-#define CN30XXPKO_MAJORDID 0x0a
-#define CN30XXPKO_SUBDID 0x02
-
#endif /* _OCTEON_PKOREG_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_powreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_powreg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_powreg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_powreg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_powreg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_powreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_powreg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -228,98 +228,74 @@
#define POW_PP_GRP_MSKX_XXX_63_16 UINT64_C(0xffffffffffff0000)
#define POW_PP_GRP_MSKX_GRP_MSK UINT64_C(0x000000000000ffff)
-#define POW_PP_GRP_MSKX_GRP_MSK_SHIFT 0
#define POW_WQ_INT_THRX_XXX_63_29 UINT64_C(0xffffffffe0000000)
#define POW_WQ_INT_THRX_TC_EN UINT64_C(0x0000000010000000)
#define POW_WQ_INT_THRX_TC_THR UINT64_C(0x000000000f000000)
-#define POW_WQ_INT_THRX_TC_THR_SHIFT 24
#define POW_WQ_INT_THRX_XXX_23_18 UINT64_C(0x0000000000fc0000)
#define POW_WQ_INT_THRX_DS_THR UINT64_C(0x000000000003f000)
-#define POW_WQ_INT_THRX_DS_THR_SHIFT 12
#define POW_WQ_INT_THRX_XXX_11_6 UINT64_C(0x0000000000000fc0)
#define POW_WQ_INT_THRX_IQ_THR UINT64_C(0x000000000000003f)
-#define POW_WQ_INT_THRX_IQ_THR_SHIFT 0
#define POW_WQ_INT_CNTX_XXX_63_28 UINT64_C(0xfffffffff0000000)
#define POW_WQ_INT_CNTX_TC_CNT UINT64_C(0x000000000f000000)
-#define POW_WQ_INT_CNTX_TC_CNT_SHIFT 24
#define POW_WQ_INT_CNTX_XXX_23_18 UINT64_C(0x0000000000fc0000)
#define POW_WQ_INT_CNTX_DS_CNT UINT64_C(0x000000000003f000)
-#define POW_WQ_INT_CNTX_DS_CNT_SHIFT 12
#define POW_WQ_INT_CNTX_XXX_11_6 UINT64_C(0x0000000000000fc0)
#define POW_WQ_INT_CNTX_IQ_CNT UINT64_C(0x000000000000003f)
-#define POW_WQ_INT_CNTX_IQ_CNT_SHIFT 0
#define POW_QOS_THRX_XXX_63_55 UINT64_C(0xff80000000000000)
#define POW_QOS_THRX_DES_CNT UINT64_C(0x007f000000000000)
-#define POW_QOS_THRX_DES_CNT_SHIFT 48
#define POW_QOS_THRX_XXX_47_43 UINT64_C(0x0000f80000000000)
#define POW_QOS_THRX_BUF_CNT UINT64_C(0x000007f000000000)
-#define POW_QOS_THRX_BUF_CNT_SHIFT 36
#define POW_QOS_THRX_XXX_35_31 UINT64_C(0x0000000f80000000)
#define POW_QOS_THRX_FREE_CNT UINT64_C(0x000000007f000000)
-#define POW_QOS_THRX_FREE_CNT_SHIFT 24
#define POW_QOS_THRX_XXX_23_18 UINT64_C(0x0000000000fc0000)
#define POW_QOS_THRX_MAX_THR UINT64_C(0x000000000003f000)
-#define POW_QOS_THRX_MAX_THR_SHIFT 12
#define POW_QOS_THRX_XXX_11_6 UINT64_C(0x0000000000000fc0)
#define POW_QOS_THRX_MIN_THR UINT64_C(0x000000000000003f)
-#define POW_QOS_THRX_MIN_THR_SHIFT 0
#define POW_QOS_RNDX_XXX_63_32 UINT64_C(0xffffffff00000000)
#define POW_QOS_RNDX_RND_P3 UINT64_C(0x00000000ff000000)
-#define POW_QOS_RNDX_RND_P3_SHIFT 24
#define POW_QOS_RNDX_RND_P2 UINT64_C(0x0000000000ff0000)
-#define POW_QOS_RNDX_RND_P2_SHIFT 16
#define POW_QOS_RNDX_RND_P1 UINT64_C(0x000000000000ff00)
-#define POW_QOS_RNDX_RND_P1_SHIFT 8
#define POW_QOS_RNDX_RND UINT64_C(0x00000000000000ff)
-#define POW_QOS_RNDX_RND_SHIFT 0
#define POW_WQ_INT_XXX_63_32 UINT64_C(0xffffffff00000000)
#define POW_WQ_INT_IQ_DIS UINT64_C(0x00000000ffff0000)
-#define POW_WQ_INT_IQ_DIS_SHIFT 16
#define POW_WQ_INT_WQ_INT UINT64_C(0x000000000000ffff)
-#define POW_WQ_INT_WQ_INT_SHIFT 0
#define POW_WQ_INT_PC_XXX_63_60 UINT64_C(0xf000000000000000)
#define POW_WQ_INT_PC_PC UINT64_C(0x0fffffff00000000)
-#define POW_WQ_INT_PC_PC_SHIFT 32
#define POW_WQ_INT_PC_XXX_31_28 UINT64_C(0x00000000f0000000)
#define POW_WQ_INT_PC_PC_THR UINT64_C(0x000000000fffff00)
-#define POW_WQ_INT_PC_PC_THR_SHIFT 8
#define POW_WQ_INT_PC_XXX_7_0 UINT64_C(0x00000000000000ff)
#define POW_NW_TIM_XXX_63_10 UINT64_C(0xfffffffffffffc00)
#define POW_NW_TIM_NW_TIM UINT64_C(0x00000000000003ff)
-#define POW_NW_TIM_NW_TIM_SHIFT 0
#define POW_ECC_ERR_XXX_63_45 UINT64_C(0xffffe00000000000)
#define POW_ECC_ERR_IOP_IE UINT64_C(0x00001fff00000000)
-#define POW_ECC_ERR_IOP_IE_SHIFT 32
#define POW_ECC_ERR_XXX_31_29 UINT64_C(0x00000000e0000000)
#define POW_ECC_ERR_IOP UINT64_C(0x000000001fff0000)
-#define POW_ECC_ERR_IOP_SHIFT 16
-#define POW_ECC_ERR_IOP_CSRPEND (UINT64_C(28) << POW_ECC_ERR_IOP_SHIFT)
-#define POW_ECC_ERR_IOP_DBGPEND (UINT64_C(27) << POW_ECC_ERR_IOP_SHIFT)
-#define POW_ECC_ERR_IOP_ADDWORK (UINT64_C(26) << POW_ECC_ERR_IOP_SHIFT)
-#define POW_ECC_ERR_IOP_ILLOP (UINT64_C(25) << POW_ECC_ERR_IOP_SHIFT)
-#define POW_ECC_ERR_IOP_PEND24 (UINT64_C(24) << POW_ECC_ERR_IOP_SHIFT)
-#define POW_ECC_ERR_IOP_PEND23 (UINT64_C(23) << POW_ECC_ERR_IOP_SHIFT)
-#define POW_ECC_ERR_IOP_PEND22 (UINT64_C(22) << POW_ECC_ERR_IOP_SHIFT)
-#define POW_ECC_ERR_IOP_PEND21 (UINT64_C(21) << POW_ECC_ERR_IOP_SHIFT)
-#define POW_ECC_ERR_IOP_TAGNULL (UINT64_C(20) << POW_ECC_ERR_IOP_SHIFT)
-#define POW_ECC_ERR_IOP_TAGNULLNULL (UINT64_C(19) << POW_ECC_ERR_IOP_SHIFT)
-#define POW_ECC_ERR_IOP_ORDATOM (UINT64_C(18) << POW_ECC_ERR_IOP_SHIFT)
-#define POW_ECC_ERR_IOP_NULL (UINT64_C(17) << POW_ECC_ERR_IOP_SHIFT)
-#define POW_ECC_ERR_IOP_NULLNULL (UINT64_C(16) << POW_ECC_ERR_IOP_SHIFT)
+#define POW_ECC_ERR_IOP_CSRPEND 28
+#define POW_ECC_ERR_IOP_DBGPEND 27
+#define POW_ECC_ERR_IOP_ADDWORK 26
+#define POW_ECC_ERR_IOP_ILLOP 25
+#define POW_ECC_ERR_IOP_PEND24 24
+#define POW_ECC_ERR_IOP_PEND23 23
+#define POW_ECC_ERR_IOP_PEND22 22
+#define POW_ECC_ERR_IOP_PEND21 21
+#define POW_ECC_ERR_IOP_TAGNULL 20
+#define POW_ECC_ERR_IOP_TAGNULLNULL 19
+#define POW_ECC_ERR_IOP_ORDATOM 18
+#define POW_ECC_ERR_IOP_NULL 17
+#define POW_ECC_ERR_IOP_NULLNULL 16
#define POW_ECC_ERR_XXX_15_14 UINT64_C(0x000000000000c000)
#define POW_ECC_ERR_RPE_IE UINT64_C(0x0000000000002000)
#define POW_ECC_ERR_RPE UINT64_C(0x0000000000001000)
#define POW_ECC_ERR_XXX_11_9 UINT64_C(0x0000000000000e00)
#define POW_ECC_ERR_SYN UINT64_C(0x00000000000001f0)
-#define POW_ECC_ERR_SYN_SHIFT 4
#define POW_ECC_ERR_DBE_IE UINT64_C(0x0000000000000008)
#define POW_ECC_ERR_SBE_IE UINT64_C(0x0000000000000004)
#define POW_ECC_ERR_DBE UINT64_C(0x0000000000000002)
@@ -327,35 +303,27 @@
#define POW_NOS_CNT_XXX_63_7 UINT64_C(0xffffffffffffff80)
#define POW_NOS_CNT_NOS_CNT UINT64_C(0x000000000000007f)
-#define POW_NOS_CNT_NOS_CNT_SHIFT 0
#define POW_WS_PC0_XXX_63_32 UINT64_C(0xffffffff00000000)
#define POW_WS_PC0_WS_PC UINT64_C(0x00000000ffffffff)
-#define POW_WS_PC0_WS_PC_SHIFT 0
#define POW_WA_PC0_XXX_63_32 UINT64_C(0xffffffff00000000)
#define POW_WA_PC0_WA_PC UINT64_C(0x00000000ffffffff)
-#define POW_WA_PC0_WA_PC_SHIFT 0
#define POW_IQ_CNT0_XXX_63_32 UINT64_C(0xffffffff00000000)
#define POW_IQ_CNT0_IQ_CNT UINT64_C(0x00000000ffffffff)
-#define POW_IQ_CNT0_IQ_CNT_SHIFT 0
#define POW_WA_COM_PC_XXX_63_32 UINT64_C(0xffffffff00000000)
#define POW_WA_COM_PC_WA_PC UINT64_C(0x00000000ffffffff)
-#define POW_WA_COM_PC_WA_PC_SHIFT 0
#define POW_WQ_COM_CNT_XXX_63_32 UINT64_C(0xffffffff00000000)
#define POW_WQ_COM_CNT_IQ_CNT UINT64_C(0x00000000ffffffff)
-#define POW_WQ_COM_CNT_IQ_CNT_SHIFT 0
#define POW_TS_PC_XXX_63_32 UINT64_C(0xffffffff00000000)
#define POW_TS_PC_TS_PC UINT64_C(0x00000000ffffffff)
-#define POW_TS_PC_TS_PC_SHIFT 0
#define POW_DS_PC_XXX_63_32 UINT64_C(0xffffffff00000000)
#define POW_DS_PC_DS_PC UINT64_C(0x00000000ffffffff)
-#define POW_DS_PC_DS_PC_SHIFT 0
#define POW_BIST_STAT_XXX_63_7 UINT64_C(0xfffffffffffe0000)
#define POW_BIST_STAT_PP UINT64_C(0x0000000000010000)
@@ -372,35 +340,19 @@
/* ---- pow operations */
-/* pow operations base */
-#define POW_OPERATION_BASE_IO_BIT UINT64_C(0x0001000000000000)
-#define POW_OPERATION_BASE_MAJOR_DID UINT64_C(0x0000f80000000000)
-#define POW_OPERATION_BASE_SUB_DID UINT64_C(0x0000070000000000)
-#define POW_OPERATION_BASE_IO_BIT_SHIFT 48
-#define POW_OPERATION_BASE_MAJOR_DID_SHIFT 43
-#define POW_OPERATION_BASE_SUB_DID_SHIFT 40
+/* -- pow load operations */
-/* get work load (subid = 0) */
+/* get work load */
+#define POW_OP_SUBDID_GET_WORK 0
#define POW_GET_WORK_LOAD_WAIT UINT64_C(0x0000000000000008)
-#define POW_GET_WORK_LOAD_2_0 UINT64_C(0x0000000000000007)
-#define POW_GET_WORK_LOAD_WAIT_SHIFT 3
-#define POW_GET_WORK_LOAD_2_0_SHIFT 0
-
-#define POW_GET_WORK_LOAD_RESULT_NO_WORK UINT64_C(0x8000000000000000)
-#define POW_GET_WORK_LOAD_RESULT_62_40 UINT64_C(0x7fffff0000000000)
-#define POW_GET_WORK_LOAD_RESULT_ADDR UINT64_C(0x000000ffffffffff)
-/* pow status load (subid = 1) */
+/* pow status load */
+#define POW_OP_SUBDID_STATUS_LOAD 1
#define POW_STATUS_LOAD_COREID UINT64_C(0x00000000000003c0)
#define POW_STATUS_LOAD_GET_REV UINT64_C(0x0000000000000020)
#define POW_STATUS_LOAD_GET_CUR UINT64_C(0x0000000000000010)
#define POW_STATUS_LOAD_GET_WQP UINT64_C(0x0000000000000008)
#define POW_STATUS_LOAD_GET_2_0 UINT64_C(0x0000000000000007)
-#define POW_STATUS_LOAD_GET_WQP_SHIFT 3
-#define POW_STATUS_LOAD_GET_CUR_SHIFT 4
-#define POW_STATUS_LOAD_COREID_SHIFT 6
-#define POW_STATUS_LOAD_GET_2_0_SHIFT 0
-#define POW_STATUS_LOAD_GET_REV_SHIFT 5
/* get_cur = 0 and get_wqp = 0 ("pend_tag") */
#define POW_STATUS_LOAD_RESULT_PEND_TAG_XXX_63_62 UINT64_C(0xc000000000000000)
@@ -543,15 +495,12 @@
"f\x24\x04" "GRP\0" \
"f\x00\x24" "WQP\0"
-/* pow memory load (subid = 2) */
-#define POW_MEMORY_LOAD_INDEX UINT64_C(0x000000000000ffe0)
-#define POW_MEMORY_LOAD_GET_DES UINT64_C(0x0000000000000010)
-#define POW_MEMORY_LOAD_GET_WQP UINT64_C(0x0000000000000008)
-#define POW_MEMORY_LOAD_2_0 UINT64_C(0x0000000000000007)
-#define POW_MEMORY_LOAD_2_0_SHIFT 0
-#define POW_MEMORY_LOAD_GET_WQP_SHIFT 3
-#define POW_MEMORY_LOAD_INDEX_SHIFT 5
-#define POW_MEMORY_LOAD_GET_DES_SHIFT 4
+/* pow memory load */
+#define POW_OP_SUBDID_MEMORY_LOAD 2
+#define POW_MEMORY_LOAD_INDEX UINT64_C(0x000000000000ffe0)
+#define POW_MEMORY_LOAD_GET_DES UINT64_C(0x0000000000000010)
+#define POW_MEMORY_LOAD_GET_WQP UINT64_C(0x0000000000000008)
+#define POW_MEMORY_LOAD_2_0 UINT64_C(0x0000000000000007)
/* get_des = 0 and get_wqp = 0 ("tag") */
#define POW_MEMORY_LOAD_RESULT_TAG_XXX_63_51 UINT64_C(0xfff8000000000000)
@@ -603,15 +552,13 @@
"f\x20\x02" "PEND_TYPE\0" \
"f\x00\x20" "PEND_TAG\0"
-/* pow index/pointer load (subid = 3) */
+/* pow index/pointer load */
+#define POW_OP_SUBDID_IDXPTR_LOAD 3
+
#define POW_IDXPTR_LOAD_QOSGRP UINT64_C(0x00000000000001e0)
#define POW_IDXPTR_LOAD_GET_DES_GET_TAIL UINT64_C(0x0000000000000010)
#define POW_IDXPTR_LOAD_GET_RMT UINT64_C(0x0000000000000008)
#define POW_IDXPTR_LOAD_2_0 UINT64_C(0x0000000000000007)
-#define POW_IDXPTR_LOAD_QOSGRP_SHIFT 5
-#define POW_IDXPTR_LOAD_GET_DES_GET_TAIL_SHIFT 4
-#define POW_IDXPTR_LOAD_2_0_SHIFT 0
-#define POW_IDXPTR_LOAD_GET_RMT_SHIFT 3
/* get_rmt = 0 and get_des_get_tail = 0 ("qos") */
#define POW_IDXPTR_LOAD_RESULT_QOS_FREE_LOC_XXX_63_52 UINT64_C(0xfff0000000000000)
@@ -697,19 +644,37 @@
"b\x24" "RMT_ONE\0" \
"f\x00\x24" "RMT_TAIL\0"
-/* pow index/pointer load (subid = 2) */
+/* pow null rd */
+#define POW_OP_SUBDID_NULL_RD 4
#define POW_NULL_RD_LOAD_39_3 UINT64_C(0x000000fffffffff8)
#define POW_NULL_RD_LOAD_2_0 UINT64_C(0x0000000000000007)
-#define POW_NULL_RD_LOAD_39_3_SHIFT 3
-#define POW_NULL_RD_LOAD_2_0_SHIFT 0
#define POW_NULL_RD_LOAD_RESULT_63_2 UINT64_C(0xfffffffffffffffc)
#define POW_NULL_RD_LOAD_RESULT_STATUS UINT64_C(0x0000000000000003)
+/* -- pow iobdma operations */
+
+#define POW_MAJOR_DID 0xc
+#define POW_IOBDMA_LEN 1 /* always 1 for POW */
+
+/* pow iobdma get work */
+#define POW_IOBDMA_SUBDID_GET_WORK POW_OP_SUBDID_GET_WORK
+#define POW_IOBDMA_GET_WORK_WAIT UINT64_C(0x0000000000000008)
+
+#define POW_IOBDMA_GET_WORK_RESULT_NO_WORK UINT64_C(0x8000000000000000)
+#define POW_IOBDMA_GET_WORK_RESULT_ADDR UINT64_C(0x000000ffffffffff)
+
+/* pow iobdma null rd */
+#define POW_IOBDMA_SUBDID_NULL_RD POW_OP_SUBDID_NULL_RD
+#define POW_IOBDMA_NULL_RD_RESULT_STATUS UINT64_C(0x0000000000000003)
+
+/* -- pow store operations */
/* pow store operations */
+#define POW_STORE_SUBDID_SWTAG_FULL 0
+#define POW_STORE_SUBDID_DESCHED 3
+#define POW_STORE_SUBDID_OTHER 1
#define POW_PHY_ADDR_STORE_ADDR UINT64_C(0x0000000fffffffff)
-#define POW_PHY_ADDR_STORE_ADDR_SHIFT 0
#define POW_STORE_DATA_NO_SCHED UINT64_C(0x8000000000000000)
#define POW_STORE_DATA_62_61 UINT64_C(0x6000000000000000)
@@ -720,48 +685,6 @@
#define POW_STORE_DATA_GRP UINT64_C(0x0000007800000000)
#define POW_STORE_DATA_TYPE UINT64_C(0x0000000700000000)
#define POW_STORE_DATA_TAG UINT64_C(0x00000000ffffffff)
-#define POW_STORE_DATA_INDEX_SHIFT 48
-#define POW_STORE_DATA_OP_SHIFT 44
-#define POW_STORE_DATA_NO_SCHED_SHIFT 63
-#define POW_STORE_DATA_62_61_SHIFT 61
-#define POW_STORE_DATA_43_42_SHIFT 42
-#define POW_STORE_DATA_QOS_SHIFT 39
-#define POW_STORE_DATA_GRP_SHIFT 35
-#define POW_STORE_DATA_TYPE_SHIFT 32
-#define POW_STORE_DATA_TAG_SHIFT 0
-
-/* pow iobdma operations */
-
-/* pow iobdma operations base*/
-#define POW_IOBDMA_BASE_SCRADDR UINT64_C(0xff00000000000000)
-#define POW_IOBDMA_BASE_LEN UINT64_C(0x00ff000000000000)
-#define POW_IOBDMA_BASE_MAJOR_DID UINT64_C(0x0000f80000000000)
-#define POW_IOBDMA_BASE_SUB_DID UINT64_C(0x0000070000000000)
-#define POW_IOBDMA_BASE_39_0 UINT64_C(0x000000ffffffffff)
-#define POW_IOBDMA_BASE_MAJOR_DID_SHIFT 43
-#define POW_IOBDMA_BASE_LEN_SHIFT 48
-#define POW_IOBDMA_BASE_39_0_SHIFT 0
-#define POW_IOBDMA_BASE_SCRADDR_SHIFT 56
-#define POW_IOBDMA_BASE_SUB_DID_SHIFT 40
-
-/* pow iobdma get work (subid = 0) */
-#define POW_IOBDMA_GET_WORK_39_4 UINT64_C(0x000000ffffffffff)
-#define POW_IOBDMA_GET_WORK_WAIT UINT64_C(0x0000000000000008)
-#define POW_IOBDMA_GET_WORK_2_0 UINT64_C(0x0000000000000007)
-#define POW_IOBDMA_GET_WORK_WAIT_SHIFT 3
-#define POW_IOBDMA_GET_WORK_39_4_SHIFT 0
-#define POW_IOBDMA_GET_WORK_2_0_SHIFT 0
-
-#define POW_IOBDMA_GET_WORK_RESULT_NO_WORK UINT64_C(0x8000000000000000)
-#define POW_IOBDMA_GET_WORK_RESULT_62_40 UINT64_C(0x7fffff0000000000)
-#define POW_IOBDMA_GET_WORK_RESULT_ADDR UINT64_C(0x000000ffffffffff)
-
-/* pow iobdma null rd (subid = 4) */
-#define POW_IOBDMA_NULL_RD_39_0 UINT64_C(0x000000ffffffffff)
-#define POW_IOBDMA_NULL_RD_39_0_SHIFT 0
-
-#define POW_IOBDMA_NULL_RD_RESULT_63_2 UINT64_C(0xfffffffffffffffc)
-#define POW_IOBDMA_NULL_RD_RESULT_STATUS UINT64_C(0x0000000000000003)
/* ------------------------------------------------------------------------- */
@@ -774,7 +697,6 @@
"\020" /* hex display */ \
"\020" /* %016x format */ \
"f\x00\x28" "NEXT\0"
-#define POW_WQE_WORD0_NEXT_SHIFT 0
#define POW_WQE_WORD1_XXX_63_42 UINT64_C(0xfffffc0000000000)
#define POW_WQE_WORD1_QOS UINT64_C(0x0000038000000000)
@@ -789,10 +711,6 @@
"f\x23\x04" "GRP\0" \
"f\x20\x03" "TT\0" \
"f\x00\x20" "TAG\0"
-#define POW_WQE_WORD1_TT_SHIFT 32
-#define POW_WQE_WORD1_QOS_SHIFT 39
-#define POW_WQE_WORD1_GRP_SHIFT 35
-#define POW_WQE_WORD1_TAG_SHIFT 0
/* ------------------------------------------------------------------------- */
Index: src/sys/arch/mips/cavium/dev/octeon_smireg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_smireg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_smireg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_smireg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_smireg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_smireg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_smireg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -51,12 +51,12 @@
/* SMI CMD */
#define SMI_CMD_63_17 UINT64_C(0xfffffffffffe0000)
#define SMI_CMD_PHY_OP UINT64_C(0x0000000000010000)
+#define SMI_CMD_PHY_OP_READ 1
+#define SMI_CMD_PHY_OP_WRITE 0
#define SMI_CMD_15_13 UINT64_C(0x000000000000e000)
#define SMI_CMD_PHY_ADR UINT64_C(0x0000000000001f00)
-#define SMI_CMD_PHY_ADR_SHIFT 8
#define SMI_CMD_7_5 UINT64_C(0x00000000000000e0)
#define SMI_CMD_REG_ADR UINT64_C(0x000000000000001f)
-#define SMI_CMD_REG_ADR_SHIFT 0
/* SMI_WR_DAT */
#define SMI_WR_DAT_63_18 UINT64_C(0xfffffffffffc0000)
Index: src/sys/arch/mips/cavium/dev/octeon_twsi.c
diff -u src/sys/arch/mips/cavium/dev/octeon_twsi.c:1.1 src/sys/arch/mips/cavium/dev/octeon_twsi.c:1.2
--- src/sys/arch/mips/cavium/dev/octeon_twsi.c:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_twsi.c Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_twsi.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_twsi.c,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -30,7 +30,7 @@
#undef TWSITEST
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_twsi.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_twsi.c,v 1.2 2020/06/18 13:52:08 simonb Exp $");
#include "opt_octeon.h"
@@ -239,8 +239,10 @@ octeon_twsi_hlcm_read(struct octeon_twsi
resid = len;
while (resid > 4) {
- cmd = MIO_TWS_SW_TWSI_OP_FOUR | MIO_TWS_SW_TWSI_R
- | (addr << MIO_TWS_SW_TWSI_A_SHIFT);
+ cmd =
+ __SHIFTIN(MIO_TWS_SW_TWSI_OP_FOUR, MIO_TWS_SW_TWSI_OP) |
+ MIO_TWS_SW_TWSI_R |
+ __SHIFTIN(addr, MIO_TWS_SW_TWSI_A);
octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd);
octeon_twsi_wait(sc);
cmd = octeon_twsi_reg_rd(sc);
@@ -249,8 +251,10 @@ octeon_twsi_hlcm_read(struct octeon_twsi
}
while (resid > 0) {
- cmd = MIO_TWS_SW_TWSI_OP_ONE | MIO_TWS_SW_TWSI_R
- | (addr << MIO_TWS_SW_TWSI_A_SHIFT);
+ cmd =
+ __SHIFTIN(MIO_TWS_SW_TWSI_OP_ONE, MIO_TWS_SW_TWSI_OP) |
+ MIO_TWS_SW_TWSI_R |
+ __SHIFTIN(addr, MIO_TWS_SW_TWSI_A);
octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd);
octeon_twsi_wait(sc);
cmd = octeon_twsi_reg_rd(sc);
@@ -279,18 +283,20 @@ octeon_twsi_hlcm_write(struct octeon_tws
resid = len;
while (resid > 4) {
- cmd = MIO_TWS_SW_TWSI_OP_FOUR
- | (addr << MIO_TWS_SW_TWSI_A_SHIFT)
- | _BUFTOLE32(&buf[len - 1 - resid]);
+ cmd =
+ __SHIFTIN(MIO_TWS_SW_TWSI_OP_FOUR, MIO_TWS_SW_TWSI_OP) |
+ __SHIFTIN(addr, MIO_TWS_SW_TWSI_A) |
+ __SHIFTIN(_BUFTOLE32(&buf[len - 1 - resid]), MIO_TWS_SW_TWSI_D);
octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd);
octeon_twsi_wait(sc);
resid -= 4;
}
while (resid > 0) {
- cmd = MIO_TWS_SW_TWSI_OP_ONE
- | (addr << MIO_TWS_SW_TWSI_A_SHIFT)
- | buf[len - 1 - resid];
+ cmd =
+ __SHIFTIN(MIO_TWS_SW_TWSI_OP_ONE, MIO_TWS_SW_TWSI_OP) |
+ __SHIFTIN(addr, MIO_TWS_SW_TWSI_A) |
+ __SHIFTIN(buf[len - 1 - resid], MIO_TWS_SW_TWSI_D);
octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd);
octeon_twsi_wait(sc);
resid--;
@@ -372,9 +378,10 @@ octeon_twsi_control_read(struct octeon_t
{
uint64_t cmd;
- cmd = MIO_TWS_SW_TWSI_OP_EXTEND
- | (addr << MIO_TWS_SW_TWSI_A_SHIFT)
- | eop_ia;
+ cmd =
+ __SHIFTIN(MIO_TWS_SW_TWSI_OP_EXTEND, MIO_TWS_SW_TWSI_OP) |
+ __SHIFTIN(addr, MIO_TWS_SW_TWSI_A) |
+ __SHIFTIN(eop_ia, MIO_TWS_SW_TWSI_EOP_IA);
octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd);
octeon_twsi_wait(sc);
return (uint8_t)octeon_twsi_reg_rd(sc, MIO_TWS_SW_TWSI_OFFSET);
@@ -386,10 +393,11 @@ octeon_twsi_control_write(struct octeon_
{
uint64_t cmd;
- cmd = MIO_TWS_SW_TWSI_OP_EXTEND
- | (addr << MIO_TWS_SW_TWSI_A_SHIFT)
- | eop_ia
- | _BUFTOLE32(&buf[len - 1 - resid]);
+ cmd =
+ __SHIFTIN(MIO_TWS_SW_TWSI_OP_EXTEND, MIO_TWS_SW_TWSI_OP) |
+ __SHIFTIN(addr, MIO_TWS_SW_TWSI_A_SHIFT) |
+ __SHIFTIN(eop_ia, MIO_TWS_SW_TWSI_EOP_IA) |
+ __SHIFTIN(_BUFTOLE32(&buf[len - 1 - resid]), MIO_TWS_SW_TWSI_D);
octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd);
octeon_twsi_wait(sc);
}
Index: src/sys/arch/mips/cavium/dev/octeon_twsireg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_twsireg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_twsireg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_twsireg.h:1.1 Wed Apr 29 08:32:01 2015
+++ src/sys/arch/mips/cavium/dev/octeon_twsireg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_twsireg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
+/* $NetBSD: octeon_twsireg.h,v 1.2 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -46,30 +46,26 @@
#define MIO_TWS_SW_TWSI_SLONLY UINT64_C(0x4000000000000000)
#define MIO_TWS_SW_TWSI_EIA UINT64_C(0x2000000000000000)
#define MIO_TWS_SW_TWSI_OP UINT64_C(0x1e00000000000000)
-#define MIO_TWS_SW_TWSI_OP_SHIFT 57
-#define MIO_TWS_SW_TWSI_OP_ONE (0x0 << MIO_TWS_SW_TWSI_OP_SHIFT)
-#define MIO_TWS_SW_TWSI_OP_MCLK (0x4 << MIO_TWS_SW_TWSI_OP_SHIFT)
-#define MIO_TWS_SW_TWSI_OP_EXTEND (0x6 << MIO_TWS_SW_TWSI_OP_SHIFT)
-#define MIO_TWS_SW_TWSI_OP_FOUR (0x8 << MIO_TWS_SW_TWSI_OP_SHIFT)
-#define MIO_TWS_SW_TWSI_OP_COMBR (0x1 << MIO_TWS_SW_TWSI_OP_SHIFT)
-#define MIO_TWS_SW_TWSI_OP_10BIT (0x2 << MIO_TWS_SW_TWSI_OP_SHIFT)
+#define MIO_TWS_SW_TWSI_OP_ONE 0
+#define MIO_TWS_SW_TWSI_OP_MCLK 4
+#define MIO_TWS_SW_TWSI_OP_EXTEND 6
+#define MIO_TWS_SW_TWSI_OP_FOUR 8
+#define MIO_TWS_SW_TWSI_OP_COMBR 1
+#define MIO_TWS_SW_TWSI_OP_10BIT 2
#define MIO_TWS_SW_TWSI_R UINT64_C(0x0100000000000000)
#define MIO_TWS_SW_TWSI_SOVR UINT64_C(0x0080000000000000)
#define MIO_TWS_SW_TWSI_SIZE UINT64_C(0x0070000000000000)
#define MIO_TWS_SW_TWSI_SCR UINT64_C(0x000c000000000000)
#define MIO_TWS_SW_TWSI_A UINT64_C(0x0003ff0000000000)
-#define MIO_TWS_SW_TWSI_A_SHIFT 40
#define MIO_TWS_SW_TWSI_IA UINT64_C(0x000000f800000000)
#define MIO_TWS_SW_TWSI_EOP_IA UINT64_C(0x0000000700000000)
-#define MIO_TWS_SW_TWSI_EOP_IA_SHIFT 32
-#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_SLAVE_ADD (0x0 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT)
-#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_DATA (0x1 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT)
-#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_CTL (0x2 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT)
-#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_CLKCTL (0x3 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT)
-#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_STAT (0x3 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT)
-#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_SLAVE_ADD_EXT \
- (0x4 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT)
-#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_RST (0x7 << MIO_TWS_SW_TWSI_EOP_IA_SHIFT)
+#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_SLAVE_ADD 0
+#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_DATA 1
+#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_CTL 2
+#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_CLKCTL 3
+#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_STAT 3
+#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_SLAVE_ADD_EXT 4
+#define MIO_TWS_SW_TWSI_EOP_IA_TWSI_RST 7
#define MIO_TWS_SW_TWSI_D UINT64_C(0x00000000ffffffff)
#define MIO_TWS_TWSI_SW_V UINT64_C(0xc000000000000000)
Index: src/sys/arch/mips/cavium/dev/octeon_fpa.c
diff -u src/sys/arch/mips/cavium/dev/octeon_fpa.c:1.5 src/sys/arch/mips/cavium/dev/octeon_fpa.c:1.6
--- src/sys/arch/mips/cavium/dev/octeon_fpa.c:1.5 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_fpa.c Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_fpa.c,v 1.5 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_fpa.c,v 1.6 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -29,7 +29,7 @@
#undef FPADEBUG
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_fpa.c,v 1.5 2020/05/31 06:27:06 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_fpa.c,v 1.6 2020/06/18 13:52:08 simonb Exp $");
#include "opt_octeon.h"
@@ -44,8 +44,8 @@ __KERNEL_RCSID(0, "$NetBSD: octeon_fpa.c
#include <mips/cavium/octeonvar.h>
#include <mips/cavium/include/iobusvar.h>
-#include <mips/cavium/dev/octeon_fpavar.h>
#include <mips/cavium/dev/octeon_fpareg.h>
+#include <mips/cavium/dev/octeon_fpavar.h>
#ifdef FPADEBUG
#define DPRINTF(x) printf x
Index: src/sys/arch/mips/cavium/dev/octeon_fpavar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_fpavar.h:1.4 src/sys/arch/mips/cavium/dev/octeon_fpavar.h:1.5
--- src/sys/arch/mips/cavium/dev/octeon_fpavar.h:1.4 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_fpavar.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_fpavar.h,v 1.4 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_fpavar.h,v 1.5 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -29,6 +29,8 @@
#ifndef _OCTEON_FPAVAR_H_
#define _OCTEON_FPAVAR_H_
+#include <mips/cavium/octeonreg.h>
+
struct octfpa_buf {
int fb_poolno; /* pool # */
@@ -95,12 +97,8 @@ void octfpa_dump(void);
static __inline uint64_t
octfpa_load(uint64_t fpapool)
{
- uint64_t addr;
-
- addr =
- (0x1ULL << 48) |
- (0x5ULL << 43) |
- (fpapool & 0x07ULL) << 40;
+ /* for FPA operations, subdid == pool number */
+ uint64_t addr = OCTEON_ADDR_IO_DID(FPA_MAJOR_DID, fpapool);
return octeon_read_csr(addr);
}
@@ -109,6 +107,7 @@ octfpa_load(uint64_t fpapool)
static __inline uint64_t
octfpa_iobdma(struct octfpa_softc *sc, int srcaddr, int len)
{
+
/* XXX */
return 0ULL;
}
@@ -117,27 +116,26 @@ octfpa_iobdma(struct octfpa_softc *sc, i
static __inline void
octfpa_store(uint64_t addr, uint64_t fpapool, uint64_t dwbcount)
{
- uint64_t ptr;
-
- ptr =
- (0x1ULL << 48) |
- (0x5ULL << 43) |
- (fpapool & 0x07ULL) << 40 |
- (addr & 0xffffffffffULL);
+ /* for FPA operations, subdid == pool number */
+ uint64_t ptr =
+ OCTEON_ADDR_IO_DID(FPA_MAJOR_DID, fpapool) |
+ __SHIFTIN(addr, FPA_OPS_STORE_ADDR);
OCTEON_SYNCWS;
- octeon_write_csr(ptr, (dwbcount & 0x0ffULL));
+ octeon_write_csr(ptr, __SHIFTIN(dwbcount, FPA_OPS_STORE_DATA_DWBCOUNT));
}
static __inline paddr_t
octfpa_buf_get_paddr(struct octfpa_buf *fb)
{
+
return octfpa_load(fb->fb_poolno);
}
static __inline void
octfpa_buf_put_paddr(struct octfpa_buf *fb, paddr_t paddr)
{
+
KASSERT(paddr >= fb->fb_paddr);
KASSERT(paddr < fb->fb_paddr + fb->fb_len);
octfpa_store(paddr, fb->fb_poolno, fb->fb_size / 128);
@@ -154,4 +152,4 @@ octfpa_buf_put(struct octfpa_buf *fb, vo
octfpa_buf_put_paddr(fb, paddr);
}
-#endif
+#endif /* _OCTEON_FPAVAR_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_gmxvar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_gmxvar.h:1.4 src/sys/arch/mips/cavium/dev/octeon_gmxvar.h:1.5
--- src/sys/arch/mips/cavium/dev/octeon_gmxvar.h:1.4 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_gmxvar.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_gmxvar.h,v 1.4 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_gmxvar.h,v 1.5 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -133,13 +133,13 @@ struct octgmx_attach_args {
*ga_gmx_port;
};
-#define CN30XXGMX_FILTER_NADDRS_MAX 8 /* XXX elsewhere */
+#define OCTEON_GMX_FILTER_NADDRS_MAX 8 /* XXX elsewhere */
-enum CN30XXGMX_FILTER_POLICY {
- CN30XXGMX_FILTER_POLICY_ACCEPT_ALL,
- CN30XXGMX_FILTER_POLICY_ACCEPT,
- CN30XXGMX_FILTER_POLICY_REJECT,
- CN30XXGMX_FILTER_POLICY_REJECT_ALL
+enum OCTEON_GMX_FILTER_POLICY {
+ OCTEON_GMX_FILTER_POLICY_ACCEPT_ALL,
+ OCTEON_GMX_FILTER_POLICY_ACCEPT,
+ OCTEON_GMX_FILTER_POLICY_REJECT,
+ OCTEON_GMX_FILTER_POLICY_REJECT_ALL
};
int octgmx_link_enable(struct octgmx_port_softc *, int);
@@ -150,7 +150,7 @@ int octgmx_stats_init(struct octgmx_por
void octgmx_tx_int_enable(struct octgmx_port_softc *, int);
void octgmx_rx_int_enable(struct octgmx_port_softc *, int);
int octgmx_setfilt(struct octgmx_port_softc *,
- enum CN30XXGMX_FILTER_POLICY, size_t, uint8_t **);
+ enum OCTEON_GMX_FILTER_POLICY, size_t, uint8_t **);
int octgmx_rx_frm_ctl_enable(struct octgmx_port_softc *, uint64_t);
int octgmx_rx_frm_ctl_disable(struct octgmx_port_softc *, uint64_t);
int octgmx_tx_thresh(struct octgmx_port_softc *, int);
@@ -173,4 +173,4 @@ octgmx_link_status(struct octgmx_port_so
return (sc->sc_link & RXN_RX_INBND_STATUS) ? 1 : 0;
}
-#endif
+#endif /* _OCTEON_GMXVAR_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_pip.c
diff -u src/sys/arch/mips/cavium/dev/octeon_pip.c:1.4 src/sys/arch/mips/cavium/dev/octeon_pip.c:1.5
--- src/sys/arch/mips/cavium/dev/octeon_pip.c:1.4 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pip.c Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pip.c,v 1.4 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_pip.c,v 1.5 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_pip.c,v 1.4 2020/05/31 06:27:06 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_pip.c,v 1.5 2020/06/18 13:52:08 simonb Exp $");
#include "opt_octeon.h"
@@ -192,11 +192,11 @@ octpip_port_config(struct octpip_softc *
CLR(prt_tag, PIP_PRT_TAGN_IP4_SRC);
CLR(prt_tag, PIP_PRT_TAGN_IP6_SRC);
CLR(prt_tag, PIP_PRT_TAGN_IP4_DST);
- SET(prt_tag, PIP_PRT_TAGN_TCP6_TAG_ORDERED);
- SET(prt_tag, PIP_PRT_TAGN_TCP4_TAG_ORDERED);
- SET(prt_tag, PIP_PRT_TAGN_IP6_TAG_ORDERED);
- SET(prt_tag, PIP_PRT_TAGN_IP4_TAG_ORDERED);
- SET(prt_tag, PIP_PRT_TAGN_NON_TAG_ORDERED);
+ SET(prt_tag, __SHIFTIN(PIP_PRT_TAGN_TCP6_TAG_ORDERED, PIP_PRT_TAGN_TCP6_TAG));
+ SET(prt_tag, __SHIFTIN(PIP_PRT_TAGN_TCP4_TAG_ORDERED, PIP_PRT_TAGN_TCP4_TAG));
+ SET(prt_tag, __SHIFTIN(PIP_PRT_TAGN_IP6_TAG_ORDERED, PIP_PRT_TAGN_IP6_TAG));
+ SET(prt_tag, __SHIFTIN(PIP_PRT_TAGN_IP4_TAG_ORDERED, PIP_PRT_TAGN_IP4_TAG));
+ SET(prt_tag, __SHIFTIN(PIP_PRT_TAGN_NON_TAG_ORDERED, PIP_PRT_TAGN_NON_TAG));
SET(prt_tag, sc->sc_receive_group & PIP_PRT_TAGN_GRP);
ip_offset = 0;
@@ -242,7 +242,7 @@ octpip_stats(struct octpip_softc *sc, st
_PIP_WR8(sc, PIP_STAT_CTL_OFFSET, pip_stat_ctl | PIP_STAT_CTL_RDCLR);
reg = &octpip_dump_stats_[gmx_port];
tmp = _PIP_RD8(sc, reg->offset);
- pkts = (tmp & 0xffffffff00000000ULL) >> 32;
+ pkts = __SHIFTOUT(tmp, PIP_STAT0_PRTN_DRP_PKTS);
if_statadd(ifp, if_iqdrops, pkts);
_PIP_WR8(sc, PIP_STAT_CTL_OFFSET, pip_stat_ctl);
Index: src/sys/arch/mips/cavium/dev/octeon_powvar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_powvar.h:1.4 src/sys/arch/mips/cavium/dev/octeon_powvar.h:1.5
--- src/sys/arch/mips/cavium/dev/octeon_powvar.h:1.4 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_powvar.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_powvar.h,v 1.4 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_powvar.h,v 1.5 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -31,6 +31,8 @@
#include <sys/cpu.h>
+#include <mips/cavium/octeonreg.h>
+
#define POW_TAG_TYPE_ORDERED 0
#define POW_TAG_TYPE_ATOMIC 1
#define POW_TAG_TYPE_NULL 2
@@ -118,10 +120,8 @@ octpow_ops_get_work_load(
int wait) /* 0-1 */
{
uint64_t ptr =
- POW_OPERATION_BASE_IO_BIT |
- __BITS64_SET(POW_OPERATION_BASE_MAJOR_DID, 0x0c) |
- __BITS64_SET(POW_OPERATION_BASE_SUB_DID, 0x00) |
- __BITS64_SET(POW_GET_WORK_LOAD_WAIT, wait);
+ OCTEON_ADDR_IO_DID(POW_MAJOR_DID, POW_OP_SUBDID_GET_WORK) |
+ (wait ? POW_GET_WORK_LOAD_WAIT : 0);
return octeon_xkphys_read_8(ptr);
}
@@ -145,13 +145,11 @@ octpow_ops_pow_status(
int get_wqp) /* 0-1 */
{
uint64_t ptr =
- POW_OPERATION_BASE_IO_BIT |
- __BITS64_SET(POW_OPERATION_BASE_MAJOR_DID, 0x0c) |
- __BITS64_SET(POW_OPERATION_BASE_SUB_DID, 0x01) |
- __BITS64_SET(POW_STATUS_LOAD_COREID, coreid) |
- __BITS64_SET(POW_STATUS_LOAD_GET_REV, get_rev) |
- __BITS64_SET(POW_STATUS_LOAD_GET_CUR, get_cur) |
- __BITS64_SET(POW_STATUS_LOAD_GET_WQP, get_wqp);
+ OCTEON_ADDR_IO_DID(POW_MAJOR_DID, POW_OP_SUBDID_STATUS_LOAD) |
+ __SHIFTIN(coreid, POW_STATUS_LOAD_COREID) |
+ __SHIFTIN(get_rev, POW_STATUS_LOAD_GET_REV) |
+ __SHIFTIN(get_cur, POW_STATUS_LOAD_GET_CUR) |
+ __SHIFTIN(get_wqp, POW_STATUS_LOAD_GET_WQP);
return octeon_xkphys_read_8(ptr);
}
@@ -171,12 +169,10 @@ octpow_ops_pow_memory(
int get_wqp) /* 0-1 */
{
uint64_t ptr =
- POW_OPERATION_BASE_IO_BIT |
- __BITS64_SET(POW_OPERATION_BASE_MAJOR_DID, 0x0c) |
- __BITS64_SET(POW_OPERATION_BASE_SUB_DID, 0x02) |
- __BITS64_SET(POW_MEMORY_LOAD_INDEX, index) |
- __BITS64_SET(POW_MEMORY_LOAD_GET_DES, get_des) |
- __BITS64_SET(POW_MEMORY_LOAD_GET_WQP, get_wqp);
+ OCTEON_ADDR_IO_DID(POW_MAJOR_DID, POW_OP_SUBDID_MEMORY_LOAD) |
+ __SHIFTIN(index, POW_MEMORY_LOAD_INDEX) |
+ __SHIFTIN(get_des, POW_MEMORY_LOAD_GET_DES) |
+ __SHIFTIN(get_wqp, POW_MEMORY_LOAD_GET_WQP);
return octeon_xkphys_read_8(ptr);
}
@@ -197,12 +193,10 @@ octpow_ops_pow_idxptr(
int get_rmt) /* 0-1 */
{
uint64_t ptr =
- POW_OPERATION_BASE_IO_BIT |
- __BITS64_SET(POW_OPERATION_BASE_MAJOR_DID, 0x0c) |
- __BITS64_SET(POW_OPERATION_BASE_SUB_DID, 0x03) |
- __BITS64_SET(POW_IDXPTR_LOAD_QOSGRP, qosgrp) |
- __BITS64_SET(POW_IDXPTR_LOAD_GET_DES_GET_TAIL, get_des_get_tail) |
- __BITS64_SET(POW_IDXPTR_LOAD_GET_RMT, get_rmt);
+ OCTEON_ADDR_IO_DID(POW_MAJOR_DID, POW_OP_SUBDID_IDXPTR_LOAD) |
+ __SHIFTIN(qosgrp, POW_IDXPTR_LOAD_QOSGRP) |
+ __SHIFTIN(get_des_get_tail, POW_IDXPTR_LOAD_GET_DES_GET_TAIL) |
+ __SHIFTIN(get_rmt, POW_IDXPTR_LOAD_GET_RMT);
return octeon_xkphys_read_8(ptr);
}
@@ -212,11 +206,8 @@ octpow_ops_pow_idxptr(
static __inline uint64_t
octpow_ops_null_rd_load(void)
{
- uint64_t ptr =
- POW_OPERATION_BASE_IO_BIT |
- __BITS64_SET(POW_OPERATION_BASE_MAJOR_DID, 0x0c) |
- __BITS64_SET(POW_OPERATION_BASE_SUB_DID, 0x04);
-
+ uint64_t ptr = OCTEON_ADDR_IO_DID(POW_MAJOR_DID, POW_OP_SUBDID_NULL_RD);
+
return octeon_xkphys_read_8(ptr);
}
@@ -236,14 +227,9 @@ octpow_ops_get_work_iobdma(
/* ``scraddr'' part is index in 64-bit words, not address */
const int scrindex = scraddr / sizeof(uint64_t);
- uint64_t args =
- __BITS64_SET(POW_IOBDMA_GET_WORK_WAIT, wait);
- uint64_t value =
- __BITS64_SET(POW_IOBDMA_BASE_SCRADDR, scrindex) |
- __BITS64_SET(POW_IOBDMA_BASE_LEN, 0x01) |
- __BITS64_SET(POW_IOBDMA_BASE_MAJOR_DID, 0x0c) |
- __BITS64_SET(POW_IOBDMA_BASE_SUB_DID, 0x00) |
- __BITS64_SET(POW_IOBDMA_BASE_39_0, args);
+ uint64_t value = IOBDMA_CREATE(POW_MAJOR_DID,
+ POW_IOBDMA_SUBDID_GET_WORK, scrindex, POW_IOBDMA_LEN,
+ wait ? POW_IOBDMA_GET_WORK_WAIT : 0);
octeon_iobdma_write_8(value);
}
@@ -257,12 +243,8 @@ octpow_ops_null_rd_iobdma(
/* ``scraddr'' part is index in 64-bit words, not address */
const int scrindex = scraddr / sizeof(uint64_t);
- uint64_t value =
- __BITS64_SET(POW_IOBDMA_BASE_SCRADDR, scrindex) |
- __BITS64_SET(POW_IOBDMA_BASE_LEN, 0x01) |
- __BITS64_SET(POW_IOBDMA_BASE_MAJOR_DID, 0x0c) |
- __BITS64_SET(POW_IOBDMA_BASE_SUB_DID, 0x04) |
- __BITS64_SET(POW_IOBDMA_BASE_39_0, 0);
+ uint64_t value = IOBDMA_CREATE(POW_MAJOR_DID,
+ POW_IOBDMA_SUBDID_NULL_RD, scrindex, POW_IOBDMA_LEN, 0);
octeon_iobdma_write_8(value);
}
@@ -282,21 +264,18 @@ octpow_store(
uint32_t tag) /* 0-0xffff.ffff */
{
/* Physical Address to Store to POW */
- uint64_t ptr =
- POW_OPERATION_BASE_IO_BIT |
- __BITS64_SET(POW_OPERATION_BASE_MAJOR_DID, 0x0c) |
- __BITS64_SET(POW_OPERATION_BASE_SUB_DID, subdid) |
- __BITS64_SET(POW_PHY_ADDR_STORE_ADDR, addr);
+ uint64_t ptr = OCTEON_ADDR_IO_DID(POW_MAJOR_DID, subdid) |
+ __SHIFTIN(addr, POW_PHY_ADDR_STORE_ADDR);
/* Store Data on Store to POW */
uint64_t args =
- __BITS64_SET(POW_STORE_DATA_NO_SCHED, no_sched) |
- __BITS64_SET(POW_STORE_DATA_INDEX, index) |
- __BITS64_SET(POW_STORE_DATA_OP, op) |
- __BITS64_SET(POW_STORE_DATA_QOS, qos) |
- __BITS64_SET(POW_STORE_DATA_GRP, grp) |
- __BITS64_SET(POW_STORE_DATA_TYPE, type) |
- __BITS64_SET(POW_STORE_DATA_TAG, tag);
+ __SHIFTIN(no_sched, POW_STORE_DATA_NO_SCHED) |
+ __SHIFTIN(index, POW_STORE_DATA_INDEX) |
+ __SHIFTIN(op, POW_STORE_DATA_OP) |
+ __SHIFTIN(qos, POW_STORE_DATA_QOS) |
+ __SHIFTIN(grp, POW_STORE_DATA_GRP) |
+ __SHIFTIN(type, POW_STORE_DATA_TYPE) |
+ __SHIFTIN(tag, POW_STORE_DATA_TAG);
octeon_xkphys_write_8(ptr, args);
}
@@ -306,8 +285,9 @@ octpow_store(
static __inline void
octpow_ops_swtag(int type, uint32_t tag)
{
+
octpow_store(
- 1, /* subdid == 1 */
+ POW_STORE_SUBDID_OTHER,
0, /* addr (not used for SWTAG) */
0, /* no_sched (not used for SWTAG) */
0, /* index (not used for SWTAG) */
@@ -324,8 +304,9 @@ octpow_ops_swtag(int type, uint32_t tag)
static __inline void
octpow_ops_swtag_full(paddr_t addr, int grp, int type, uint32_t tag)
{
+
octpow_store(
- 0, /* subdid == 0 */
+ POW_STORE_SUBDID_SWTAG_FULL,
addr,
0, /* no_sched (not used for SWTAG_FULL) */
0, /* index (not used for SWTAG_FULL) */
@@ -341,8 +322,9 @@ octpow_ops_swtag_full(paddr_t addr, int
static __inline void
octpow_ops_swtag_desched(int no_sched, int grp, int type, uint32_t tag)
{
+
octpow_store(
- 3, /* subdid == 3 */
+ POW_STORE_SUBDID_DESCHED,
0, /* addr (not used for SWTAG_DESCHED) */
no_sched,
0, /* index (not used for SWTAG_DESCHED) */
@@ -358,8 +340,9 @@ octpow_ops_swtag_desched(int no_sched, i
static __inline void
octpow_ops_desched(int no_sched)
{
+
octpow_store(
- 3, /* subdid == 3 */
+ POW_STORE_SUBDID_DESCHED,
0, /* addr (not used for DESCHED) */
no_sched,
0, /* index (not used for DESCHED) */
@@ -375,8 +358,9 @@ octpow_ops_desched(int no_sched)
static __inline void
octpow_ops_addwq(paddr_t addr, int qos, int grp, int type, uint32_t tag)
{
+
octpow_store(
- 1, /* subdid == 1 */
+ POW_STORE_SUBDID_OTHER,
addr,
0, /* no_sched (not used for ADDWQ) */
0, /* index (not used for ADDWQ) */
@@ -392,8 +376,9 @@ octpow_ops_addwq(paddr_t addr, int qos,
static __inline void
octpow_ops_upd_wqp_grp(paddr_t addr, int grp)
{
+
octpow_store(
- 1, /* subdid == 1 */
+ POW_STORE_SUBDID_OTHER,
addr,
0, /* no_sched (not used for UPD_WQP_GRP) */
0, /* index (not used for UPD_WQP_GRP) */
@@ -409,8 +394,9 @@ octpow_ops_upd_wqp_grp(paddr_t addr, int
static __inline void
octpow_ops_clr_nsched(paddr_t addr, int index)
{
+
octpow_store(
- 1, /* subdid == 1 */
+ POW_STORE_SUBDID_OTHER,
addr,
0, /* no_sched (not used for CLR_NSCHED) */
index,
@@ -426,8 +412,9 @@ octpow_ops_clr_nsched(paddr_t addr, int
static __inline void
octpow_ops_nop(void)
{
+
octpow_store(
- 1, /* subdid == 1 */
+ POW_STORE_SUBDID_OTHER,
0, /* addr (not used for NOP) */
0, /* no_sched (not used for NOP) */
0, /* index (not used for NOP) */
@@ -446,6 +433,7 @@ octpow_ops_nop(void)
static __inline void
octpow_work_request_async(uint64_t scraddr, uint64_t wait)
{
+
octpow_ops_get_work_iobdma(scraddr, wait);
}
@@ -483,13 +471,14 @@ octpow_config_int_pc(struct octpow_softc
/* from SDK */
pc_thr = (cpu_clock_hz) / (unit * 16 * 256);
- wq_int_pc = pc_thr << POW_WQ_INT_PC_PC_THR_SHIFT;
+ wq_int_pc = __SHIFTIN(pc_thr, POW_WQ_INT_PC_PC_THR);
_POW_WR8(sc, POW_WQ_INT_PC_OFFSET, wq_int_pc);
}
static __inline void
octpow_config_int_pc_rate(struct octpow_softc *sc, int rate)
{
+
octpow_config_int_pc(sc, sc->sc_int_pc_base / rate);
}
Index: src/sys/arch/mips/cavium/dev/octeon_smivar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_smivar.h:1.4 src/sys/arch/mips/cavium/dev/octeon_smivar.h:1.5
--- src/sys/arch/mips/cavium/dev/octeon_smivar.h:1.4 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_smivar.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_smivar.h,v 1.4 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_smivar.h,v 1.5 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -47,4 +47,4 @@ int octsmi_read(struct octsmi_softc *, i
int octsmi_write(struct octsmi_softc *, int, int, uint16_t);
void octsmi_set_clock(struct octsmi_softc *, uint64_t);
-#endif
+#endif /* _OCTEON_SMIVAR_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_gmx.c
diff -u src/sys/arch/mips/cavium/dev/octeon_gmx.c:1.11 src/sys/arch/mips/cavium/dev/octeon_gmx.c:1.12
--- src/sys/arch/mips/cavium/dev/octeon_gmx.c:1.11 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_gmx.c Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_gmx.c,v 1.11 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_gmx.c,v 1.12 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -32,7 +32,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_gmx.c,v 1.11 2020/05/31 06:27:06 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_gmx.c,v 1.12 2020/06/18 13:52:08 simonb Exp $");
#include "opt_octeon.h"
@@ -418,15 +418,15 @@ octgmx_tx_ovr_bp_enable(struct octgmx_po
ovr_bp = _GMX_RD8(sc, GMX0_TX_OVR_BP);
if (enable) {
- CLR(ovr_bp, (1 << sc->sc_port_no) << TX_OVR_BP_EN_SHIFT);
- SET(ovr_bp, (1 << sc->sc_port_no) << TX_OVR_BP_BP_SHIFT);
+ CLR(ovr_bp, __SHIFTIN(__BIT(sc->sc_port_no), TX_OVR_BP_EN));
+ SET(ovr_bp, __SHIFTIN(__BIT(sc->sc_port_no), TX_OVR_BP_BP));
/* XXX really??? */
- SET(ovr_bp, (1 << sc->sc_port_no) << TX_OVR_BP_IGN_FULL_SHIFT);
+ SET(ovr_bp, __SHIFTIN(__BIT(sc->sc_port_no), TX_OVR_BP_IGN_FULL));
} else {
- SET(ovr_bp, (1 << sc->sc_port_no) << TX_OVR_BP_EN_SHIFT);
- CLR(ovr_bp, (1 << sc->sc_port_no) << TX_OVR_BP_BP_SHIFT);
+ SET(ovr_bp, __SHIFTIN(__BIT(sc->sc_port_no), TX_OVR_BP_EN));
+ CLR(ovr_bp, __SHIFTIN(__BIT(sc->sc_port_no), TX_OVR_BP_BP));
/* XXX really??? */
- SET(ovr_bp, (1 << sc->sc_port_no) << TX_OVR_BP_IGN_FULL_SHIFT);
+ SET(ovr_bp, __SHIFTIN(__BIT(sc->sc_port_no), TX_OVR_BP_IGN_FULL));
}
_GMX_WR8(sc, GMX0_TX_OVR_BP, ovr_bp);
return 0;
@@ -639,7 +639,7 @@ octgmx_rgmii_speed(struct octgmx_port_so
}
sc->sc_link = newlink;
- switch (sc->sc_link & RXN_RX_INBND_SPEED) {
+ switch (__SHIFTOUT(sc->sc_link, RXN_RX_INBND_SPEED)) {
case RXN_RX_INBND_SPEED_2_5:
baudrate = IF_Mbps(10);
break;
@@ -824,7 +824,7 @@ octgmx_rgmii_speed_speed(struct octgmx_p
* GMX Port Configuration Registers
* Duplex mode: 0 = half-duplex mode, 1=full-duplex
*/
- if (ISSET(sc->sc_link, RXN_RX_INBND_DUPLEX)) {
+ if (__SHIFTOUT(sc->sc_link, RXN_RX_INBND_DUPLEX)) {
/* Full-Duplex */
SET(prt_cfg, PRTN_CFG_DUPLEX);
} else {
@@ -973,7 +973,7 @@ octgmx_rgmii_set_filter(struct octgmx_po
/* XXX XXX XXX */
/* XXX XXX XXX */
- SET(cam_en, 1ULL << multi);
+ SET(cam_en, __BIT(multi));
/* XXX XXX XXX */
for (i = 0; i < 6; i++) {
@@ -1012,17 +1012,17 @@ setmulti:
ISSET(ifp->if_flags, IFF_PROMISC)) {
/* XXX XXX XXX */
dprintf("accept all multicast\n");
- SET(ctl, RXN_ADR_CTL_MCST_ACCEPT);
+ ctl |= __SHIFTIN(RXN_ADR_CTL_MCST_ACCEPT, RXN_ADR_CTL_MCST);
/* XXX XXX XXX */
} else if (multi) {
/* XXX XXX XXX */
dprintf("use cam\n");
- SET(ctl, RXN_ADR_CTL_MCST_AFCAM);
+ ctl |= __SHIFTIN(RXN_ADR_CTL_MCST_AFCAM, RXN_ADR_CTL_MCST);
/* XXX XXX XXX */
} else {
/* XXX XXX XXX */
dprintf("reject all multicast\n");
- SET(ctl, RXN_ADR_CTL_MCST_REJECT);
+ ctl |= __SHIFTIN(RXN_ADR_CTL_MCST_REJECT, RXN_ADR_CTL_MCST);
/* XXX XXX XXX */
}
/* XXX XXX XXX */
@@ -1093,11 +1093,11 @@ octgmx_stats(struct octgmx_port_softc *s
*/
/* XXX local namespace */
-#define _POLICY CN30XXGMX_FILTER_POLICY
-#define _POLICY_ACCEPT_ALL CN30XXGMX_FILTER_POLICY_ACCEPT_ALL
-#define _POLICY_ACCEPT CN30XXGMX_FILTER_POLICY_ACCEPT
-#define _POLICY_REJECT CN30XXGMX_FILTER_POLICY_REJECT
-#define _POLICY_REJECT_ALL CN30XXGMX_FILTER_POLICY_REJECT_ALL
+#define _POLICY OCTEON_GMX_FILTER_POLICY
+#define _POLICY_ACCEPT_ALL OCTEON_GMX_FILTER_POLICY_ACCEPT_ALL
+#define _POLICY_ACCEPT OCTEON_GMX_FILTER_POLICY_ACCEPT
+#define _POLICY_REJECT OCTEON_GMX_FILTER_POLICY_REJECT
+#define _POLICY_REJECT_ALL OCTEON_GMX_FILTER_POLICY_REJECT_ALL
static int octgmx_setfilt_addrs(struct octgmx_port_softc *, size_t,
uint8_t **);
@@ -1120,16 +1120,19 @@ octgmx_setfilt(struct octgmx_port_softc
KASSERT(naddrs == 0);
KASSERT(addrs == NULL);
- SET(rx_adr_ctl, (policy == _POLICY_ACCEPT_ALL) ?
- RXN_ADR_CTL_MCST_ACCEPT : RXN_ADR_CTL_MCST_REJECT);
+ SET(rx_adr_ctl,
+ __SHIFTIN((policy == _POLICY_ACCEPT_ALL) ?
+ RXN_ADR_CTL_MCST_ACCEPT : RXN_ADR_CTL_MCST_REJECT),
+ RXN_ADR_CTL_MCST);
break;
case _POLICY_ACCEPT:
case _POLICY_REJECT:
- if (naddrs > CN30XXGMX_FILTER_NADDRS_MAX)
+ if (naddrs > OCTEON_GMX_FILTER_NADDRS_MAX)
return E2BIG;
SET(rx_adr_ctl, (policy == _POLICY_ACCEPT) ?
RXN_ADR_CTL_CAM_MODE : 0);
- SET(rx_adr_ctl, RXN_ADR_CTL_MCST_AFCAM);
+ SET(rx_adr_ctl,
+ __SHIFTIN(RXN_ADR_CTL_MCST_AFCAM, RXN_ADR_CTL_MCST);
/* set GMX0_RXN_ADR_CAM_EN, GMX0_RXN_ADR_CAM[0-5] */
octgmx_setfilt_addrs(sc, naddrs, addrs);
break;
@@ -1146,16 +1149,16 @@ octgmx_setfilt_addrs(struct octgmx_port_
uint8_t **addrs)
{
uint64_t rx_adr_cam_en;
- uint64_t rx_adr_cam_addrs[CN30XXGMX_FILTER_NADDRS_MAX];
+ uint64_t rx_adr_cam_addrs[OCTEON_GMX_FILTER_NADDRS_MAX];
int i, j;
- KASSERT(naddrs <= CN30XXGMX_FILTER_NADDRS_MAX);
+ KASSERT(naddrs <= OCTEON_GMX_FILTER_NADDRS_MAX);
rx_adr_cam_en = 0;
(void)memset(rx_adr_cam_addrs, 0, sizeof(rx_adr_cam_addrs));
for (i = 0; i < naddrs; i++) {
- SET(rx_adr_cam_en, 1ULL << i);
+ SET(rx_adr_cam_en, __BIT(i));
for (j = 0; j < 6; j++)
SET(rx_adr_cam_addrs[j],
(uint64_t)addrs[i][j] << (8 * i));
Index: src/sys/arch/mips/cavium/dev/octeon_rnm.c
diff -u src/sys/arch/mips/cavium/dev/octeon_rnm.c:1.11 src/sys/arch/mips/cavium/dev/octeon_rnm.c:1.12
--- src/sys/arch/mips/cavium/dev/octeon_rnm.c:1.11 Mon Jun 8 01:17:05 2020
+++ src/sys/arch/mips/cavium/dev/octeon_rnm.c Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_rnm.c,v 1.11 2020/06/08 01:17:05 simonb Exp $ */
+/* $NetBSD: octeon_rnm.c,v 1.12 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -99,7 +99,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_rnm.c,v 1.11 2020/06/08 01:17:05 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_rnm.c,v 1.12 2020/06/18 13:52:08 simonb Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -108,10 +108,11 @@ __KERNEL_RCSID(0, "$NetBSD: octeon_rnm.c
#include <sys/systm.h>
#include <mips/locore.h>
+#include <mips/cavium/octeonreg.h>
+#include <mips/cavium/octeonvar.h>
#include <mips/cavium/include/iobusvar.h>
#include <mips/cavium/dev/octeon_rnmreg.h>
#include <mips/cavium/dev/octeon_corereg.h>
-#include <mips/cavium/octeonvar.h>
#include <sys/bus.h>
@@ -345,10 +346,7 @@ octrnm_raw_entropy(struct octrnm_softc *
static uint64_t
octrnm_load(struct octrnm_softc *sc)
{
- uint64_t addr =
- RNM_OPERATION_BASE_IO_BIT |
- __BITS64_SET(RNM_OPERATION_BASE_MAJOR_DID, 0x08) |
- __BITS64_SET(RNM_OPERATION_BASE_SUB_DID, 0x00);
+ uint64_t addr = OCTEON_ADDR_IO_DID(RNM_MAJOR_DID, RNM_SUB_DID);
return octeon_xkphys_read_8(addr);
}
@@ -361,12 +359,10 @@ octrnm_load(struct octrnm_softc *sc)
static void
octrnm_iobdma(struct octrnm_softc *sc, uint64_t *buf, unsigned nwords)
{
+ /* ``scraddr'' part is index in 64-bit words, not address */
size_t scraddr = OCTEON_CVMSEG_OFFSET(csm_rnm);
- uint64_t iobdma =
- __SHIFTIN(scraddr/sizeof(uint64_t), IOBDMA_SCRADDR) |
- __SHIFTIN(nwords, IOBDMA_LEN) |
- __SHIFTIN(RNM_IOBDMA_MAJORDID, IOBDMA_MAJORDID) |
- __SHIFTIN(RNM_IOBDMA_SUBDID, IOBDMA_SUBDID);
+ uint64_t iobdma = IOBDMA_CREATE(RNM_MAJOR_DID, RNM_SUB_DID,
+ scraddr / sizeof(uint64_t), nwords, 0);
KASSERT(nwords < 128); /* iobdma address restriction */
KASSERT(nwords <= CVMSEG_LM_RNM_SIZE); /* size of CVMSEG LM buffer */
Index: src/sys/arch/mips/cavium/dev/octeon_ipd.c
diff -u src/sys/arch/mips/cavium/dev/octeon_ipd.c:1.3 src/sys/arch/mips/cavium/dev/octeon_ipd.c:1.4
--- src/sys/arch/mips/cavium/dev/octeon_ipd.c:1.3 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_ipd.c Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_ipd.c,v 1.3 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_ipd.c,v 1.4 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_ipd.c,v 1.3 2020/05/31 06:27:06 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_ipd.c,v 1.4 2020/06/18 13:52:08 simonb Exp $");
#include "opt_octeon.h"
@@ -40,6 +40,7 @@ __KERNEL_RCSID(0, "$NetBSD: octeon_ipd.c
#include <mips/locore.h>
#include <mips/cavium/octeonvar.h>
#include <mips/cavium/dev/octeon_ciureg.h>
+#include <mips/cavium/dev/octeon_fpareg.h>
#include <mips/cavium/dev/octeon_fpavar.h>
#include <mips/cavium/dev/octeon_pipreg.h>
#include <mips/cavium/dev/octeon_ipdreg.h>
@@ -50,7 +51,7 @@ __KERNEL_RCSID(0, "$NetBSD: octeon_ipd.c
#include <netinet/ip.h>
#define IP_OFFSET(data, word2) \
- ((uintptr_t)(data) + (uintptr_t)((word2 & PIP_WQE_WORD2_IP_OFFSET) >> PIP_WQE_WORD2_IP_OFFSET_SHIFT))
+ ((uintptr_t)(data) + (uintptr_t)__SHIFTOUT(word2, PIP_WQE_WORD2_IP_OFFSET))
#ifdef CNMAC_DEBUG
void octipd_intr_evcnt_attach(struct octipd_softc *);
@@ -163,7 +164,8 @@ octipd_config(struct octipd_softc *sc)
ctl_status = _IPD_RD8(sc, IPD_CTL_STATUS_OFFSET);
CLR(ctl_status, IPD_CTL_STATUS_OPC_MODE);
- SET(ctl_status, IPD_CTL_STATUS_OPC_MODE_ALL);
+ SET(ctl_status,
+ __SHIFTIN(IPD_CTL_STATUS_OPC_MODE_ALL, IPD_CTL_STATUS_OPC_MODE));
SET(ctl_status, IPD_CTL_STATUS_PBP_EN);
/*
Index: src/sys/arch/mips/cavium/dev/octeon_pkovar.h
diff -u src/sys/arch/mips/cavium/dev/octeon_pkovar.h:1.3 src/sys/arch/mips/cavium/dev/octeon_pkovar.h:1.4
--- src/sys/arch/mips/cavium/dev/octeon_pkovar.h:1.3 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pkovar.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pkovar.h,v 1.3 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_pkovar.h,v 1.4 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -97,37 +97,37 @@ octpko_cmd_word0(int sz1, int sz0, int s
int le, int n2, int q, int r, int g, int ipoffp1, int ii, int df, int segs,
int totalbytes)
{
- uint64_t cmd = 0;
+ uint64_t cmd =
+ __SHIFTIN(sz1, PKO_CMD_WORD0_SZ1) |
+ __SHIFTIN(sz0, PKO_CMD_WORD0_SZ0) |
+ __SHIFTIN(s1, PKO_CMD_WORD0_S1) |
+ __SHIFTIN(reg1, PKO_CMD_WORD0_REG1) |
+ __SHIFTIN(s0, PKO_CMD_WORD0_S0) |
+ __SHIFTIN(reg0, PKO_CMD_WORD0_REG0) |
+ __SHIFTIN(le, PKO_CMD_WORD0_LE) |
+ __SHIFTIN(n2, PKO_CMD_WORD0_N2) |
+ __SHIFTIN(q, PKO_CMD_WORD0_Q) |
+ __SHIFTIN(r, PKO_CMD_WORD0_R) |
+ __SHIFTIN(g, PKO_CMD_WORD0_G) |
+ __SHIFTIN(ipoffp1, PKO_CMD_WORD0_IPOFFP1) |
+ __SHIFTIN(ii, PKO_CMD_WORD0_II) |
+ __SHIFTIN(df, PKO_CMD_WORD0_DF) |
+ __SHIFTIN(segs, PKO_CMD_WORD0_SEGS) |
+ __SHIFTIN(totalbytes, PKO_CMD_WORD0_TOTALBYTES);
- SET(cmd, (((uint64_t)sz1 << 62) & PKO_CMD_WORD0_SZ1)
- | (((uint64_t)sz0 << 60) & PKO_CMD_WORD0_SZ0)
- | (((uint64_t)s1 << 59) & PKO_CMD_WORD0_S1)
- | (((uint64_t)reg1 << 48) & PKO_CMD_WORD0_REG1)
- | (((uint64_t)s0 << 47) & PKO_CMD_WORD0_S0)
- | (((uint64_t)reg0 << 36) & PKO_CMD_WORD0_REG0)
- | (((uint64_t)le << 35) & PKO_CMD_WORD0_LE)
- | (((uint64_t)n2 << 34) & PKO_CMD_WORD0_N2)
- | (((uint64_t)q << 33) & PKO_CMD_WORD0_Q)
- | (((uint64_t)r << 32) & PKO_CMD_WORD0_R)
- | (((uint64_t)g << 31) & PKO_CMD_WORD0_G)
- | (((uint64_t)ipoffp1 << 24) & PKO_CMD_WORD0_IPOFFP1)
- | (((uint64_t)ii << 23) & PKO_CMD_WORD0_II)
- | (((uint64_t)df << 22) & PKO_CMD_WORD0_DF)
- | (((uint64_t)segs << 16) & PKO_CMD_WORD0_SEGS)
- | (((uint64_t)totalbytes << 0) & PKO_CMD_WORD0_TOTALBYTES));
return cmd;
}
static __inline uint64_t
octpko_cmd_word1(int i, int back, int pool, int size, paddr_t addr)
{
- uint64_t cmd = 0;
+ uint64_t cmd =
+ __SHIFTIN(i, PKO_CMD_WORD1_I) |
+ __SHIFTIN(back, PKO_CMD_WORD1_BACK) |
+ __SHIFTIN(pool, PKO_CMD_WORD1_POOL) |
+ __SHIFTIN(size, PKO_CMD_WORD1_SIZE) |
+ __SHIFTIN(addr, PKO_CMD_WORD1_ADDR);
- SET(cmd, (((uint64_t)i << 63) & PKO_CMD_WORD1_I)
- | (((uint64_t)back << 59) & PKO_CMD_WORD1_BACK)
- | (((uint64_t)pool << 56) & PKO_CMD_WORD1_POOL)
- | (((uint64_t)size << 40) & PKO_CMD_WORD1_SIZE)
- | (((uint64_t)addr << 0) & PKO_CMD_WORD1_ADDR));
return cmd;
}
@@ -140,11 +140,7 @@ octpko_op_store(uint64_t args, uint64_t
{
paddr_t addr;
- addr =
- ((uint64_t)1 << 48) |
- ((uint64_t)(CN30XXPKO_MAJORDID & 0x1f) << 43) |
- ((uint64_t)(CN30XXPKO_SUBDID & 0x7) << 40) |
- ((uint64_t)args);
+ addr = OCTEON_ADDR_IO_DID(PKO_MAJOR_DID, PKO_SUB_DID) | args;
/* XXX */
OCTEON_SYNCW;
octeon_write_csr(addr, value);
@@ -156,10 +152,10 @@ octpko_op_doorbell_write(int pid, int qi
uint64_t args, value;
args =
- ((uint64_t)(pid & 0x3f) << 12) |
- ((uint64_t)(qid & 0x1ff) << 3);
- value = wdc & 0xfffff;
+ __SHIFTIN(pid, PKO_DOORBELL_WRITE_PID) |
+ __SHIFTIN(qid, PKO_DOORBELL_WRITE_QID);
+ value = __SHIFTIN(wdc, PKO_DOORBELL_WRITE_WDC);
octpko_op_store(args, value);
}
-#endif
+#endif /* _OCTEON_PKOVAR_H_ */
Index: src/sys/arch/mips/cavium/dev/octeon_rnmreg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_rnmreg.h:1.3 src/sys/arch/mips/cavium/dev/octeon_rnmreg.h:1.4
--- src/sys/arch/mips/cavium/dev/octeon_rnmreg.h:1.3 Wed May 13 21:09:02 2020
+++ src/sys/arch/mips/cavium/dev/octeon_rnmreg.h Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_rnmreg.h,v 1.3 2020/05/13 21:09:02 riastradh Exp $ */
+/* $NetBSD: octeon_rnmreg.h,v 1.4 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -33,10 +33,14 @@
#ifndef _OCTEON_RNMREG_H_
#define _OCTEON_RNMREG_H_
+/* ---- IO address IDs */
+#define RNM_MAJOR_DID 8
+#define RNM_SUB_DID 0
+
/* ---- register addresses */
-#define RNM_CTL_STATUS 0x0001180040000000ULL
-#define RNM_BIST_STATUS 0x0001180040000008ULL
+#define RNM_CTL_STATUS UINT64_C(0x0001180040000000)
+#define RNM_BIST_STATUS UINT64_C(0x0001180040000008)
/* ---- register bits */
@@ -52,28 +56,6 @@
#define RNM_BIST_STATUS_RRC UINT64_C(0x0000000000000002)
#define RNM_BIST_STATUS_MEM UINT64_C(0x0000000000000001)
-/* ---- operations */
-#define RNM_OPERATION_BASE_IO_BIT UINT64_C(0x0001000000000000)
-#define RNM_OPERATION_BASE_MAJOR_DID UINT64_C(0x0000f80000000000)
-#define RNM_OPERATION_BASE_SUB_DID UINT64_C(0x0000070000000000)
-#define RNM_OPERATION_BASE_MAJOR_DID_SHIFT 43
-#define RNM_OPERATION_BASE_SUB_DID_SHIFT 40
-#define RNM_OPERATION_BASE_IO_BIT_SHIFT 48
-
-/* ---- IOBDMA */
-
-/* 4.7 IOBDMA Operations (XXX move me elsewhere) */
-#define IOBDMA_SCRADDR __BITS(63,56)
-#define IOBDMA_LEN __BITS(55,48)
-#define IOBDMA_MAJORDID __BITS(47,43)
-#define IOBDMA_SUBDID __BITS(42,40)
-/* reserved 39:36 */
-#define IOBDMA_OFFSET __BITS(35,0)
-
-/* 19.1.12 IOBDMA Operations, p. 661 */
-#define RNM_IOBDMA_MAJORDID 8
-#define RNM_IOBDMA_SUBDID 0
-
/* ---- snprintb */
#define RNM_CTL_STATUS_BITS \
Index: src/sys/arch/mips/cavium/dev/octeon_smi.c
diff -u src/sys/arch/mips/cavium/dev/octeon_smi.c:1.3 src/sys/arch/mips/cavium/dev/octeon_smi.c:1.4
--- src/sys/arch/mips/cavium/dev/octeon_smi.c:1.3 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_smi.c Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_smi.c,v 1.3 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_smi.c,v 1.4 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_smi.c,v 1.3 2020/05/31 06:27:06 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_smi.c,v 1.4 2020/06/18 13:52:08 simonb Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -35,6 +35,7 @@ __KERNEL_RCSID(0, "$NetBSD: octeon_smi.c
#include <sys/mbuf.h>
#include <mips/locore.h>
#include <mips/cavium/octeonvar.h>
+#include <mips/cavium/dev/octeon_fpareg.h>
#include <mips/cavium/dev/octeon_fpavar.h>
#include <mips/cavium/dev/octeon_pipreg.h>
#include <mips/cavium/dev/octeon_smireg.h>
@@ -77,9 +78,10 @@ octsmi_read(struct octsmi_softc *sc, int
uint64_t smi_rd;
int timo;
- _SMI_WR8(sc, SMI_CMD_OFFSET, SMI_CMD_PHY_OP |
- (phy_addr << SMI_CMD_PHY_ADR_SHIFT) |
- (reg << SMI_CMD_REG_ADR_SHIFT));
+ _SMI_WR8(sc, SMI_CMD_OFFSET,
+ __SHIFTIN(SMI_CMD_PHY_OP_READ, SMI_CMD_PHY_OP) |
+ __SHIFTIN(phy_addr, SMI_CMD_PHY_ADR) |
+ __SHIFTIN(reg, SMI_CMD_REG_ADR));
timo = 10000;
smi_rd = _SMI_RD8(sc, SMI_RD_DAT_OFFSET);
@@ -108,8 +110,10 @@ octsmi_write(struct octsmi_softc *sc, in
SET(smi_wr, value);
_SMI_WR8(sc, SMI_WR_DAT_OFFSET, smi_wr);
- _SMI_WR8(sc, SMI_CMD_OFFSET, (phy_addr << SMI_CMD_PHY_ADR_SHIFT) |
- (reg << SMI_CMD_REG_ADR_SHIFT));
+ _SMI_WR8(sc, SMI_CMD_OFFSET,
+ __SHIFTIN(SMI_CMD_PHY_OP_WRITE, SMI_CMD_PHY_OP) |
+ __SHIFTIN(phy_addr, SMI_CMD_PHY_ADR) |
+ __SHIFTIN(reg, SMI_CMD_REG_ADR));
timo = 10000;
smi_wr = _SMI_RD8(sc, SMI_WR_DAT_OFFSET);
Index: src/sys/arch/mips/cavium/dev/octeon_pow.c
diff -u src/sys/arch/mips/cavium/dev/octeon_pow.c:1.6 src/sys/arch/mips/cavium/dev/octeon_pow.c:1.7
--- src/sys/arch/mips/cavium/dev/octeon_pow.c:1.6 Sun May 31 06:27:06 2020
+++ src/sys/arch/mips/cavium/dev/octeon_pow.c Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pow.c,v 1.6 2020/05/31 06:27:06 simonb Exp $ */
+/* $NetBSD: octeon_pow.c,v 1.7 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_pow.c,v 1.6 2020/05/31 06:27:06 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_pow.c,v 1.7 2020/06/18 13:52:08 simonb Exp $");
#include "opt_octeon.h" /* CNMAC_DEBUG */
@@ -129,16 +129,6 @@ int int_rate = 1;
/* -------------------------------------------------------------------------- */
-/* ---- operation primitive functions */
-
-/* Load Operations */
-
-/* IOBDMA Operations */
-
-/* Store Operations */
-
-/* -------------------------------------------------------------------------- */
-
/* ---- utility functions */
@@ -281,13 +271,12 @@ static inline void
octpow_config_int(struct octpow_softc *sc, int group, uint64_t tc_thr,
uint64_t ds_thr, uint64_t iq_thr)
{
- uint64_t wq_int_thr;
-
- wq_int_thr =
+ uint64_t wq_int_thr =
POW_WQ_INT_THRX_TC_EN |
- (tc_thr << POW_WQ_INT_THRX_TC_THR_SHIFT) |
- (ds_thr << POW_WQ_INT_THRX_DS_THR_SHIFT) |
- (iq_thr << POW_WQ_INT_THRX_IQ_THR_SHIFT);
+ __SHIFTIN(tc_thr, POW_WQ_INT_THRX_TC_THR) |
+ __SHIFTIN(ds_thr, POW_WQ_INT_THRX_DS_THR) |
+ __SHIFTIN(iq_thr, POW_WQ_INT_THRX_IQ_THR);
+
_POW_WR8(sc, POW_WQ_INT_THR0_OFFSET + (group * 8), wq_int_thr);
}
@@ -523,7 +512,7 @@ octpow_intr_work(struct octpow_softc *sc
uint64_t *work;
uint64_t count = 0;
- _POW_WR8(sc, POW_PP_GRP_MSK0_OFFSET, UINT64_C(1) << pow_ih->pi_group);
+ _POW_WR8(sc, POW_PP_GRP_MSK0_OFFSET, __BIT(pow_ih->pi_group));
_POW_INTR_WORK_DEBUG_IVAL(sc, pow_ih);
@@ -546,7 +535,7 @@ octpow_intr(void *data)
{
struct octpow_intr_handle *pow_ih = data;
struct octpow_softc *sc = pow_ih->pi_sc;
- uint64_t wq_int_mask = UINT64_C(0x1) << pow_ih->pi_group;
+ uint64_t wq_int_mask = __BIT(pow_ih->pi_group);
#ifdef CNMAC_INTR_FEEDBACK_RING
octpow_intr_work(sc, pow_ih, recv_cnt);
@@ -554,7 +543,8 @@ octpow_intr(void *data)
octpow_intr_work(sc, pow_ih, INT_MAX);
#endif /* CNMAC_INTR_FEEDBACK_RING */
- _POW_WR8(sc, POW_WQ_INT_OFFSET, wq_int_mask << POW_WQ_INT_WQ_INT_SHIFT);
+ _POW_WR8(sc, POW_WQ_INT_OFFSET,
+ __SHIFTIN(wq_int_mask, POW_WQ_INT_WQ_INT));
return 1;
}
Index: src/sys/arch/mips/cavium/dev/octeon_uart.c
diff -u src/sys/arch/mips/cavium/dev/octeon_uart.c:1.6 src/sys/arch/mips/cavium/dev/octeon_uart.c:1.7
--- src/sys/arch/mips/cavium/dev/octeon_uart.c:1.6 Mon Jun 15 07:48:12 2020
+++ src/sys/arch/mips/cavium/dev/octeon_uart.c Thu Jun 18 13:52:08 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_uart.c,v 1.6 2020/06/15 07:48:12 simonb Exp $ */
+/* $NetBSD: octeon_uart.c,v 1.7 2020/06/18 13:52:08 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_uart.c,v 1.6 2020/06/15 07:48:12 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_uart.c,v 1.7 2020/06/18 13:52:08 simonb Exp $");
#include "opt_octeon.h"
@@ -60,9 +60,6 @@ static int octuart_com_enable(struct com
static void octuart_com_disable(struct com_softc *);
-#define CN30XXUART_BUSYDETECT 0x7
-
-
/* XXX */
int octuart_com_cnattach(bus_space_tag_t, int, int);
