Module Name: src
Committed By: ryo
Date: Wed Jul 1 08:02:13 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: trap.c
src/sys/arch/arm/include: cputypes.h
Log Message:
add workaround for Neoverse N1 erratum 1542419
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/aarch64/aarch64/trap.c
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/include/cputypes.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.28 src/sys/arch/aarch64/aarch64/trap.c:1.29
--- src/sys/arch/aarch64/aarch64/trap.c:1.28 Wed Jul 1 08:01:07 2020
+++ src/sys/arch/aarch64/aarch64/trap.c Wed Jul 1 08:02:13 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.28 2020/07/01 08:01:07 ryo Exp $ */
+/* $NetBSD: trap.c,v 1.29 2020/07/01 08:02:13 ryo Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.28 2020/07/01 08:01:07 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.29 2020/07/01 08:02:13 ryo Exp $");
#include "opt_arm_intr_impl.h"
#include "opt_compat_netbsd32.h"
@@ -338,6 +338,11 @@ configure_cpu_traps(void)
if (__SHIFTOUT(ctr_el0_cpu, CTR_EL0_DIC) == 1)
ctr_el0_cpu |= CTR_EL0_IMIN_LINE;
+ /* Neoverse N1 erratum 1542419 */
+ if (CPU_ID_NEOVERSEN1_P(ci->ci_id.ac_midr) &&
+ __SHIFTOUT(ctr_el0_cpu, CTR_EL0_DIC) == 1)
+ ctr_el0_cpu &= ~CTR_EL0_DIC;
+
if (cii == 0) {
ctr_el0_usr = ctr_el0_cpu;
continue;
Index: src/sys/arch/arm/include/cputypes.h
diff -u src/sys/arch/arm/include/cputypes.h:1.12 src/sys/arch/arm/include/cputypes.h:1.13
--- src/sys/arch/arm/include/cputypes.h:1.12 Mon Jan 27 12:56:44 2020
+++ src/sys/arch/arm/include/cputypes.h Wed Jul 1 08:02:13 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cputypes.h,v 1.12 2020/01/27 12:56:44 skrll Exp $ */
+/* $NetBSD: cputypes.h,v 1.13 2020/07/01 08:02:13 ryo Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -198,6 +198,8 @@
#define CPU_ID_CORTEX_A76AE_P(n) ((n & 0xff0ff0f0) == 0x410fd0e0)
#define CPU_ID_CORTEX_A77_P(n) ((n & 0xff0ff0f0) == 0x410fd0f0)
+#define CPU_ID_NEOVERSEN1_P(n) ((n & 0xff0ffff0) == 0x410fd0c0)
+
#define CPU_ID_THUNDERXRX 0x43000a10
#define CPU_ID_THUNDERXP1d0 0x43000a10
#define CPU_ID_THUNDERXP1d1 0x43000a11
