Module Name: src
Committed By: simonb
Date: Fri Jul 17 08:06:02 UTC 2020
Modified Files:
src/sys/arch/mips/cavium/dev: octeon_xhci.c octeon_xhcireg.h
Log Message:
Don't use a reserved value for the USB endian CSR selects and
enable octxhci_uctl_init(). Between these, USB works without
needing a "usb start" from u-boot.
XXX: Note the port power enable goop is still disabled until
we get a GPIO driver.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/cavium/dev/octeon_xhci.c \
src/sys/arch/mips/cavium/dev/octeon_xhcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/cavium/dev/octeon_xhci.c
diff -u src/sys/arch/mips/cavium/dev/octeon_xhci.c:1.1 src/sys/arch/mips/cavium/dev/octeon_xhci.c:1.2
--- src/sys/arch/mips/cavium/dev/octeon_xhci.c:1.1 Thu Jul 16 21:34:52 2020
+++ src/sys/arch/mips/cavium/dev/octeon_xhci.c Fri Jul 17 08:06:02 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_xhci.c,v 1.1 2020/07/16 21:34:52 jmcneill Exp $ */
+/* $NetBSD: octeon_xhci.c,v 1.2 2020/07/17 08:06:02 simonb Exp $ */
/* $OpenBSD: octxhci.c,v 1.4 2019/09/29 04:32:23 visa Exp $ */
/*
@@ -151,7 +151,6 @@ octxhci_attach(device_t parent, device_t
if (strcmp(clock_type_hs, "pll_ref_clk") == 0)
clock_sel |= 2;
- if (0)
octxhci_uctl_init(osc, clock_freq, clock_sel);
if (octxhci_dwc3_init(sc) != 0) {
@@ -330,8 +329,8 @@ octxhci_uctl_init(struct octxhci_softc *
val = XCTL_RD_8(sc, XCTL_SHIM_CFG);
val &= ~XCTL_SHIM_CFG_CSR_BYTE_SWAP;
val &= ~XCTL_SHIM_CFG_DMA_BYTE_SWAP;
- val |= 3ull << XCTL_SHIM_CFG_CSR_BYTE_SWAP_SHIFT;
- val |= 1ull << XCTL_SHIM_CFG_DMA_BYTE_SWAP_SHIFT;
+ val |= __SHIFTIN(XCTL_SHIM_ENDIAN_BIG, XCTL_SHIM_CFG_DMA_BYTE_SWAP);
+ val |= __SHIFTIN(XCTL_SHIM_ENDIAN_BIG, XCTL_SHIM_CFG_CSR_BYTE_SWAP);
XCTL_WR_8(sc, XCTL_SHIM_CFG, val);
(void)XCTL_RD_8(sc, XCTL_SHIM_CFG);
}
Index: src/sys/arch/mips/cavium/dev/octeon_xhcireg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_xhcireg.h:1.1 src/sys/arch/mips/cavium/dev/octeon_xhcireg.h:1.2
--- src/sys/arch/mips/cavium/dev/octeon_xhcireg.h:1.1 Thu Jul 16 21:34:52 2020
+++ src/sys/arch/mips/cavium/dev/octeon_xhcireg.h Fri Jul 17 08:06:02 2020
@@ -59,6 +59,10 @@
#define XCTL_SHIM_CFG_DMA_BYTE_SWAP_SHIFT 8
#define XCTL_SHIM_CFG_CSR_BYTE_SWAP 0x0000000000000003ull
#define XCTL_SHIM_CFG_CSR_BYTE_SWAP_SHIFT 0
+#define XCTL_SHIM_ENDIAN_LITTLE 0 /* A-B-C-D-E-F-G-H -> A-B-C-D-E-F-G-H */
+#define XCTL_SHIM_ENDIAN_BIG 1 /* A-B-C-D-E-F-G-H -> H-G-F-E-D-C-B-A */
+#define XCTL_SHIM_ENDIAN_RSVD2 2 /* A-B-C-D-E-F-G-H -> D-C-B-A-H-G-F-E */
+#define XCTL_SHIM_ENDIAN_RSVD3 3 /* A-B-C-D-E-F-G-H -> E-F-G-H-A-B-C-D */
/*
* DWC3 core control registers.
