Module Name: src
Committed By: simonb
Date: Sun Jul 26 07:46:21 UTC 2020
Modified Files:
src/sys/arch/mips/cavium/dev: octeon_corereg.h
src/sys/arch/mips/include: cpuregs.h
Log Message:
Remove mostly duplicate MIPS spec CP0 regs from octeon_corereg.h, move
the Cavium specific CP0 regs to <mips/cpuregs.h> as done for other core
specific regs.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/cavium/dev/octeon_corereg.h
cvs rdiff -u -r1.102 -r1.103 src/sys/arch/mips/include/cpuregs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/cavium/dev/octeon_corereg.h
diff -u src/sys/arch/mips/cavium/dev/octeon_corereg.h:1.3 src/sys/arch/mips/cavium/dev/octeon_corereg.h:1.4
--- src/sys/arch/mips/cavium/dev/octeon_corereg.h:1.3 Mon Jun 22 03:05:07 2020
+++ src/sys/arch/mips/cavium/dev/octeon_corereg.h Sun Jul 26 07:46:21 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_corereg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $ */
+/* $NetBSD: octeon_corereg.h,v 1.4 2020/07/26 07:46:21 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -29,345 +29,10 @@
#ifndef _OCTEON_COREREG_H_
#define _OCTEON_COREREG_H_
-/*
- * Core Coprocessor 0 Privileged Registers.
- */
-
-#ifdef _LOCORE
-#define CP0_INDEX $0 /* Index Register */
-#define CP0_RANDOM $1 /* Random Register */
-#define CP0_ENTRYLO0 $2 /* EntryLo0 Registers */
-#define CP0_ENTRYLO1 $3 /* EntryLo1 Registers */
-#define CP0_CONTEXT $4 /* Context Register */
-#define CP0_PAGEMASK $5 /* PageMask Register */
-#define CP0_PAGEGRAIN $5, 1 /* PageGrain Register */
-#define CP0_WIRED $6 /* Wired Register */
-#define CP0_HWRENA $7 /* HWREna Register */
-#define CP0_BADVADDR $8 /* BadVAddr Register */
-#define CP0_COUNT $9 /* Count Register */
-#define CP0_ENTRYHI $10 /* EntryHi Register */
-#define CP0_COMPARE $11 /* Compare Register */
-#define CP0_STATUS $12 /* Status Register */
-#define CP0_INTCTL $12, 1 /* IntCtl Register */
-#define CP0_SRSCTL $12, 2 /* SRSCtl Register */
-#define CP0_CAUSE $13 /* Cause Register */
-#define CP0_EPC $14 /* Exception Program Counter */
-#define CP0_PRID $15 /* PRId Register */
-#define CP0_EBASE $15, 1 /* EBase Register */
-#define CP0_CONFIG $16 /* Config Register */
-#define CP0_CONFIG1 $16, 1 /* Config1 Register */
-#define CP0_CONFIG2 $16, 2 /* Config2 Register */
-#define CP0_CONFIG3 $16, 3 /* Config3 Register */
-#define CP0_WATCHLO $18 /* WatchLo Register */
-#define CP0_WATCHLO1 $18, 1
-#define CP0_WATCHHI $19 /* WatchHi Register */
-#define CP0_WATCHHI1 $19, 1
-#define CP0_XCONTEXT $20 /* XContext Register */
-#define CP0_DEBUG $23 /* Debug Register */
-#define CP0_DPC $24 /* Debug Exception Program Counter Register */
-#define CP0_PCCTL $25 /* Performance Counter Control Register */
-#define CP0_PCCTL1 $25, 2
-#define CP0_PCCNT $25, 1 /* Performance Counter Counter Register */
-#define CP0_PCCNT1 $25, 3
-#define CP0_ERROREPC $30 /* ErrorEPC */
-#define CP0_DESAVE $31 /* DESAVE Register */
-#define CP0_CACHEERRI $27 /* CacheErr (Icache) */
-#define CP0_CACHEERRD $27, 1 /* CacheErr (Dcache) */
-#define CP0_TAGLOI $28 /* TagLo Register (Icache) */
-#define CP0_TAGLOD $28, 2 /* TagLo Register (Dcache) */
-#define CP0_DATALOI $28, 1 /* DataLo Register (Icache) */
-#define CP0_DATALOD $28, 3 /* DataLo Register (Dcache) */
-#define CP0_TAGHI $29, 2 /* TagHi Register */
-#define CP0_DATAHII $29, 1 /* DataHi Register (Icache) */
-#define CP0_DATAHID $29, 3 /* DataHi Register (Dcache) */
-#define CP0_CVMCTL $9, 7 /* CvmCtl Register */
-#define CP0_CVMMEMCTL $11, 7 /* CvmMemCtl Register */
-#define CP0_CVMCNT $9, 6 /* CvmCount Register */
-#define CP0_MCD $22 /* Multi-Core Debug Register */
-#endif
-
/* ---- register bits */
-/* Index Register */
-
-#define CP0_INDEX_P UINT32_C(0x80000000)
-#define CP0_INDEX_XXX_30_5 0x7fffffe0
-#define CP0_INDEX_INDEX 0x0000001f
-
-/* Random Register */
-
-#define CP0_RANDOM_XXX_31_5 0xffffffe0
-#define CP0_RANDOM_RANDOM 0x0000001f
-
-/* EntryLo0, EntryLo1 Registers */
-
-#define CP0_ENTRYLON_FILL UINT64_C(0xfffff80000000000)
-#define CP0_ENTRYLON_PFNX UINT64_C(0x000007ffc0000000)
-#define CP0_ENTRYLON_PFN UINT64_C(0x000000003fffffc0)
-#define CP0_ENTRYLON_C UINT64_C(0x0000000000000038)
-#define CP0_ENTRYLON_D UINT64_C(0x0000000000000004)
-#define CP0_ENTRYLON_V UINT64_C(0x0000000000000002)
-#define CP0_ENTRYLON_G UINT64_C(0x0000000000000001)
-
-/* Context Register */
-
-#define CP0_CONTEXT_PTEBASE UINT64_C(0xffffffffff800000)
-#define CP0_CONTEXT_BADVPN2 UINT64_C(0x00000000007ffff0)
-#define CP0_CONTEXT_XXX_3_0 UINT64_C(0x000000000000000f)
-
-/* PageMask Register */
-
-#define CP0_PAGEMASK_XXX_31_29 UINT64_C(0xe000000000000000)
-#define CP0_PAGEMASK_MASK UINT64_C(0x1fffffffffffe000)
-#define CP0_PAGEMASK_MASKX UINT64_C(0x0000000000001800)
-#define CP0_PAGEMASK_XXX_10_0 UINT64_C(0x0000000000000fff)
-
-/* PageGrain Register */
-
-#define CP0_PAGEGRAIN_ASE 0xc0000000
-#define CP0_PAGEGRAIN_ELPA UINT32_C(0x20000000)
-#define CP0_PAGEGRAIN_ESP UINT32_C(0x10000000)
-#define CP0_PAGEGRAIN_XXX_27_13 0x0fffe000
-#define CP0_PAGEGRAIN_XXX_7_0 0x000000ff
-
-/* Wired Register */
-
-#define CP0_WIRED_XXX_31_5 UINT64_C(0xffffffffffffffe0)
-#define CP0_WIRED_WIRED UINT64_C(0x000000000000001f)
-
-/* HWREna Register */
-
-#define CP0_HWRENA_MASKX 0xc0000000
-#define CP0_HWRENA_XXX_29_4 0x3ffffff0
-#define CP0_HWRENA_MASK 0x0000000f
-
-/* BadVAddr Register */
-
-/* Count Register */
-
-/* EntryHi Register */
-
-#define CP0_ENTRYHI_R UINT64_C(0xc000000000000000)
-#define CP0_ENTRYHI_FILL UINT64_C(0x3ffe000000000000)
-#define CP0_ENTRYHI_VPN2 UINT64_C(0x0001ffffffffe000)
-#define CP0_ENTRYHI_VPN2X UINT64_C(0x0000000000001800)
-#define CP0_ENTRYHI_XXX_10_8 UINT64_C(0x0000000000000700)
-#define CP0_ENTRYHI_ASID UINT64_C(0x00000000000000ff)
-
-/* Compare Register */
-
-/* Status Register */
-
-#define CP0_STATUS_CU3 UINT32_C(0x80000000)
-#define CP0_STATUS_CU2 UINT32_C(0x40000000)
-#define CP0_STATUS_CU1 UINT32_C(0x20000000)
-#define CP0_STATUS_CU0 UINT32_C(0x10000000)
-#define CP0_STATUS_RP UINT32_C(0x08000000)
-#define CP0_STATUS_FR UINT32_C(0x04000000)
-#define CP0_STATUS_RE UINT32_C(0x02000000)
-#define CP0_STATUS_MX UINT32_C(0x01000000)
-#define CP0_STATUS_PX UINT32_C(0x00800000)
-#define CP0_STATUS_BEV UINT32_C(0x00400000)
-#define CP0_STATUS_TS UINT32_C(0x00200000)
-#define CP0_STATUS_SR UINT32_C(0x00100000)
-#define CP0_STATUS_NMI UINT32_C(0x00080000)
-#define CP0_STATUS_XXX_18_16 0x00070000
-#define CP0_STATUS_IM_7_4 0x0000fc00
-#define CP0_STATUS_IM_1_0 0x00000300
-#define CP0_STATUS_KX UINT32_C(0x00000080)
-#define CP0_STATUS_SX UINT32_C(0x00000040)
-#define CP0_STATUS_UX UINT32_C(0x00000020)
-#define CP0_STATUS_KSU 0x00000018
-#define CP0_STATUS_ERL UINT32_C(0x00000004)
-#define CP0_STATUS_EXL UINT32_C(0x00000002)
-#define CP0_STATUS_IE UINT32_C(0x00000001)
-
-/* IntCtl Register */
-
-#define CP0_INTCTL_IPTI 0xe0000000
-#define CP0_INTCTL_IPPCI 0x1c000000
-#define CP0_INTCTL_XXX_25_10 0x03fffc00
-#define CP0_INTCTL_VS 0x000003e0
-#define CP0_INTCTL_XXX_4_0 0x0000001f
-
-/* SRSCtl Register */
-
-#define CP0_SRSCTL_XXX_31_30 0xc0000000
-#define CP0_SRSCTL_HSS 0x3c000000
-#define CP0_SRSCTL_XXX_25_22 0x03c00000
-#define CP0_SRSCTL_EICSS 0x003c0000
-#define CP0_SRSCTL_XXX_17_16 0x00030000
-#define CP0_SRSCTL_ESS 0x0000f000
-#define CP0_SRSCTL_XXX_11_10 0x00000c00
-#define CP0_SRSCTL_EXL 0x000003c0
-#define CP0_SRSCTL_XXX_5_4 0x00000030
-#define CP0_SRSCTL_CSS 0x0000000f
-
-/* Cause Register */
-
-#define CP0_CAUSE_BD UINT32_C(0x80000000)
-#define CP0_CAUSE_TI UINT32_C(0x40000000)
-#define CP0_CAUSE_CE 0x30000000
-#define CP0_CAUSE_DC UINT32_C(0x08000000)
-#define CP0_CAUSE_PCI UINT32_C(0x04000000)
-#define CP0_CAUSE_XXX_25_24 0x03000000
-#define CP0_CAUSE_IV UINT32_C(0x00800000)
-#define CP0_CAUSE_WP UINT32_C(0x00400000)
-#define CP0_CAUSE_XXX_21_16 0x003f0000
-#define CP0_CAUSE_IP_7_4 0x0000f000
-#define CP0_CAUSE_IP_3_2 0x00000c00
-#define CP0_CAUSE_IP_1_0 0x00000300
-#define CP0_CAUSE_XXX_7 UINT32_C(0x00000080)
-#define CP0_CAUSE_EXCCODE 0x0000007c
-#define CP0_CAUSE_XXX_1_0 0x00000003
-
-/* Exception Program Counter */
-
-/* PRId Register */
-
-#define CP0_PRID_COMPANY_OPTIONS 0xff000000
-#define CP0_PRID_COMPANY_ID 0x00ff0000
-#define CP0_PRID_PROCESSOR_ID 0x0000ff00
-#define CP0_PRID_REVISION 0x000000ff
-
-/* EBase Register */
-
-#define CP0_EBASE_ALWAYS UINT32_C(0x80000000)
-#define CP0_EBASE_XXX_30 UINT32_C(0x40000000)
-#define CP0_EBASE_EXCEPTION_BASE 0x3ffff000
-#define CP0_EBASE_XXX_11_10 0x00000c00
-#define CP0_EBASE_CPU_NUM 0x000003ff
-
-/* Config Register */
-
-#define CP0_CONFIG_M UINT32_C(0x80000000)
-#define CP0_CONFIG_IMPL 0x7fff0000
-#define CP0_CONFIG_BE UINT32_C(0x00008000)
-#define CP0_CONFIG_AT 0x00006000
-#define CP0_CONFIG_AR 0x00001c00
-#define CP0_CONFIG_MT 0x00000380
-#define CP0_CONFIG_XXX_6_4 0x00000070
-#define CP0_CONFIG_VI UINT32_C(0x00000008)
-#define CP0_CONFIG_KO 0x00000007
-
-/* Config1 Register */
-
-#define CP0_CONFIG1_M UINT32_C(0x10000000)
-#define CP0_CONFIG1_MMUSIZE_1 0x7e000000
-#define CP0_CONFIG1_IS 0x01c00000
-#define CP0_CONFIG1_IL 0x00380000
-#define CP0_CONFIG1_IA 0x00070000
-#define CP0_CONFIG1_DS 0x0000e000
-#define CP0_CONFIG1_DL 0x00001c00
-#define CP0_CONFIG1_DA 0x00000380
-#define CP0_CONFIG1_C2 UINT32_C(0x00000040)
-#define CP0_CONFIG1_MD UINT32_C(0x00000020)
-#define CP0_CONFIG1_PC UINT32_C(0x00000010)
-#define CP0_CONFIG1_WR UINT32_C(0x00000008)
-#define CP0_CONFIG1_CA UINT32_C(0x00000004)
-#define CP0_CONFIG1_EP UINT32_C(0x00000002)
-#define CP0_CONFIG1_FP UINT32_C(0x00000001)
-
-/* Config2 Register */
-
-#define CP0_CONFIG2_M UINT32_C(0x80000000)
-#define CP0_CONFIG2_TU 0x70000000
-#define CP0_CONFIG2_TS 0x0f000000
-#define CP0_CONFIG2_TL 0x00f00000
-#define CP0_CONFIG2_TA 0x000f0000
-#define CP0_CONFIG2_SU 0x0000f000
-#define CP0_CONFIG2_SS 0x00000f00
-#define CP0_CONFIG2_SL 0x000000f0
-#define CP0_CONFIG2_SA 0x0000000f
-
-/* Config3 Register */
-
-#define CP0_CONFIG3_M UINT32_C(0x80000000)
-#define CP0_CONFIG3_XXX_30_8 0x7fffff00
-#define CP0_CONFIG3_LPA UINT32_C(0x00000080)
-#define CP0_CONFIG3_VEIC UINT32_C(0x00000040)
-#define CP0_CONFIG3_VINT UINT32_C(0x00000020)
-#define CP0_CONFIG3_SP UINT32_C(0x00000010)
-#define CP0_CONFIG3_XXX_3_2 0x0000000c
-#define CP0_CONFIG3_SM UINT32_C(0x00000002)
-#define CP0_CONFIG3_TL UINT32_C(0x00000001)
-
-/* WatchLo Register */
-
-#define CP0_WATCHLO_VADDR UINT64_C(0xfffffffffffffff8)
-#define CP0_WATCHLO_I UINT64_C(0x0000000000000004)
-#define CP0_WATCHLO_R UINT64_C(0x0000000000000002)
-#define CP0_WATCHLO_W UINT64_C(0x0000000000000001)
-
-/* WatchHi Register */
-
-#define CP0_WATCHHI_M UINT32_C(0x80000000)
-#define CP0_WATCHHI_G UINT32_C(0x40000000)
-#define CP0_WATCHHI_XXX_29_24 0x3f000000
-#define CP0_WATCHHI_ASID 0x00ff0000
-#define CP0_WATCHHI_XXX_15_12 0x0000f000
-#define CP0_WATCHHI_MASK 0x00000ff8
-#define CP0_WATCHHI_I UINT32_C(0x00000004)
-#define CP0_WATCHHI_R UINT32_C(0x00000002)
-#define CP0_WATCHHI_W UINT32_C(0x00000001)
-
-/* XContext Register */
-
-#define CP0_XCONTEXT_PTEBASE UINT64_C(0xfffffc0000000000)
-#define CP0_XCONTEXT_R UINT64_C(0x0000030000000000)
-#define CP0_XCONTEXT_BADVPN2 UINT64_C(0x000000fffffffff0)
-#define CP0_XCONTEXT_XXX_3_0 UINT64_C(0x000000000000000f)
-
-/* Debug Register */
-
-#define CP0_DEBUG_DBD UINT32_C(0x80000000)
-#define CP0_DEBUG_DM UINT32_C(0x40000000)
-#define CP0_DEBUG_NODCR UINT32_C(0x20000000)
-#define CP0_DEBUG_LSNM UINT32_C(0x10000000)
-#define CP0_DEBUG_DOZE UINT32_C(0x08000000)
-#define CP0_DEBUG_HALT UINT32_C(0x04000000)
-#define CP0_DEBUG_COUNTDM UINT32_C(0x02000000)
-#define CP0_DEBUG_IBUSEP UINT32_C(0x01000000)
-#define CP0_DEBUG_MCHECKP UINT32_C(0x00800000)
-#define CP0_DEBUG_CACHEEP UINT32_C(0x00400000)
-#define CP0_DEBUG_DBUSEP UINT32_C(0x00200000)
-#define CP0_DEBUG_IEXI UINT32_C(0x00100000)
-#define CP0_DEBUG_DDBSIMPR UINT32_C(0x00080000)
-#define CP0_DEBUG_DDBLIMPR UINT32_C(0x00040000)
-#define CP0_DEBUG_EJTAG 0x00038000
-#define CP0_DEBUG_DEXCCODE 0x00007c00
-#define CP0_DEBUG_NOSST UINT32_C(0x00000200)
-#define CP0_DEBUG_SST UINT32_C(0x00000100)
-#define CP0_DEBUG_XXX_7_6 0x000000c0
-#define CP0_DEBUG_DINT UINT32_C(0x00000020)
-#define CP0_DEBUG_DIB UINT32_C(0x00000010)
-#define CP0_DEBUG_DDBS UINT32_C(0x00000008)
-#define CP0_DEBUG_DDBL UINT32_C(0x00000004)
-#define CP0_DEBUG_DBP UINT32_C(0x00000002)
-#define CP0_DEBUG_DSS UINT32_C(0x00000001)
-
-/* Debug Exception Program Counter Register */
-
-/* Performance Counter Control Register */
-
-#define CP0_PCCTL_M UINT32_C(0x80000000)
-#define CP0_PCCTL_W UINT32_C(0x40000000)
-#define CP0_PCCTL_XXX_29_11 0x3ffff800
-#define CP0_PCCTL_EVENT 0x000007e0
-#define CP0_PCCTL_IE UINT32_C(0x00000010)
-#define CP0_PCCTL_U UINT32_C(0x00000008)
-#define CP0_PCCTL_S UINT32_C(0x00000004)
-#define CP0_PCCTL_K UINT32_C(0x00000002)
-#define CP0_PCCTL_EXL UINT32_C(0x00000001)
-
-/* Performance Counter Counter Register */
-
-/* ErrorEPC */
-
-/* DESAVE Register */
-
/*
- * Cavium Networks-Specific Coprocessor 0 Register
+ * Cavium Networks-Specific Coprocessor 0 Registers
*/
/* CacheErr (Icache) */
@@ -421,27 +86,6 @@
#define CP0_TAGLOD_G UINT64_C(0x0000000000000002)
#define CP0_TAGLOD_VALID UINT64_C(0x0000000000000001)
-/* DataLo Register (Icache) */
-
-/* DataLo Register (Dcache) */
-
-/* TagHi Register */
-
-#define CP0_TAGHI_XXX_63_36 UINT64_C(0xfffffff000000000)
-#define CP0_TAGHI_PTAG UINT64_C(0x0000000fffffff80)
-#define CP0_TAGHI_XXX_6_1 UINT64_C(0x000000000000007e)
-#define CP0_TAGHI_VALID UINT64_C(0x0000000000000001)
-
-/* DataHi Register (Icache) */
-
-#define CP0_DATAHII_XXX_63_8 UINT64_C(0xffffffffffffff00)
-#define CP0_DATAHII_PAR UINT64_C(0x00000000000000ff)
-
-/* DataHi Register (Dcache) */
-
-#define CP0_DATAHID_XXX_63_8 UINT64_C(0xffffffffffffff00)
-#define CP0_DATAHID_PAR UINT64_C(0x00000000000000ff)
-
/* CvmCtl Register */
#define CP0_CVMCTL_XXX_63_32 UINT64_C(0xffffffff00000000)
@@ -529,22 +173,8 @@
#define CP0_MCD_MCD1 UINT64_C(0x0000000000000002)
#define CP0_MCD_MCD0 UINT64_C(0x0000000000000001)
-/*
- * Core EJTAG DRSEG Registers
- */
-
-/* XXX */
-
-/*
- * Core EJTAG TAP Registers
- */
-
-/* XXX */
-
/* ---- operations */
-/* XXX */
-
/*
* OCTEON Configuration and Status Registers (CSRs)
*/
Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.102 src/sys/arch/mips/include/cpuregs.h:1.103
--- src/sys/arch/mips/include/cpuregs.h:1.102 Mon Jul 20 03:17:44 2020
+++ src/sys/arch/mips/include/cpuregs.h Sun Jul 26 07:46:21 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.102 2020/07/20 03:17:44 simonb Exp $ */
+/* $NetBSD: cpuregs.h,v 1.103 2020/07/26 07:46:21 simonb Exp $ */
/*
* Copyright (c) 2009 Miodrag Vallat.
@@ -498,13 +498,22 @@
* 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
* 4/2 MIPS_COP_0_USERLOCAL ..36 UserLocal.
* 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
- * 5/1 MIPS_COP_0_PG_GRAIN ..33 PageGrain register
+ * 5/1 MIPS_COP_0_PG_GRAIN ..33 PageGrain register.
+ * 5/5 MIPS_COP_0_PWBASE ..33 Page Walker Base register.
+ * 5/6 MIPS_COP_0_PWFIELD ..33 Page Walker Field register.
+ * 5/7 MIPS_COP_0_PWSIZE ..33 Page Walker Size register.
* 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
+ * 6/6 MIPS_COP_0_PWCTL ..33 Page Walker Control register.
+ * 6/6 MIPS_COP_0_EIRR ...6 [RMI] Extended Interrupt Request Register.
+ * 6/7 MIPS_COP_0_EIMR ...6 [RMI] Extended Interrupt Mask Register.
* 7 MIPS_COP_0_HWRENA ..33 rdHWR Enable.
* 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
* 9 MIPS_COP_0_COUNT .333 Count register.
+ * 9/6 MIPS_COP_0_CVMCNT ...6 [CAVIUM] CvmCtl register.
+ * 9/7 MIPS_COP_0_CVMCTL ...6 [CAVIUM] CvmCount register (64 bit).
* 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
* 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
+ * 11/7 MIPS_COP_0_CVMMEMCTL ...6 [CAVIUM] CvmMemCtl register.
* 12 MIPS_COP_0_STATUS 3333 Status register.
* 12/1 MIPS_COP_0_INTCTL ..33 Interrupt Control.
* 12/2 MIPS_COP_0_SRSCTL ..33 Shadow Register Set Selectors.
@@ -523,23 +532,32 @@
* 16/7 MIPS_COP_0_CONFIG7 ..33 Configuration register 7.
* 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
* 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
+ * 18/1 MIPS_COP_0_WATCH_LO2 ..ii WatchLo 1 register.
* 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
+ * 19/1 MIPS_COP_0_WATCH_HI1 ..ii WatchHi 1 register.
* 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
* 22 MIPS_COP_0_OSSCRATCH ...6 [RMI] OS Scratch register. (select 0..7)
* 22 MIPS_COP_0_DIAG ...6 [LOONGSON2] Diagnostic register.
+ * 22 MIPS_COP_0_MCD ...6 [CAVIUM] Multi-Core Debug register.
* 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
* 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
- * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
+ * 25/0 MIPS_COP_0_PERFCNT0_CTL ..ii Performance Counter 0 control register.
+ * 25/1 MIPS_COP_0_PERFCNT0_CNT ..ii Performance Counter 0 value register.
+ * 25/2 MIPS_COP_0_PERFCNT1_CTL ..ii Performance Counter 1 control register.
+ * 25/3 MIPS_COP_0_PERFCNT1_CNT ..ii Performance Counter 1 value register.
* 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
* 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
+ * 27 MIPS_COP_0_CACHE_ERR_I ...6 [CAVIUM] Cache Error register (instr).
+ * 27/1 MIPS_COP_0_CACHE_ERR_D ...6 [CAVIUM] Cache Error register (data).
+ * 27/1 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
* 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
* 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
* 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
* 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
* 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
* 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
- * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
- * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
+ * 29/2 MIPS_COP_0_TAG_HI_DATA ..ii Cache TagHi register (data).
+ * 29/3 MIPS_COP_0_DATA_HI_DATA ..ii Cache DataHi register (data).
* 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
* 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
*/
@@ -561,7 +579,6 @@
#define MIPS_COP_0_EXC_PC _(14)
#define MIPS_COP_0_PRID _(15)
-
/* MIPS-I */
#define MIPS_COP_0_TLB_LOW _(2)
@@ -578,12 +595,17 @@
#define MIPS_COP_0_CONFIG _(16)
#define MIPS_COP_0_LLADDR _(17)
#define MIPS_COP_0_WATCH_LO _(18)
+#define MIPS_COP_0_WATCH_LO1 _(18), 1 /* MIPS32/64 optional */
#define MIPS_COP_0_WATCH_HI _(19)
+#define MIPS_COP_0_WATCH_HI1 _(19), 1 /* MIPS32/64 optional */
#define MIPS_COP_0_TLB_XCONTEXT _(20)
#define MIPS_COP_0_ECC _(26)
#define MIPS_COP_0_CACHE_ERR _(27)
+#define MIPS_COP_0_CACHE_ERR_I _(27) /* CAVIUM */
+#define MIPS_COP_0_CACHE_ERR_D _(27), 1 /* CAVIUM */
#define MIPS_COP_0_TAG_LO _(28)
#define MIPS_COP_0_TAG_HI _(29)
+#define MIPS_COP_0_TAG_HI_DATA _(29), 2
#define MIPS_COP_0_ERROR_PC _(30)
/* MIPS32/64 */
@@ -599,9 +621,14 @@
#define MIPS_COP_0_PWFIELD _(5), 6
#define MIPS_COP_0_PWSIZE _(5), 7
#define MIPS_COP_0_PWCTL _(6), 6
+#define MIPS_COP_0_EIRR _(6), 6 /* RMI */
+#define MIPS_COP_0_EIMR _(6), 7 /* RMI */
#define MIPS_COP_0_HWRENA _(7)
#define MIPS_COP_0_BADINSTR _(8), 1
#define MIPS_COP_0_BADINSTRP _(8), 2
+#define MIPS_COP_0_CVMCNT _(9), 6 /* CAVIUM */
+#define MIPS_COP_0_CVMCTL _(9), 7 /* CAVIUM */
+#define MIPS_COP_0_CVMMEMCTL _(11), 7 /* CAVIUM */
#define MIPS_COP_0_INTCTL _(12), 1
#define MIPS_COP_0_SRSCTL _(12), 2
#define MIPS_COP_0_SRSMAP _(12), 3
@@ -616,12 +643,17 @@
#define MIPS_COP_0_CONFIG4 _(16), 4
#define MIPS_COP_0_CONFIG5 _(16), 5
#define MIPS_COP_0_OSSCRATCH _(22) /* RMI */
-#define MIPS_COP_0_DIAG _(22)
+#define MIPS_COP_0_DIAG _(22) /* LOONGSON2 */
+#define MIPS_COP_0_MCD _(22) /* CAVIUM */
#define MIPS_COP_0_DEBUG _(23)
#define MIPS_COP_0_DEPC _(24)
-#define MIPS_COP_0_PERFCNT _(25)
-#define MIPS_COP_0_DATA_LO _(28)
-#define MIPS_COP_0_DATA_HI _(29)
+#define MIPS_COP_0_PERFCNT0_CTL _(25)
+#define MIPS_COP_0_PERFCNT0_CNT _(25), 1
+#define MIPS_COP_0_PERFCNT1_CTL _(25), 2
+#define MIPS_COP_0_PERFCNT1_CNT _(25), 3
+#define MIPS_COP_0_DATA_LO _(28), 1
+#define MIPS_COP_0_DATA_HI _(29), 3
+#define MIPS_COP_0_DATA_HI_DATA _(29)
#define MIPS_COP_0_DESAVE _(31)
#define MIPS_DIAG_RAS_DISABLE 0x00000001 /* Loongson2 */
