Module Name: src
Committed By: martin
Date: Wed Aug 5 18:26:17 UTC 2020
Modified Files:
src/sys/arch/x86/include [netbsd-8]: specialreg.h
Log Message:
Accidently not commited for ticket #1595:
sys/arch/x86/include/specialreg.h 1.129 via patch
Add six errata for AMD Family 17h (Ryzen etc).
To generate a diff of this commit:
cvs rdiff -u -r1.98.2.20 -r1.98.2.21 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.98.2.20 src/sys/arch/x86/include/specialreg.h:1.98.2.21
--- src/sys/arch/x86/include/specialreg.h:1.98.2.20 Wed Aug 5 16:02:53 2020
+++ src/sys/arch/x86/include/specialreg.h Wed Aug 5 18:26:17 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.98.2.20 2020/08/05 16:02:53 martin Exp $ */
+/* $NetBSD: specialreg.h,v 1.98.2.21 2020/08/05 18:26:17 martin Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -1055,6 +1055,9 @@
#define NB_CFG_INITAPICCPUIDLO (1ULL << 54)
#define MSR_LS_CFG 0xc0011020
+#define LS_CFG_ERRATA_1033 __BIT(4)
+#define LS_CFG_ERRATA_793 __BIT(15)
+#define LS_CFG_ERRATA_1095 __BIT(57)
#define LS_CFG_DIS_LS2_SQUISH 0x02000000
#define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL
#define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL
@@ -1063,6 +1066,7 @@
#define MSR_IC_CFG 0xc0011021
#define IC_CFG_DIS_SEQ_PREFETCH 0x00000800
#define IC_CFG_DIS_IND 0x00004000
+#define IC_CFG_ERRATA_776 __BIT(26)
#define MSR_DC_CFG 0xc0011022
#define DC_CFG_DIS_CNV_WC_SSO 0x00000008
@@ -1077,9 +1081,16 @@
#define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
#define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL
+#define MSR_FP_CFG 0xc0011028
+#define FP_CFG_ERRATA_1049 __BIT(4)
+
#define MSR_DE_CFG 0xc0011029
#define DE_CFG_ERRATA_721 0x00000001
#define DE_CFG_LFENCE_SERIALIZE __BIT(1)
+#define DE_CFG_ERRATA_1021 __BIT(13)
+
+#define MSR_LS_CFG2 0xc001102d
+#define LS_CFG2_ERRATA_1091 __BIT(34)
/* AMD Family10h MSRs */
#define MSR_OSVW_ID_LENGTH 0xc0010140
