Module Name: src
Committed By: jmcneill
Date: Mon Aug 17 21:00:29 UTC 2020
Modified Files:
src/sys/arch/mips/cavium: octeon_intr.c
Log Message:
IPI_SHOOTDOWN needs to be IPL_SCHED. Spotted by nick.
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/mips/cavium/octeon_intr.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/cavium/octeon_intr.c
diff -u src/sys/arch/mips/cavium/octeon_intr.c:1.22 src/sys/arch/mips/cavium/octeon_intr.c:1.23
--- src/sys/arch/mips/cavium/octeon_intr.c:1.22 Wed Aug 5 04:47:35 2020
+++ src/sys/arch/mips/cavium/octeon_intr.c Mon Aug 17 21:00:29 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_intr.c,v 1.22 2020/08/05 04:47:35 simonb Exp $ */
+/* $NetBSD: octeon_intr.c,v 1.23 2020/08/17 21:00:29 jmcneill Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
@@ -44,7 +44,7 @@
#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.22 2020/08/05 04:47:35 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_intr.c,v 1.23 2020/08/17 21:00:29 jmcneill Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -173,12 +173,33 @@ static struct octeon_intrhand ipi_intrha
.ih_irq = CIU_INT_MBOX_15_0,
.ih_ipl = IPL_HIGH,
},
+ [1] = {
+ .ih_func = octeon_ipi_intr,
+ .ih_arg = (void *)(uintptr_t)__BITS(31,16),
+ .ih_irq = CIU_INT_MBOX_31_16,
+ .ih_ipl = IPL_SCHED,
+ },
};
+
+static int ipi_prio[NIPIS] = {
+ [IPI_NOP] = IPL_HIGH,
+ [IPI_AST] = IPL_HIGH,
+ [IPI_SHOOTDOWN] = IPL_SCHED,
+ [IPI_SYNCICACHE] = IPL_HIGH,
+ [IPI_KPREEMPT] = IPL_HIGH,
+ [IPI_SUSPEND] = IPL_HIGH,
+ [IPI_HALT] = IPL_HIGH,
+ [IPI_XCALL] = IPL_HIGH,
+ [IPI_GENERIC] = IPL_HIGH,
+ [IPI_WDOG] = IPL_HIGH,
+};
+
#endif
static struct octeon_intrhand *octciu_intrs[NIRQS] = {
#ifdef MULTIPROCESSOR
[CIU_INT_MBOX_15_0] = &ipi_intrhands[0],
+ [CIU_INT_MBOX_31_16] = &ipi_intrhands[1],
#endif
};
@@ -256,6 +277,7 @@ octeon_intr_init(struct cpu_info *ci)
#ifdef MULTIPROCESSOR
// Enable the IPIs
cpu->cpu_ip4_enable[0] |= __BIT(CIU_INT_MBOX_15_0);
+ cpu->cpu_ip3_enable[0] |= __BIT(CIU_INT_MBOX_31_16);
#endif
if (ci->ci_dev) {
@@ -514,10 +536,11 @@ octeon_ipi_intr(void *arg)
{
struct cpu_info * const ci = curcpu();
struct cpu_softc * const cpu = ci->ci_softc;
- uint32_t ipi_mask = (uintptr_t) arg;
+ const uint32_t mbox_mask = (uintptr_t) arg;
+ uint32_t ipi_mask = mbox_mask;
- KASSERTMSG(ci->ci_cpl == IPL_HIGH,
- "ipi_mask %#"PRIx32" cpl %d", ipi_mask, ci->ci_cpl);
+ KASSERTMSG((mbox_mask & __BITS(31,16)) == 0 || ci->ci_cpl >= IPL_SCHED,
+ "mbox_mask %#"PRIx32" cpl %d", mbox_mask, ci->ci_cpl);
ipi_mask &= mips3_ld(cpu->cpu_mbox_set);
if (ipi_mask == 0)
@@ -525,7 +548,7 @@ octeon_ipi_intr(void *arg)
mips3_sd(cpu->cpu_mbox_clr, ipi_mask);
- KASSERT(ipi_mask < __BIT(NIPIS));
+ KASSERT(__SHIFTOUT(ipi_mask, mbox_mask) < __BIT(NIPIS));
#if NWDOG > 0
// Handle WDOG requests ourselves.
@@ -546,7 +569,7 @@ octeon_ipi_intr(void *arg)
atomic_or_64(&ci->ci_active_ipis, ipi_mask);
atomic_and_64(&ci->ci_request_ipis, ~ipi_mask);
- ipi_process(ci, ipi_mask);
+ ipi_process(ci, __SHIFTOUT(ipi_mask, mbox_mask));
atomic_and_64(&ci->ci_active_ipis, ~ipi_mask);
@@ -571,7 +594,8 @@ octeon_send_ipi(struct cpu_info *ci, int
return -1;
struct cpu_softc * const cpu = ci->ci_softc;
- const uint32_t ipi_mask = __BIT(req);
+ const u_int ipi_shift = ipi_prio[req] == IPL_SCHED ? 16 : 0;
+ const uint32_t ipi_mask = __BIT(req + ipi_shift);
atomic_or_64(&ci->ci_request_ipis, ipi_mask);
