Module Name: src
Committed By: martin
Date: Sun Sep 13 11:54:10 UTC 2020
Modified Files:
src/sys/dev/nvmm/x86 [netbsd-9]: nvmm_x86.c nvmm_x86_svm.c
nvmm_x86_vmx.c
Log Message:
Pull up following revision(s) (requested by maxv in ticket #1077):
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.68
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.74
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.16
Improve emulation of MSR_IA32_ARCH_CAPABILITIES: publish only the *_NO
bits. Initially they were the only ones there, but Intel then added other
bits we aren't interested in, and they must be filtered out.
nvmm-x86-svm: improve the handling of MSR_EFER
Intercept reads of it as well, just to mask EFER_SVME, which the guest
doesn't need to see.
nvmm-x86: improve the CPUID emulation
- Mask DTES64, DS_CPL, CID, SDBG, xTPR, PN.
- B10, B20 and IA64 do not exist, so just remove them.
To generate a diff of this commit:
cvs rdiff -u -r1.7.4.5 -r1.7.4.6 src/sys/dev/nvmm/x86/nvmm_x86.c
cvs rdiff -u -r1.46.4.11 -r1.46.4.12 src/sys/dev/nvmm/x86/nvmm_x86_svm.c
cvs rdiff -u -r1.36.2.13 -r1.36.2.14 src/sys/dev/nvmm/x86/nvmm_x86_vmx.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/nvmm/x86/nvmm_x86.c
diff -u src/sys/dev/nvmm/x86/nvmm_x86.c:1.7.4.5 src/sys/dev/nvmm/x86/nvmm_x86.c:1.7.4.6
--- src/sys/dev/nvmm/x86/nvmm_x86.c:1.7.4.5 Sat Aug 29 17:00:28 2020
+++ src/sys/dev/nvmm/x86/nvmm_x86.c Sun Sep 13 11:54:10 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86.c,v 1.7.4.5 2020/08/29 17:00:28 martin Exp $ */
+/* $NetBSD: nvmm_x86.c,v 1.7.4.6 2020/09/13 11:54:10 martin Exp $ */
/*
* Copyright (c) 2018-2020 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.7.4.5 2020/08/29 17:00:28 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.7.4.6 2020/09/13 11:54:10 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -235,19 +235,19 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
.ecx =
CPUID2_SSE3 |
CPUID2_PCLMUL |
- CPUID2_DTES64 |
+ /* CPUID2_DTES64 excluded */
/* CPUID2_MONITOR excluded */
- CPUID2_DS_CPL |
+ /* CPUID2_DS_CPL excluded */
/* CPUID2_VMX excluded */
/* CPUID2_SMX excluded */
/* CPUID2_EST excluded */
/* CPUID2_TM2 excluded */
CPUID2_SSSE3 |
- CPUID2_CID |
- CPUID2_SDBG |
+ /* CPUID2_CID excluded */
+ /* CPUID2_SDBG excluded */
CPUID2_FMA |
CPUID2_CX16 |
- CPUID2_xTPR |
+ /* CPUID2_xTPR excluded */
/* CPUID2_PDCM excluded */
/* CPUID2_PCID excluded, but re-included in VMX */
/* CPUID2_DCA excluded */
@@ -275,7 +275,6 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
/* CPUID_MCE excluded */
CPUID_CX8 |
CPUID_APIC |
- CPUID_B10 |
CPUID_SEP |
/* CPUID_MTRR excluded */
CPUID_PGE |
@@ -283,9 +282,8 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
CPUID_CMOV |
CPUID_PAT |
CPUID_PSE36 |
- CPUID_PN |
+ /* CPUID_PN excluded */
CPUID_CFLUSH |
- CPUID_B20 |
/* CPUID_DS excluded */
/* CPUID_ACPI excluded */
CPUID_MMX |
@@ -295,7 +293,6 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
CPUID_SS |
CPUID_HTT |
/* CPUID_TM excluded */
- CPUID_IA64 |
CPUID_SBF
};
Index: src/sys/dev/nvmm/x86/nvmm_x86_svm.c
diff -u src/sys/dev/nvmm/x86/nvmm_x86_svm.c:1.46.4.11 src/sys/dev/nvmm/x86/nvmm_x86_svm.c:1.46.4.12
--- src/sys/dev/nvmm/x86/nvmm_x86_svm.c:1.46.4.11 Fri Sep 4 18:53:43 2020
+++ src/sys/dev/nvmm/x86/nvmm_x86_svm.c Sun Sep 13 11:54:10 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86_svm.c,v 1.46.4.11 2020/09/04 18:53:43 martin Exp $ */
+/* $NetBSD: nvmm_x86_svm.c,v 1.46.4.12 2020/09/13 11:54:10 martin Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.46.4.11 2020/09/04 18:53:43 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.46.4.12 2020/09/13 11:54:10 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -1142,6 +1142,12 @@ svm_inkernel_handle_msr(struct nvmm_mach
size_t i;
if (exit->reason == NVMM_VCPU_EXIT_RDMSR) {
+ if (exit->u.rdmsr.msr == MSR_EFER) {
+ val = vmcb->state.efer & ~EFER_SVME;
+ vmcb->state.rax = (val & 0xFFFFFFFF);
+ cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32);
+ goto handled;
+ }
if (exit->u.rdmsr.msr == MSR_NB_CFG) {
val = NB_CFG_INITAPICCPUIDLO;
vmcb->state.rax = (val & 0xFFFFFFFF);
@@ -2169,7 +2175,6 @@ svm_vcpu_init(struct nvmm_machine *mach,
/* Allow direct access to certain MSRs. */
memset(cpudata->msrbm, 0xFF, MSRBM_SIZE);
- svm_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, false);
svm_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true);
svm_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true);
svm_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true);
Index: src/sys/dev/nvmm/x86/nvmm_x86_vmx.c
diff -u src/sys/dev/nvmm/x86/nvmm_x86_vmx.c:1.36.2.13 src/sys/dev/nvmm/x86/nvmm_x86_vmx.c:1.36.2.14
--- src/sys/dev/nvmm/x86/nvmm_x86_vmx.c:1.36.2.13 Fri Sep 4 18:53:43 2020
+++ src/sys/dev/nvmm/x86/nvmm_x86_vmx.c Sun Sep 13 11:54:10 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86_vmx.c,v 1.36.2.13 2020/09/04 18:53:43 martin Exp $ */
+/* $NetBSD: nvmm_x86_vmx.c,v 1.36.2.14 2020/09/13 11:54:10 martin Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_vmx.c,v 1.36.2.13 2020/09/04 18:53:43 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_vmx.c,v 1.36.2.14 2020/09/13 11:54:10 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -1753,6 +1753,24 @@ vmx_inkernel_handle_msr(struct nvmm_mach
cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32);
goto handled;
}
+ if (exit->u.rdmsr.msr == MSR_IA32_ARCH_CAPABILITIES) {
+ u_int descs[4];
+ if (cpuid_level < 7) {
+ goto error;
+ }
+ x86_cpuid(7, descs);
+ if (!(descs[3] & CPUID_SEF_ARCH_CAP)) {
+ goto error;
+ }
+ val = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
+ val &= (IA32_ARCH_RDCL_NO |
+ IA32_ARCH_SSB_NO |
+ IA32_ARCH_MDS_NO |
+ IA32_ARCH_TAA_NO);
+ cpudata->gprs[NVMM_X64_GPR_RAX] = (val & 0xFFFFFFFF);
+ cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32);
+ goto handled;
+ }
for (i = 0; i < __arraycount(msr_ignore_list); i++) {
if (msr_ignore_list[i] != exit->u.rdmsr.msr)
continue;
@@ -2786,8 +2804,6 @@ vmx_vcpu_init(struct nvmm_machine *mach,
vmx_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true);
vmx_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true);
vmx_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false);
- vmx_vcpu_msr_allow(cpudata->msrbm, MSR_IA32_ARCH_CAPABILITIES,
- true, false);
vmx_vmwrite(VMCS_MSR_BITMAP, (uint64_t)cpudata->msrbm_pa);
/*
