Module Name: src
Committed By: martin
Date: Wed Sep 23 08:46:54 UTC 2020
Modified Files:
src/sys/dev/mii [netbsd-9]: inbmphyreg.h
src/sys/dev/pci [netbsd-9]: if_wm.c if_wmreg.h if_wmvar.h
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1093):
sys/dev/pci/if_wmreg.h: revision 1.120
sys/dev/pci/if_wmvar.h: revision 1.46
sys/dev/pci/if_wm.c: revision 1.686
sys/dev/pci/if_wm.c: revision 1.687
sys/dev/mii/inbmphyreg.h: revision 1.20
sys/dev/pci/if_wm.c: revision 1.688
sys/dev/pci/if_wm.c: revision 1.689
s/ressource/resource/. Found by knakahara.
Add new flag named WM_F_CRC_STRIP and use it. No functional change.
This change also sets the RCTL_SECRC bit on I211 but it doesn't change
the behavior because I211 always strips CRC like I35[04] and I210.
Add a workaround for jumbo frame on PCH2 and newer. Tested by chs@.
- Add wm_lv_jumbo_workaround_ich8lan() and use it. From FreeBSD.
XXX For KUMCTRLSTA_OFFSET_HD_CTRL register modification, it's doubtful.
FreeBSD and Linux do the same thing that they set the same value on both
jumbo frame's enable case and the disable case. It seems the default value
is 0x0b0c and it's not changed on the enable case, so it might be a bug
on the enable case or the modification is not required.
- Rename I219_UNKNOWN1 to I82579_UNKNOWN1.
Use 12K for packet buffer for jumbo frame on PCH2 and newer.
XXX Note that Linux Use 14K.
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.18.4.1 src/sys/dev/mii/inbmphyreg.h
cvs rdiff -u -r1.645.2.6 -r1.645.2.7 src/sys/dev/pci/if_wm.c
cvs rdiff -u -r1.115.2.2 -r1.115.2.3 src/sys/dev/pci/if_wmreg.h
cvs rdiff -u -r1.44.4.1 -r1.44.4.2 src/sys/dev/pci/if_wmvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/mii/inbmphyreg.h
diff -u src/sys/dev/mii/inbmphyreg.h:1.18 src/sys/dev/mii/inbmphyreg.h:1.18.4.1
--- src/sys/dev/mii/inbmphyreg.h:1.18 Thu Jan 31 15:30:23 2019
+++ src/sys/dev/mii/inbmphyreg.h Wed Sep 23 08:46:54 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: inbmphyreg.h,v 1.18 2019/01/31 15:30:23 msaitoh Exp $ */
+/* $NetBSD: inbmphyreg.h,v 1.18.4.1 2020/09/23 08:46:54 martin Exp $ */
/*******************************************************************************
Copyright (c) 2001-2015, Intel Corporation
All rights reserved.
@@ -136,6 +136,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define BM_PORT_GEN_CFG BME1000_REG(BM_PORT_CTRL_PAGE, 17)
+#define I82579_DFT_CTRL BME1000_REG(BM_PORT_CTRL_PAGE, 20)
+
#define CV_SMB_CTRL BME1000_REG(BM_PORT_CTRL_PAGE, 23)
#define CV_SMB_CTRL_FORCE_SMBUS __BIT(0)
@@ -180,7 +182,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define HV_MUX_DATA_CTRL_FORCE_SPEED (1 << 2)
#define HV_MUX_DATA_CTRL_GEN_TO_MAC (1 << 10)
-#define I219_UNKNOWN1 BME1000_REG(776, 20)
+#define I82579_UNKNOWN1 BME1000_REG(776, 20)
+#define I82579_TX_PTR_GAP 0x1f
#define I218_ULP_CONFIG1 BME1000_REG(779, 16)
#define I218_ULP_CONFIG1_START __BIT(0)
Index: src/sys/dev/pci/if_wm.c
diff -u src/sys/dev/pci/if_wm.c:1.645.2.6 src/sys/dev/pci/if_wm.c:1.645.2.7
--- src/sys/dev/pci/if_wm.c:1.645.2.6 Wed Aug 5 15:14:18 2020
+++ src/sys/dev/pci/if_wm.c Wed Sep 23 08:46:54 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.645.2.6 2020/08/05 15:14:18 martin Exp $ */
+/* $NetBSD: if_wm.c,v 1.645.2.7 2020/09/23 08:46:54 martin Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -82,7 +82,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.645.2.6 2020/08/05 15:14:18 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.645.2.7 2020/09/23 08:46:54 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -1015,6 +1015,8 @@ static int wm_kmrn_lock_loss_workaround_
static void wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
static int wm_hv_phy_workarounds_ich8lan(struct wm_softc *);
static void wm_copy_rx_addrs_to_phy_ich8lan(struct wm_softc *);
+static void wm_copy_rx_addrs_to_phy_ich8lan_locked(struct wm_softc *);
+static int wm_lv_jumbo_workaround_ich8lan(struct wm_softc *, bool);
static int wm_lv_phy_workarounds_ich8lan(struct wm_softc *);
static int wm_k1_workaround_lpt_lp(struct wm_softc *, bool);
static int wm_k1_gig_workaround_hv(struct wm_softc *, int);
@@ -2885,6 +2887,14 @@ alloc_retry:
sc->sc_flags |= WM_F_EEE;
}
+ /*
+ * The I350 has a bug where it always strips the CRC whether
+ * asked to or not. So ask for stripped CRC here and cope in rxeof
+ */
+ if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
+ || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
+ sc->sc_flags |= WM_F_CRC_STRIP;
+
/* Set device properties (macflags) */
prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags);
@@ -3791,7 +3801,7 @@ wm_set_filter(struct wm_softc *sc)
struct ether_multistep step;
bus_addr_t mta_reg;
uint32_t hash, reg, bit;
- int i, size, ralmax;
+ int i, size, ralmax, rv;
DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
device_xname(sc->sc_dev), __func__));
@@ -3917,6 +3927,17 @@ wm_set_filter(struct wm_softc *sc)
sc->sc_rctl |= RCTL_MPE;
setit:
+ if (sc->sc_type >= WM_T_PCH2) {
+ if (((ec->ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
+ && (ifp->if_mtu > ETHERMTU))
+ rv = wm_lv_jumbo_workaround_ich8lan(sc, true);
+ else
+ rv = wm_lv_jumbo_workaround_ich8lan(sc, false);
+ if (rv != 0)
+ device_printf(sc->sc_dev,
+ "Failed to do workaround for jumbo frame.\n");
+ }
+
CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
}
@@ -4849,7 +4870,8 @@ wm_reset(struct wm_softc *sc)
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
case WM_T_PCH_CNP:
- sc->sc_pba = PBA_26K;
+ sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 1500 ?
+ PBA_12K : PBA_26K;
break;
default:
sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
@@ -6308,12 +6330,7 @@ wm_init_locked(struct ifnet *ifp)
if (sc->sc_type == WM_T_82574)
sc->sc_rctl |= RCTL_DTYP_ONEBUF;
- /*
- * The I350 has a bug where it always strips the CRC whether
- * asked to or not. So ask for stripped CRC here and cope in rxeof
- */
- if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
- || (sc->sc_type == WM_T_I210))
+ if ((sc->sc_flags & WM_F_CRC_STRIP) != 0)
sc->sc_rctl |= RCTL_SECRC;
if (((ec->ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
@@ -9069,17 +9086,16 @@ wm_rxeof(struct wm_rxqueue *rxq, u_int l
/*
* Okay, we have the entire packet now. The chip is
- * configured to include the FCS except I350 and I21[01]
- * (not all chips can be configured to strip it),
- * so we need to trim it.
+ * configured to include the FCS except I35[05], I21[01].
+ * (not all chips can be configured to strip it), so we need
+ * to trim it. Those chips have an eratta, the RCTL_SECRC bit
+ * in RCTL register is always set, so we don't trim it.
+ * PCH2 and newer chip also not include FCS when jumbo
+ * frame is used to do workaround an errata.
* May need to adjust length of previous mbuf in the
* chain if the current mbuf is too short.
- * For an eratta, the RCTL_SECRC bit in RCTL register
- * is always set in I350, so we don't trim it.
*/
- if ((sc->sc_type != WM_T_I350) && (sc->sc_type != WM_T_I354)
- && (sc->sc_type != WM_T_I210)
- && (sc->sc_type != WM_T_I211)) {
+ if ((sc->sc_flags & WM_F_CRC_STRIP) == 0) {
if (m->m_len < ETHER_CRC_LEN) {
rxq->rxq_tail->m_len
-= (ETHER_CRC_LEN - m->m_len);
@@ -9319,7 +9335,7 @@ wm_linkintr_gmii(struct wm_softc *sc, ui
return;
rv = sc->phy.readreg_locked(dev, 2,
- I219_UNKNOWN1, &data);
+ I82579_UNKNOWN1, &data);
if (rv) {
sc->phy.release(sc);
return;
@@ -9330,7 +9346,7 @@ wm_linkintr_gmii(struct wm_softc *sc, ui
data &= ~(0x3ff << 2);
data |= (0x18 << 2);
rv = sc->phy.writereg_locked(dev,
- 2, I219_UNKNOWN1, data);
+ 2, I82579_UNKNOWN1, data);
}
sc->phy.release(sc);
if (rv)
@@ -9341,7 +9357,7 @@ wm_linkintr_gmii(struct wm_softc *sc, ui
return;
rv = sc->phy.writereg_locked(dev, 2,
- I219_UNKNOWN1, 0xc023);
+ I82579_UNKNOWN1, 0xc023);
sc->phy.release(sc);
if (rv)
return;
@@ -10984,7 +11000,7 @@ wm_gmii_i82544_writereg_locked(device_t
*
* Read a PHY register on the kumeran
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_i80003_readreg(device_t dev, int phy, int reg, uint16_t *val)
@@ -11043,7 +11059,7 @@ out:
*
* Write a PHY register on the kumeran.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_i80003_writereg(device_t dev, int phy, int reg, uint16_t val)
@@ -11101,7 +11117,7 @@ out:
*
* Read a PHY register on the kumeran
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_bm_readreg(device_t dev, int phy, int reg, uint16_t *val)
@@ -11148,7 +11164,7 @@ release:
*
* Write a PHY register on the kumeran.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_bm_writereg(device_t dev, int phy, int reg, uint16_t val)
@@ -11359,7 +11375,7 @@ wm_access_phy_wakeup_reg_bm(device_t dev
*
* Read a PHY register on the kumeran
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_hv_readreg(device_t dev, int phy, int reg, uint16_t *val)
@@ -11423,7 +11439,7 @@ wm_gmii_hv_readreg_locked(device_t dev,
*
* Write a PHY register on the kumeran.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_hv_writereg(device_t dev, int phy, int reg, uint16_t val)
@@ -11509,7 +11525,7 @@ wm_gmii_hv_writereg_locked(device_t dev,
*
* Read a PHY register on the 82580 and I350.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_82580_readreg(device_t dev, int phy, int reg, uint16_t *val)
@@ -11540,7 +11556,7 @@ wm_gmii_82580_readreg(device_t dev, int
*
* Write a PHY register on the 82580 and I350.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_82580_writereg(device_t dev, int phy, int reg, uint16_t val)
@@ -11571,7 +11587,7 @@ wm_gmii_82580_writereg(device_t dev, int
*
* Read a PHY register on the I2100 and I211.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_gs40g_readreg(device_t dev, int phy, int reg, uint16_t *val)
@@ -11606,7 +11622,7 @@ release:
*
* Write a PHY register on the I210 and I211.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_gs40g_writereg(device_t dev, int phy, int reg, uint16_t val)
@@ -11893,7 +11909,7 @@ wm_sgmii_sfp_preconfig(struct wm_softc *
*
* Read a PHY register on the SGMII
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_sgmii_readreg(device_t dev, int phy, int reg, uint16_t *val)
@@ -11950,7 +11966,7 @@ wm_sgmii_readreg_locked(device_t dev, in
*
* Write a PHY register on the SGMII.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_sgmii_writereg(device_t dev, int phy, int reg, uint16_t val)
@@ -15904,18 +15920,31 @@ release:
static void
wm_copy_rx_addrs_to_phy_ich8lan(struct wm_softc *sc)
{
+
+ DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
+ device_xname(sc->sc_dev), __func__));
+
+ if (sc->phy.acquire(sc) != 0)
+ return;
+
+ wm_copy_rx_addrs_to_phy_ich8lan_locked(sc);
+
+ sc->phy.release(sc);
+}
+
+static void
+wm_copy_rx_addrs_to_phy_ich8lan_locked(struct wm_softc *sc)
+{
device_t dev = sc->sc_dev;
uint32_t mac_reg;
uint16_t i, wuce;
int count;
DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
- device_xname(sc->sc_dev), __func__));
+ device_xname(dev), __func__));
- if (sc->phy.acquire(sc) != 0)
- return;
if (wm_enable_phy_wakeup_reg_access_bm(dev, &wuce) != 0)
- goto release;
+ return;
/* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
count = wm_rar_count(sc);
@@ -15935,9 +15964,182 @@ wm_copy_rx_addrs_to_phy_ich8lan(struct w
}
wm_disable_phy_wakeup_reg_access_bm(dev, &wuce);
+}
-release:
+/*
+ * wm_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
+ * with 82579 PHY
+ * @enable: flag to enable/disable workaround when enabling/disabling jumbos
+ */
+static int
+wm_lv_jumbo_workaround_ich8lan(struct wm_softc *sc, bool enable)
+{
+ device_t dev = sc->sc_dev;
+ int rar_count;
+ int rv;
+ uint32_t mac_reg;
+ uint16_t dft_ctrl, data;
+ uint16_t i;
+
+ DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
+ device_xname(dev), __func__));
+
+ if (sc->sc_type < WM_T_PCH2)
+ return 0;
+
+ /* Acquire PHY semaphore */
+ rv = sc->phy.acquire(sc);
+ if (rv != 0)
+ return rv;
+
+ /* Disable Rx path while enabling/disabling workaround */
+ sc->phy.readreg_locked(dev, 2, I82579_DFT_CTRL, &dft_ctrl);
+ if (rv != 0)
+ goto out;
+ rv = sc->phy.writereg_locked(dev, 2, I82579_DFT_CTRL,
+ dft_ctrl | (1 << 14));
+ if (rv != 0)
+ goto out;
+
+ if (enable) {
+ /* Write Rx addresses (rar_entry_count for RAL/H, and
+ * SHRAL/H) and initial CRC values to the MAC
+ */
+ rar_count = wm_rar_count(sc);
+ for (i = 0; i < rar_count; i++) {
+ uint8_t mac_addr[ETHER_ADDR_LEN] = {0};
+ uint32_t addr_high, addr_low;
+
+ addr_high = CSR_READ(sc, WMREG_CORDOVA_RAH(i));
+ if (!(addr_high & RAL_AV))
+ continue;
+ addr_low = CSR_READ(sc, WMREG_CORDOVA_RAL(i));
+ mac_addr[0] = (addr_low & 0xFF);
+ mac_addr[1] = ((addr_low >> 8) & 0xFF);
+ mac_addr[2] = ((addr_low >> 16) & 0xFF);
+ mac_addr[3] = ((addr_low >> 24) & 0xFF);
+ mac_addr[4] = (addr_high & 0xFF);
+ mac_addr[5] = ((addr_high >> 8) & 0xFF);
+
+ CSR_WRITE(sc, WMREG_PCH_RAICC(i),
+ ~ether_crc32_le(mac_addr, ETHER_ADDR_LEN));
+ }
+
+ /* Write Rx addresses to the PHY */
+ wm_copy_rx_addrs_to_phy_ich8lan_locked(sc);
+ }
+
+ /*
+ * If enable ==
+ * true: Enable jumbo frame workaround in the MAC.
+ * false: Write MAC register values back to h/w defaults.
+ */
+ mac_reg = CSR_READ(sc, WMREG_FFLT_DBG);
+ if (enable) {
+ mac_reg &= ~(1 << 14);
+ mac_reg |= (7 << 15);
+ } else
+ mac_reg &= ~(0xf << 14);
+ CSR_WRITE(sc, WMREG_FFLT_DBG, mac_reg);
+
+ mac_reg = CSR_READ(sc, WMREG_RCTL);
+ if (enable) {
+ mac_reg |= RCTL_SECRC;
+ sc->sc_rctl |= RCTL_SECRC;
+ sc->sc_flags |= WM_F_CRC_STRIP;
+ } else {
+ mac_reg &= ~RCTL_SECRC;
+ sc->sc_rctl &= ~RCTL_SECRC;
+ sc->sc_flags &= ~WM_F_CRC_STRIP;
+ }
+ CSR_WRITE(sc, WMREG_RCTL, mac_reg);
+
+ rv = wm_kmrn_readreg_locked(sc, KUMCTRLSTA_OFFSET_CTRL, &data);
+ if (rv != 0)
+ goto out;
+ if (enable)
+ data |= 1 << 0;
+ else
+ data &= ~(1 << 0);
+ rv = wm_kmrn_writereg_locked(sc, KUMCTRLSTA_OFFSET_CTRL, data);
+ if (rv != 0)
+ goto out;
+
+ rv = wm_kmrn_readreg_locked(sc, KUMCTRLSTA_OFFSET_HD_CTRL, &data);
+ if (rv != 0)
+ goto out;
+ /*
+ * XXX FreeBSD and Linux do the same thing that they set the same value
+ * on both the enable case and the disable case. Is it correct?
+ */
+ data &= ~(0xf << 8);
+ data |= (0xb << 8);
+ rv = wm_kmrn_writereg_locked(sc, KUMCTRLSTA_OFFSET_HD_CTRL, data);
+ if (rv != 0)
+ goto out;
+
+ /*
+ * If enable ==
+ * true: Enable jumbo frame workaround in the PHY.
+ * false: Write PHY register values back to h/w defaults.
+ */
+ rv = sc->phy.readreg_locked(dev, 2, BME1000_REG(769, 23), &data);
+ if (rv != 0)
+ goto out;
+ data &= ~(0x7F << 5);
+ if (enable)
+ data |= (0x37 << 5);
+ rv = sc->phy.writereg_locked(dev, 2, BME1000_REG(769, 23), data);
+ if (rv != 0)
+ goto out;
+
+ rv = sc->phy.readreg_locked(dev, 2, BME1000_REG(769, 16), &data);
+ if (rv != 0)
+ goto out;
+ if (enable)
+ data &= ~(1 << 13);
+ else
+ data |= (1 << 13);
+ rv = sc->phy.writereg_locked(dev, 2, BME1000_REG(769, 16), data);
+ if (rv != 0)
+ goto out;
+
+ rv = sc->phy.readreg_locked(dev, 2, I82579_UNKNOWN1, &data);
+ if (rv != 0)
+ goto out;
+ data &= ~(0x3FF << 2);
+ if (enable)
+ data |= (I82579_TX_PTR_GAP << 2);
+ else
+ data |= (0x8 << 2);
+ rv = sc->phy.writereg_locked(dev, 2, I82579_UNKNOWN1, data);
+ if (rv != 0)
+ goto out;
+
+ rv = sc->phy.writereg_locked(dev, 2, BME1000_REG(776, 23),
+ enable ? 0xf100 : 0x7e00);
+ if (rv != 0)
+ goto out;
+
+ rv = sc->phy.readreg_locked(dev, 2, HV_PM_CTRL, &data);
+ if (rv != 0)
+ goto out;
+ if (enable)
+ data |= 1 << 10;
+ else
+ data &= ~(1 << 10);
+ rv = sc->phy.writereg_locked(dev, 2, HV_PM_CTRL, data);
+ if (rv != 0)
+ goto out;
+
+ /* Re-enable Rx path after enabling/disabling workaround */
+ rv = sc->phy.writereg_locked(dev, 2, I82579_DFT_CTRL,
+ dft_ctrl & ~(1 << 14));
+
+out:
sc->phy.release(sc);
+
+ return rv;
}
/*
Index: src/sys/dev/pci/if_wmreg.h
diff -u src/sys/dev/pci/if_wmreg.h:1.115.2.2 src/sys/dev/pci/if_wmreg.h:1.115.2.3
--- src/sys/dev/pci/if_wmreg.h:1.115.2.2 Fri Jul 10 10:45:56 2020
+++ src/sys/dev/pci/if_wmreg.h Wed Sep 23 08:46:54 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wmreg.h,v 1.115.2.2 2020/07/10 10:45:56 martin Exp $ */
+/* $NetBSD: if_wmreg.h,v 1.115.2.3 2020/09/23 08:46:54 martin Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -1379,7 +1379,10 @@ struct livengood_tcpip_ctxdesc {
#define WMREG_FEXTNVM11 0x5bbc /* Future Extended NVM 11 */
#define FEXTNVM11_DIS_MULRFIX __BIT(13) /* Disable MULR fix */
+#define WMREG_FFLT_DBG 0x05F04 /* Debug Register */
+
#define WMREG_CRC_OFFSET 0x5f50
+#define WMREG_PCH_RAICC(x) (WMREG_CRC_OFFSET + (x) * 4)
#define WMREG_EEC 0x12010
#define EEC_FLASH_DETECTED (1U << 19) /* FLASH */
Index: src/sys/dev/pci/if_wmvar.h
diff -u src/sys/dev/pci/if_wmvar.h:1.44.4.1 src/sys/dev/pci/if_wmvar.h:1.44.4.2
--- src/sys/dev/pci/if_wmvar.h:1.44.4.1 Fri Jul 10 10:45:56 2020
+++ src/sys/dev/pci/if_wmvar.h Wed Sep 23 08:46:54 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wmvar.h,v 1.44.4.1 2020/07/10 10:45:56 martin Exp $ */
+/* $NetBSD: if_wmvar.h,v 1.44.4.2 2020/09/23 08:46:54 martin Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -99,6 +99,7 @@
#define WM_F_WA_I210_CLSEM 0x08000000 /* I21[01] Semaphore workaround */
#define WM_F_SFP 0x10000000 /* SFP */
#define WM_F_MAS 0x20000000 /* Media Auto Sense */
+#define WM_F_CRC_STRIP 0x40000000 /* CRC strip */
#define WM_FLAGS "\20" \
"\1" "HAS_MII" "\2" "LOCK_EECD" "\3" "_B02" "\4" "_B03" \
@@ -108,7 +109,7 @@
"\21" "NEWQUEUE" "\22" "ASF_FIRM" "\23" "ARC_SUBSYS" "\24" "AMT" \
"\25" "MANAGE" "\26" "WOL" "\27" "EEE" "\30" "ATTACHED" \
"\31" "MDIC_WA" "\32" "PCS_DIS_AUTONEGO" "\33" "PLLWA" "\34" "CLSEMWA" \
- "\35" "SFP" "\36" "MAS"
+ "\35" "SFP" "\36" "MAS" "\37" "CRC_STRIP"
/*
* Variations of Intel gigabit Ethernet controller:
