Module Name: src
Committed By: jmcneill
Date: Tue Sep 29 19:58:50 UTC 2020
Modified Files:
src/sys/arch/aarch64/conf: files.aarch64
src/sys/arch/arm/arm32: arm32_tlb.c db_machdep.c
src/sys/arch/arm/conf: files.arm
src/sys/arch/arm/cortex: armperiph.c files.cortex
src/sys/arch/arm/imx: imx6_board.c
src/sys/arch/arm/include: cpuconf.h
src/sys/arch/arm/samsung: files.exynos
src/sys/arch/evbarm/beagle: beagle_machdep.c
src/sys/arch/evbarm/conf: BCM5301X BCM56340 DUOVERO GENERIC GENERIC64
KOBO N900 NETWALKER OMAP5EVM PANDABOARD PARALLELLA PEPPER RPI2
VTC100 ZEDBOARD
src/sys/arch/evbarm/gumstix: gumstix_machdep.c
Log Message:
Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtime
detection instead of ifdefs where required.
To generate a diff of this commit:
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/aarch64/conf/files.aarch64
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/arm32/arm32_tlb.c
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/arm/arm32/db_machdep.c
cvs rdiff -u -r1.161 -r1.162 src/sys/arch/arm/conf/files.arm
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/armperiph.c
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/files.cortex
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/imx/imx6_board.c
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/include/cpuconf.h
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/samsung/files.exynos
cvs rdiff -u -r1.83 -r1.84 src/sys/arch/evbarm/beagle/beagle_machdep.c
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/evbarm/conf/BCM5301X
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/evbarm/conf/BCM56340
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/evbarm/conf/DUOVERO
cvs rdiff -u -r1.82 -r1.83 src/sys/arch/evbarm/conf/GENERIC
cvs rdiff -u -r1.161 -r1.162 src/sys/arch/evbarm/conf/GENERIC64
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/evbarm/conf/KOBO \
src/sys/arch/evbarm/conf/RPI2
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/evbarm/conf/N900
cvs rdiff -u -r1.40 -r1.41 src/sys/arch/evbarm/conf/NETWALKER
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/evbarm/conf/OMAP5EVM \
src/sys/arch/evbarm/conf/PEPPER
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/evbarm/conf/PANDABOARD
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbarm/conf/PARALLELLA
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/evbarm/conf/VTC100
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/evbarm/conf/ZEDBOARD
cvs rdiff -u -r1.66 -r1.67 src/sys/arch/evbarm/gumstix/gumstix_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/conf/files.aarch64
diff -u src/sys/arch/aarch64/conf/files.aarch64:1.27 src/sys/arch/aarch64/conf/files.aarch64:1.28
--- src/sys/arch/aarch64/conf/files.aarch64:1.27 Wed Aug 12 13:28:46 2020
+++ src/sys/arch/aarch64/conf/files.aarch64 Tue Sep 29 19:58:49 2020
@@ -1,4 +1,4 @@
-# $NetBSD: files.aarch64,v 1.27 2020/08/12 13:28:46 skrll Exp $
+# $NetBSD: files.aarch64,v 1.28 2020/09/29 19:58:49 jmcneill Exp $
defflag opt_cpuoptions.h AARCH64_ALIGNMENT_CHECK
defflag opt_cpuoptions.h AARCH64_EL0_STACK_ALIGNMENT_CHECK
@@ -8,9 +8,6 @@ defflag opt_cpuoptions.h AARCH64_DEVICE_
defflag opt_cputypes.h CPU_ARMV8
defflag opt_cputypes.h CPU_CORTEX: CPU_ARMV8
-defflag opt_cputypes.h CPU_CORTEXA35: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA53: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA57: CPU_CORTEX
defflag opt_cputypes.h CPU_THUNDERX: CPU_ARMV8
# Interrupt implementation header definition
Index: src/sys/arch/arm/arm32/arm32_tlb.c
diff -u src/sys/arch/arm/arm32/arm32_tlb.c:1.12 src/sys/arch/arm/arm32/arm32_tlb.c:1.13
--- src/sys/arch/arm/arm32/arm32_tlb.c:1.12 Wed Aug 15 06:00:02 2018
+++ src/sys/arch/arm/arm32/arm32_tlb.c Tue Sep 29 19:58:49 2020
@@ -31,7 +31,7 @@
#include "opt_multiprocessor.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.12 2018/08/15 06:00:02 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.13 2020/09/29 19:58:49 jmcneill Exp $");
#include <sys/param.h>
#include <sys/types.h>
@@ -143,7 +143,7 @@ tlb_update_addr(vaddr_t va, tlb_asid_t a
return true;
}
-#if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA5)
+#if !defined(MULTIPROCESSOR)
static u_int
tlb_cortex_a5_record_asids(u_long *mapp, tlb_asid_t asid_max)
{
@@ -175,7 +175,7 @@ tlb_cortex_a5_record_asids(u_long *mapp,
}
#endif
-#if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA7)
+#if !defined(MULTIPROCESSOR)
static u_int
tlb_cortex_a7_record_asids(u_long *mapp, tlb_asid_t asid_max)
{
@@ -212,14 +212,10 @@ u_int
tlb_record_asids(u_long *mapp, tlb_asid_t asid_max)
{
#ifndef MULTIPROCESSOR
-#ifdef CPU_CORTEXA5
if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid))
return tlb_cortex_a5_record_asids(mapp, asid_max);
-#endif
-#ifdef CPU_CORTEXA7
if (CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid))
return tlb_cortex_a7_record_asids(mapp, asid_max);
-#endif
#endif /* MULTIPROCESSOR */
#ifdef DIAGNOSTIC
mapp[0] = 0xfffffffe;
Index: src/sys/arch/arm/arm32/db_machdep.c
diff -u src/sys/arch/arm/arm32/db_machdep.c:1.35 src/sys/arch/arm/arm32/db_machdep.c:1.36
--- src/sys/arch/arm/arm32/db_machdep.c:1.35 Fri Aug 14 16:18:36 2020
+++ src/sys/arch/arm/arm32/db_machdep.c Tue Sep 29 19:58:49 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.35 2020/08/14 16:18:36 skrll Exp $ */
+/* $NetBSD: db_machdep.c,v 1.36 2020/09/29 19:58:49 jmcneill Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe
@@ -34,7 +34,7 @@
#endif
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.35 2020/08/14 16:18:36 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.36 2020/09/29 19:58:49 jmcneill Exp $");
#include <sys/param.h>
@@ -135,11 +135,9 @@ const struct db_command db_machine_comma
{ DDB_ADD_CMD("reset", db_reset_cmd, 0,
"Reset the system",
NULL,NULL) },
-#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7)
{ DDB_ADD_CMD("tlb", db_show_tlb_cmd, 0,
"Displays the TLB",
NULL,NULL) },
-#endif
#endif /* _KERNEL */
{ DDB_ADD_CMD(NULL, NULL, 0,NULL,NULL,NULL) }
@@ -220,7 +218,6 @@ db_reset_cmd(db_expr_t addr, bool have_a
cpu_reset_address();
}
-#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7)
static void
tlb_print_common_header(const char *str)
{
@@ -257,7 +254,6 @@ struct db_tlbinfo {
u_int dti_index;
};
-#if defined(CPU_CORTEXA5)
static void
tlb_print_cortex_a5_header(void)
{
@@ -315,9 +311,7 @@ static const struct db_tlbinfo tlb_corte
.dti_print_entry = tlb_print_cortex_a5_entry,
.dti_index = ARM_A5_TLBDATAOP_INDEX,
};
-#endif /* CPU_CORTEXA5 */
-#if defined(CPU_CORTEXA7)
static const char tlb_cortex_a7_esizes[8][8] = {
" 4KB(S)", " 4KB(L)", "64KB(S)", "64KB(L)",
" 1MB(S)", " 2MB(L)", "16MB(S)", " 1GB(L)",
@@ -394,29 +388,18 @@ static const struct db_tlbinfo tlb_corte
.dti_print_entry = tlb_print_cortex_a7_entry,
.dti_index = ARM_A7_TLBDATAOP_INDEX,
};
-#endif /* CPU_CORTEXA7 */
static inline const struct db_tlbinfo *
tlb_lookup_tlbinfo(void)
{
-#if defined(CPU_CORTEXA5) && defined(CPU_CORTEXA7)
const bool cortex_a5_p = CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid);
const bool cortex_a7_p = CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid);
-#elif defined(CPU_CORTEXA5)
- const bool cortex_a5_p = true;
-#else
- const bool cortex_a7_p = true;
-#endif
-#ifdef CPU_CORTEXA5
if (cortex_a5_p) {
return &tlb_cortex_a5_info;
}
-#endif
-#ifdef CPU_CORTEXA7
if (cortex_a7_p) {
return &tlb_cortex_a7_info;
}
-#endif
return NULL;
}
@@ -425,6 +408,11 @@ db_show_tlb_cmd(db_expr_t addr, bool hav
{
const struct db_tlbinfo * const dti = tlb_lookup_tlbinfo();
+ if (dti == NULL) {
+ db_printf("not supported on this CPU\n");
+ return;
+ }
+
if (have_addr) {
const vaddr_t vpn = (vaddr_t)addr >> L2_S_SHIFT;
const u_int va_index = vpn & dti->dti_index;
@@ -468,7 +456,6 @@ db_show_tlb_cmd(db_expr_t addr, bool hav
}
db_printf("%zu TLB valid entries found\n", n);
}
-#endif /* CPU_CORTEXA5 || CPU_CORTEXA7 */
#if defined(MULTIPROCESSOR)
void
Index: src/sys/arch/arm/conf/files.arm
diff -u src/sys/arch/arm/conf/files.arm:1.161 src/sys/arch/arm/conf/files.arm:1.162
--- src/sys/arch/arm/conf/files.arm:1.161 Sun Aug 2 06:58:16 2020
+++ src/sys/arch/arm/conf/files.arm Tue Sep 29 19:58:49 2020
@@ -1,4 +1,4 @@
-# $NetBSD: files.arm,v 1.161 2020/08/02 06:58:16 maxv Exp $
+# $NetBSD: files.arm,v 1.162 2020/09/29 19:58:49 jmcneill Exp $
# temporary define to allow easy moving to ../arch/arm/arm32
defflag ARM32
@@ -40,15 +40,6 @@ defflag opt_cputypes.h CPU_ARM1176: CPU
defflag opt_cputypes.h CPU_ARM11MPCORE: CPU_ARM11
defflag opt_cputypes.h CPU_PJ4B: CPU_ARMV7
defflag opt_cputypes.h CPU_CORTEX: CPU_ARMV7
-defflag opt_cputypes.h CPU_CORTEXA5: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA7: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA8: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA9: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA15: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA17: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA35: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA53: CPU_CORTEX
-defflag opt_cputypes.h CPU_CORTEXA57: CPU_CORTEX
defflag opt_cputypes.h FPU_VFP
defparam opt_cpuoptions.h XSCALE_CCLKCFG
Index: src/sys/arch/arm/cortex/armperiph.c
diff -u src/sys/arch/arm/cortex/armperiph.c:1.15 src/sys/arch/arm/cortex/armperiph.c:1.16
--- src/sys/arch/arm/cortex/armperiph.c:1.15 Tue Sep 25 20:55:34 2018
+++ src/sys/arch/arm/cortex/armperiph.c Tue Sep 29 19:58:50 2020
@@ -32,7 +32,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.15 2018/09/25 20:55:34 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.16 2020/09/29 19:58:50 jmcneill Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -61,7 +61,6 @@ struct armperiph_info {
bus_size_t pi_off2;
};
-#ifdef CPU_CORTEXA5
static const struct armperiph_info a5_devices[] = {
{ "armscu", 0x0000, 0 },
{ "armgic", 0x1000, 0x0100 },
@@ -70,17 +69,13 @@ static const struct armperiph_info a5_de
{ "arml2cc", 0, 0 }, /* external; needs "offset" property */
{ "", 0, 0 },
};
-#endif
-#ifdef CPU_CORTEXA7
static const struct armperiph_info a7_devices[] = {
{ "armgic", 0x1000, 0x2000 },
{ "armgtmr", 0, 0 },
{ "", 0, 0 },
};
-#endif
-#ifdef CPU_CORTEXA9
static const struct armperiph_info a9_devices[] = {
{ "armscu", 0x0000, 0 },
{ "arml2cc", 0x2000, 0 },
@@ -89,31 +84,24 @@ static const struct armperiph_info a9_de
{ "a9wdt", 0x0600, 0 },
{ "", 0, 0 },
};
-#endif
-#ifdef CPU_CORTEXA15
static const struct armperiph_info a15_devices[] = {
{ "armgic", 0x1000, 0x2000 },
{ "armgtmr", 0, 0 },
{ "", 0, 0 },
};
-#endif
-#ifdef CPU_CORTEXA17
static const struct armperiph_info a17_devices[] = {
{ "armgic", 0x1000, 0x2000 },
{ "armgtmr", 0, 0 },
{ "", 0, 0 },
};
-#endif
-#ifdef CPU_CORTEXA57
static const struct armperiph_info a57_devices[] = {
{ "armgic", 0x1000, 0x2000 },
{ "armgtmr", 0, 0 },
{ "", 0, 0 },
};
-#endif
static const struct mpcore_config {
@@ -121,24 +109,12 @@ static const struct mpcore_config {
uint32_t cfg_cpuid;
uint32_t cfg_cbar_size;
} configs[] = {
-#ifdef CPU_CORTEXA5
{ a5_devices, 0x410fc050, 2*4096 },
-#endif
-#ifdef CPU_CORTEXA7
{ a7_devices, 0x410fc070, 8*4096 },
-#endif
-#ifdef CPU_CORTEXA9
{ a9_devices, 0x410fc090, 3*4096 },
-#endif
-#ifdef CPU_CORTEXA15
{ a15_devices, 0x410fc0f0, 8*4096 },
-#endif
-#ifdef CPU_CORTEXA17
{ a17_devices, 0x410fc0e0, 8*4096 },
-#endif
-#ifdef CPU_CORTEXA57
{ a57_devices, 0x410fd070, 8*4096 },
-#endif
};
static const struct mpcore_config *
@@ -230,15 +206,12 @@ armperiph_attach(device_t parent, device
.mpcaa_off1 = cfg->cfg_devices[i].pi_off1,
.mpcaa_off2 = cfg->cfg_devices[i].pi_off2,
};
-#if defined(CPU_CORTEXA9) || defined(CPU_CORTEXA5)
- if (strcmp(mpcaa.mpcaa_name, "arma9tmr") == 0)
+ if (strcmp(mpcaa.mpcaa_name, "arma9tmr") == 0) {
mpcaa.mpcaa_irq = IRQ_A9TMR_PPI_GTIMER;
-#endif
-#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA57)
+ }
if (strcmp(mpcaa.mpcaa_name, "armgtmr") == 0) {
mpcaa.mpcaa_irq = IRQ_GTMR_PPI_VTIMER;
}
-#endif
config_found(self, &mpcaa, NULL);
}
Index: src/sys/arch/arm/cortex/files.cortex
diff -u src/sys/arch/arm/cortex/files.cortex:1.13 src/sys/arch/arm/cortex/files.cortex:1.14
--- src/sys/arch/arm/cortex/files.cortex:1.13 Mon Oct 14 11:00:13 2019
+++ src/sys/arch/arm/cortex/files.cortex Tue Sep 29 19:58:50 2020
@@ -1,4 +1,4 @@
-# $NetBSD: files.cortex,v 1.13 2019/10/14 11:00:13 jmcneill Exp $
+# $NetBSD: files.cortex,v 1.14 2020/09/29 19:58:50 jmcneill Exp $
defflag opt_cpu_in_cksum.h NEON_IN_CKSUM
@@ -32,12 +32,12 @@ file arch/arm/cortex/pl310.c arml2cc n
# ARMv7 Generic Timer
device armgtmr
attach armgtmr at mpcorebus
-file arch/arm/cortex/gtmr.c armgtmr
+file arch/arm/cortex/gtmr.c armgtmr needs-flag
# A9 MPCore Global Timer
device arma9tmr
attach arma9tmr at mpcorebus
-file arch/arm/cortex/a9tmr.c arma9tmr
+file arch/arm/cortex/a9tmr.c arma9tmr needs-flag
# A9 MPcore Private Timer
device arma9ptmr
Index: src/sys/arch/arm/imx/imx6_board.c
diff -u src/sys/arch/arm/imx/imx6_board.c:1.15 src/sys/arch/arm/imx/imx6_board.c:1.16
--- src/sys/arch/arm/imx/imx6_board.c:1.15 Wed Jan 15 01:09:56 2020
+++ src/sys/arch/arm/imx/imx6_board.c Tue Sep 29 19:58:50 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_board.c,v 1.15 2020/01/15 01:09:56 jmcneill Exp $ */
+/* $NetBSD: imx6_board.c,v 1.16 2020/09/29 19:58:50 jmcneill Exp $ */
/*
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: imx6_board.c,v 1.15 2020/01/15 01:09:56 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: imx6_board.c,v 1.16 2020/09/29 19:58:50 jmcneill Exp $");
#include "arml2cc.h"
#include "imxgpio.h"
@@ -228,14 +228,12 @@ imx6_device_register(device_t self, void
imx6_armrootclk() / IMX6_PERIPHCLK_N);
return;
}
-#ifdef CPU_CORTEXA7
/* also for A7 */
if (device_is_a(self, "armgtmr")) {
prop_dictionary_set_uint32(dict, "frequency",
armreg_cnt_frq_read());
return;
}
-#endif
}
void
Index: src/sys/arch/arm/include/cpuconf.h
diff -u src/sys/arch/arm/include/cpuconf.h:1.27 src/sys/arch/arm/include/cpuconf.h:1.28
--- src/sys/arch/arm/include/cpuconf.h:1.27 Fri Aug 10 16:17:30 2018
+++ src/sys/arch/arm/include/cpuconf.h Tue Sep 29 19:58:50 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuconf.h,v 1.27 2018/08/10 16:17:30 maxv Exp $ */
+/* $NetBSD: cpuconf.h,v 1.28 2020/09/29 19:58:50 jmcneill Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@@ -72,8 +72,6 @@
defined(CPU_ARM1176) + \
defined(CPU_ARM11MPCORE) + \
defined(CPU_CORTEX) + \
- defined(CPU_CORTEXA8) + \
- defined(CPU_CORTEXA9) + \
defined(CPU_SA110) + defined(CPU_SA1100) + \
defined(CPU_SA1110) + \
defined(CPU_FA526) + \
Index: src/sys/arch/arm/samsung/files.exynos
diff -u src/sys/arch/arm/samsung/files.exynos:1.36 src/sys/arch/arm/samsung/files.exynos:1.37
--- src/sys/arch/arm/samsung/files.exynos:1.36 Thu Jan 3 23:04:09 2019
+++ src/sys/arch/arm/samsung/files.exynos Tue Sep 29 19:58:50 2020
@@ -1,4 +1,4 @@
-# $NetBSD: files.exynos,v 1.36 2019/01/03 23:04:09 jmcneill Exp $
+# $NetBSD: files.exynos,v 1.37 2020/09/29 19:58:50 jmcneill Exp $
#
# Configuration info for Samsung Exynos SoC ARM Peripherals
#
@@ -11,12 +11,12 @@ defparam opt_exynos.h EXYNOS_WDT_DEFA
#
defflag opt_exynos.h SOC_EXYNOS
-defflag opt_exynos.h SOC_EXYNOS4: SOC_EXYNOS, CPU_CORTEXA9
+defflag opt_exynos.h SOC_EXYNOS4: SOC_EXYNOS, CPU_CORTEX
defflag opt_exynos.h SOC_EXYNOS4120: SOC_EXYNOS4
defflag opt_exynos.h SOC_EXYNOS4212: SOC_EXYNOS4
defflag opt_exynos.h SOC_EXYNOS4412: SOC_EXYNOS4
defflag opt_exynos.h SOC_EXYNOS4412P: SOC_EXYNOS4
-defflag opt_exynos.h SOC_EXYNOS5: SOC_EXYNOS, CPU_CORTEXA15
+defflag opt_exynos.h SOC_EXYNOS5: SOC_EXYNOS, CPU_CORTEX
defflag opt_exynos.h SOC_EXYNOS5250: SOC_EXYNOS5
defflag opt_exynos.h SOC_EXYNOS5260: SOC_EXYNOS5
defflag opt_exynos.h SOC_EXYNOS5410: SOC_EXYNOS5
Index: src/sys/arch/evbarm/beagle/beagle_machdep.c
diff -u src/sys/arch/evbarm/beagle/beagle_machdep.c:1.83 src/sys/arch/evbarm/beagle/beagle_machdep.c:1.84
--- src/sys/arch/evbarm/beagle/beagle_machdep.c:1.83 Fri Jul 10 12:25:10 2020
+++ src/sys/arch/evbarm/beagle/beagle_machdep.c Tue Sep 29 19:58:50 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: beagle_machdep.c,v 1.83 2020/07/10 12:25:10 skrll Exp $ */
+/* $NetBSD: beagle_machdep.c,v 1.84 2020/09/29 19:58:50 jmcneill Exp $ */
/*
* Machine dependent functions for kernel setup for TI OSK5912 board.
@@ -125,7 +125,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.83 2020/07/10 12:25:10 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: beagle_machdep.c,v 1.84 2020/09/29 19:58:50 jmcneill Exp $");
#include "opt_arm_debug.h"
#include "opt_console.h"
@@ -142,6 +142,8 @@ __KERNEL_RCSID(0, "$NetBSD: beagle_machd
#include "prcm.h"
#include "sdhc.h"
#include "ukbd.h"
+#include "arma9tmr.h"
+#include "armgtmr.h"
#include "arml2cc.h"
#include <sys/param.h>
@@ -198,17 +200,13 @@ __KERNEL_RCSID(0, "$NetBSD: beagle_machd
# endif
#endif
-#ifdef CPU_CORTEXA9
#include <arm/cortex/pl310_reg.h>
#include <arm/cortex/scu_reg.h>
#include <arm/cortex/a9tmr_var.h>
#include <arm/cortex/pl310_var.h>
-#endif
-#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
#include <arm/cortex/gtmr_var.h>
-#endif
#include <evbarm/include/autoconf.h>
#include <evbarm/beagle/beagle.h>
@@ -245,9 +243,7 @@ int use_fb_console = false;
int use_fb_console = true;
#endif
-#ifdef CPU_CORTEXA15
uint32_t omap5_cnt_frq;
-#endif
/*
* Macros to translate between physical and virtual for a subset of the
@@ -439,10 +435,16 @@ static const struct pmap_devmap devmap[]
void
beagle_cpu_hatch(struct cpu_info *ci)
{
-#if defined(CPU_CORTEXA9)
- a9tmr_init_cpu_clock(ci);
-#elif defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
- gtmr_init_cpu_clock(ci);
+#if NARMA9TMR > 0
+ if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) {
+ a9tmr_init_cpu_clock(ci);
+ }
+#endif
+#if NARMGMR > 0
+ if (CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid) ||
+ CPU_ID_CORTEX_A15_P(curcpu()->ci_arm_cpuid)) {
+ gtmr_init_cpu_clock(ci);
+ }
#endif
}
#endif
@@ -453,25 +455,26 @@ beagle_mpstart(void)
#if defined(MULTIPROCESSOR)
const bus_space_tag_t bst = &omap_bs_tag;
-#if defined(CPU_CORTEXA9)
- const bus_space_handle_t scu_bsh = OMAP4_SCU_BASE
- + OMAP_L4_PERIPHERAL_VBASE - OMAP_L4_PERIPHERAL_BASE;
+ if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) {
+ const bus_space_handle_t scu_bsh = OMAP4_SCU_BASE
+ + OMAP_L4_PERIPHERAL_VBASE - OMAP_L4_PERIPHERAL_BASE;
- /*
- * Invalidate all SCU cache tags. That is, for all cores (0-3)
- */
- bus_space_write_4(bst, scu_bsh, SCU_INV_ALL_REG, 0xffff);
+ /*
+ * Invalidate all SCU cache tags. That is, for all cores (0-3)
+ */
+ bus_space_write_4(bst, scu_bsh, SCU_INV_ALL_REG, 0xffff);
- uint32_t diagctl = bus_space_read_4(bst, scu_bsh, SCU_DIAG_CONTROL);
- diagctl |= SCU_DIAG_DISABLE_MIGBIT;
- bus_space_write_4(bst, scu_bsh, SCU_DIAG_CONTROL, diagctl);
+ uint32_t diagctl = bus_space_read_4(bst, scu_bsh, SCU_DIAG_CONTROL);
+ diagctl |= SCU_DIAG_DISABLE_MIGBIT;
+ bus_space_write_4(bst, scu_bsh, SCU_DIAG_CONTROL, diagctl);
- uint32_t scu_ctl = bus_space_read_4(bst, scu_bsh, SCU_CTL);
- scu_ctl |= SCU_CTL_SCU_ENA;
- bus_space_write_4(bst, scu_bsh, SCU_CTL, scu_ctl);
+ uint32_t scu_ctl = bus_space_read_4(bst, scu_bsh, SCU_CTL);
+ scu_ctl |= SCU_CTL_SCU_ENA;
+ bus_space_write_4(bst, scu_bsh, SCU_CTL, scu_ctl);
+
+ armv7_dcache_wbinv_all();
+ }
- armv7_dcache_wbinv_all();
-#endif
const bus_space_handle_t wugen_bsh = OMAP4_WUGEN_BASE + OMAP_L4_CORE_VOFFSET;
const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart);
@@ -610,10 +613,10 @@ initarm(void *arg)
}
consinit();
-#ifdef CPU_CORTEXA15
#ifdef MULTIPROCESSOR
- arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
-#endif
+ if (CPU_ID_CORTEX_A15_P(curcpu()->ci_arm_cpuid)) {
+ arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
+ }
#endif
#if defined(OMAP_4XXX)
#if NARML2CC > 0
@@ -659,10 +662,6 @@ initarm(void *arg)
VPRINTF("initarm: Configuring system ...\n");
-#if !defined(CPU_CORTEXA8)
- printf("initarm: cbar=%#x\n", armreg_cbar_read());
-#endif
-
/*
* Set up the variables that define the availability of physical
* memory.
@@ -911,8 +910,8 @@ omap4_cpu_clk(void)
__func__, curcpu()->ci_data.cpu_cc_freq,
sys_clk, m, n, n+1, m2, OMAP4_CM_CLKSEL_MULT);
-#if defined(CPU_CORTEXA15)
- if ((armreg_pfr1_read() & ARM_PFR1_GTIMER_MASK) != 0) {
+ if (CPU_ID_CORTEX_A15_P(curcpu()->ci_arm_cpuid) &&
+ (armreg_pfr1_read() & ARM_PFR1_GTIMER_MASK) != 0) {
beagle_putchar('0');
uint32_t voffset = OMAP_L4_PERIPHERAL_VBASE - OMAP_L4_PERIPHERAL_BASE;
uint32_t frac1_reg = OMAP5_PRM_FRAC_INCREMENTER_NUMERATOR;
@@ -959,7 +958,6 @@ omap4_cpu_clk(void)
omap5_cnt_frq = freq;
beagle_putchar('4');
}
-#endif
}
#endif /* OMAP_4XXX || OMAP_5XXX */
@@ -968,15 +966,15 @@ omap4_cpu_clk(void)
static inline uint32_t
emif_read_sdram_config(vaddr_t emif_base)
{
-#ifdef CPU_CORTEXA15
- return 0x61851b32; // XXX until i figure out why deref emif_base dies
-#else
+ if (CPU_ID_CORTEX_A15_P(curcpu()->ci_arm_cpuid)) {
+ return 0x61851b32; // XXX until i figure out why deref emif_base dies
+ }
+
emif_base += EMIF_SDRAM_CONFIG;
//printf("%s: sdram_config @ %#"PRIxVADDR" = ", __func__, emif_base);
uint32_t v = *(const volatile uint32_t *)(emif_base);
//printf("%#x\n", v);
return v;
-#endif
}
static psize_t
@@ -1090,7 +1088,6 @@ beagle_device_register(device_t self, vo
return;
}
-#ifdef CPU_CORTEXA9
/*
* We need to tell the A9 Global/Watchdog Timer
* what frequency it runs at.
@@ -1104,9 +1101,7 @@ beagle_device_register(device_t self, vo
curcpu()->ci_data.cpu_cc_freq / 2);
return;
}
-#endif
-#ifdef CPU_CORTEXA15
if (device_is_a(self, "armgtmr")) {
/*
* The frequency of the generic timer was figured out when
@@ -1114,7 +1109,6 @@ beagle_device_register(device_t self, vo
*/
prop_dictionary_set_uint32(dict, "frequency", omap5_cnt_frq);
}
-#endif
if (device_is_a(self, "ehci")) {
#if defined(OMAP_3530)
Index: src/sys/arch/evbarm/conf/BCM5301X
diff -u src/sys/arch/evbarm/conf/BCM5301X:1.37 src/sys/arch/evbarm/conf/BCM5301X:1.38
--- src/sys/arch/evbarm/conf/BCM5301X:1.37 Sun Sep 27 13:48:50 2020
+++ src/sys/arch/evbarm/conf/BCM5301X Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: BCM5301X,v 1.37 2020/09/27 13:48:50 roy Exp $
+# $NetBSD: BCM5301X,v 1.38 2020/09/29 19:58:50 jmcneill Exp $
#
# BCM5301X -- Broadcom BCM5301X Eval Board Kernel
#
@@ -23,7 +23,7 @@ options UVMHIST
options BCM53XX_CONSOLE_EARLY
options BCMETH_COUNTERS
#options MULTIPROCESSOR
-options CPU_CORTEXA9
+options CPU_CORTEX
#options MEMSIZE=256
options BCM5301X
#options PMAPCOUNTERS
Index: src/sys/arch/evbarm/conf/BCM56340
diff -u src/sys/arch/evbarm/conf/BCM56340:1.20 src/sys/arch/evbarm/conf/BCM56340:1.21
--- src/sys/arch/evbarm/conf/BCM56340:1.20 Sat Apr 18 11:00:38 2020
+++ src/sys/arch/evbarm/conf/BCM56340 Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: BCM56340,v 1.20 2020/04/18 11:00:38 skrll Exp $
+# $NetBSD: BCM56340,v 1.21 2020/09/29 19:58:50 jmcneill Exp $
#
# BCM5301X -- Broadcom BCM5301X Eval Board Kernel
#
@@ -23,7 +23,7 @@ options UVMHIST
options BCM53XX_CONSOLE_EARLY
options BCMETH_COUNTERS
#options MULTIPROCESSOR
-options CPU_CORTEXA9
+options CPU_CORTEX
#options MEMSIZE=256
options BCM563XX
options PMAPCOUNTERS
Index: src/sys/arch/evbarm/conf/DUOVERO
diff -u src/sys/arch/evbarm/conf/DUOVERO:1.21 src/sys/arch/evbarm/conf/DUOVERO:1.22
--- src/sys/arch/evbarm/conf/DUOVERO:1.21 Sun Sep 27 13:48:50 2020
+++ src/sys/arch/evbarm/conf/DUOVERO Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: DUOVERO,v 1.21 2020/09/27 13:48:50 roy Exp $
+# $NetBSD: DUOVERO,v 1.22 2020/09/29 19:58:50 jmcneill Exp $
#
# DUOOVERO -- Gumstix. Inc. DuoVero COMS platforms kernel
#
@@ -14,7 +14,7 @@ maxusers 32
# CPU options
-options CPU_CORTEXA9
+options CPU_CORTEX
options OMAP_4430
options MULTIPROCESSOR
options __HAVE_CPU_UAREA_ALLOC_IDLELWP # need for MULTIPROCESSOR
Index: src/sys/arch/evbarm/conf/GENERIC
diff -u src/sys/arch/evbarm/conf/GENERIC:1.82 src/sys/arch/evbarm/conf/GENERIC:1.83
--- src/sys/arch/evbarm/conf/GENERIC:1.82 Sun Jul 12 13:35:33 2020
+++ src/sys/arch/evbarm/conf/GENERIC Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: GENERIC,v 1.82 2020/07/12 13:35:33 skrll Exp $
+# $NetBSD: GENERIC,v 1.83 2020/09/29 19:58:50 jmcneill Exp $
#
# GENERIC ARM (aarch32) kernel
#
@@ -8,13 +8,7 @@ include "arch/evbarm/conf/std.generic"
include "arch/evbarm/conf/files.generic"
include "arch/evbarm/conf/GENERIC.common"
-options CPU_CORTEXA5
-options CPU_CORTEXA7
-options CPU_CORTEXA8
-options CPU_CORTEXA9
-options CPU_CORTEXA15
-options CPU_CORTEXA17
-options CPU_CORTEXA53
+options CPU_CORTEX
options SOC_AM33XX
options SOC_BCM2836
Index: src/sys/arch/evbarm/conf/GENERIC64
diff -u src/sys/arch/evbarm/conf/GENERIC64:1.161 src/sys/arch/evbarm/conf/GENERIC64:1.162
--- src/sys/arch/evbarm/conf/GENERIC64:1.161 Sun Aug 2 06:58:16 2020
+++ src/sys/arch/evbarm/conf/GENERIC64 Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: GENERIC64,v 1.161 2020/08/02 06:58:16 maxv Exp $
+# $NetBSD: GENERIC64,v 1.162 2020/09/29 19:58:50 jmcneill Exp $
#
# GENERIC ARM (aarch64) kernel
#
@@ -10,8 +10,7 @@ include "arch/evbarm/conf/GENERIC.common
maxusers 64
-options CPU_CORTEXA53
-options CPU_CORTEXA57
+options CPU_CORTEX
options CPU_THUNDERX
options SOC_BCM2837
options SOC_MESONGXBB
Index: src/sys/arch/evbarm/conf/KOBO
diff -u src/sys/arch/evbarm/conf/KOBO:1.11 src/sys/arch/evbarm/conf/KOBO:1.12
--- src/sys/arch/evbarm/conf/KOBO:1.11 Sat Apr 18 11:00:38 2020
+++ src/sys/arch/evbarm/conf/KOBO Tue Sep 29 19:58:50 2020
@@ -1,4 +1,4 @@
-# $NetBSD: KOBO,v 1.11 2020/04/18 11:00:38 skrll Exp $
+# $NetBSD: KOBO,v 1.12 2020/09/29 19:58:50 jmcneill Exp $
#
# KOBO -- http://kobo.com
#
@@ -7,7 +7,7 @@ include "arch/evbarm/conf/std.kobo"
include "arch/evbarm/conf/GENERIC.common"
# CPU options
-options CPU_CORTEXA8 # Support the ARM-v7a core
+options CPU_CORTEX # Support the ARM-v7a core
options IMX51
options IMX50
options IMX508
Index: src/sys/arch/evbarm/conf/RPI2
diff -u src/sys/arch/evbarm/conf/RPI2:1.11 src/sys/arch/evbarm/conf/RPI2:1.12
--- src/sys/arch/evbarm/conf/RPI2:1.11 Mon May 18 21:19:35 2020
+++ src/sys/arch/evbarm/conf/RPI2 Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: RPI2,v 1.11 2020/05/18 21:19:35 jmcneill Exp $
+# $NetBSD: RPI2,v 1.12 2020/09/29 19:58:50 jmcneill Exp $
#
# RPi2 -- Raspberry Pi 2
#
@@ -19,7 +19,7 @@ no makeoptions CPUFLAGS
#options EARLYCONS=bcm2837,CONSADDR=0x3f215040 # RPI3
options SOC_BCM2836
-options CPU_CORTEXA7
+options CPU_CORTEX
options MULTIPROCESSOR
#options CORTEX_PMC
options TPIDRPRW_IS_CURCPU
Index: src/sys/arch/evbarm/conf/N900
diff -u src/sys/arch/evbarm/conf/N900:1.35 src/sys/arch/evbarm/conf/N900:1.36
--- src/sys/arch/evbarm/conf/N900:1.35 Sat Jun 13 16:51:25 2020
+++ src/sys/arch/evbarm/conf/N900 Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: N900,v 1.35 2020/06/13 16:51:25 ad Exp $
+# $NetBSD: N900,v 1.36 2020/09/29 19:58:50 jmcneill Exp $
#
# N900 -- Nokia N900 Kernel
#
@@ -18,7 +18,7 @@ options RTC_OFFSET=0 # hardware clock i
# CPU options
#options UVMHIST,UVMHIST_PRINT
-options CPU_CORTEXA8
+options CPU_CORTEX
options OMAP_3430
#options PMAPCOUNTERS
Index: src/sys/arch/evbarm/conf/NETWALKER
diff -u src/sys/arch/evbarm/conf/NETWALKER:1.40 src/sys/arch/evbarm/conf/NETWALKER:1.41
--- src/sys/arch/evbarm/conf/NETWALKER:1.40 Sat Apr 18 11:00:38 2020
+++ src/sys/arch/evbarm/conf/NETWALKER Tue Sep 29 19:58:50 2020
@@ -1,4 +1,4 @@
-# $NetBSD: NETWALKER,v 1.40 2020/04/18 11:00:38 skrll Exp $
+# $NetBSD: NETWALKER,v 1.41 2020/09/29 19:58:50 jmcneill Exp $
#
# NETWALKER -- http://www.sharp.co.jp/netwalker/
#
@@ -7,7 +7,7 @@ include "arch/evbarm/conf/std.netwalker"
include "arch/evbarm/conf/GENERIC.common"
# CPU options
-options CPU_CORTEXA8 # Support the ARM-v7a core
+options CPU_CORTEX # Support the ARM-v7a core
options IMX51
# Device options
Index: src/sys/arch/evbarm/conf/OMAP5EVM
diff -u src/sys/arch/evbarm/conf/OMAP5EVM:1.19 src/sys/arch/evbarm/conf/OMAP5EVM:1.20
--- src/sys/arch/evbarm/conf/OMAP5EVM:1.19 Sat Jun 13 16:51:25 2020
+++ src/sys/arch/evbarm/conf/OMAP5EVM Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: OMAP5EVM,v 1.19 2020/06/13 16:51:25 ad Exp $
+# $NetBSD: OMAP5EVM,v 1.20 2020/09/29 19:58:50 jmcneill Exp $
#
# OMAP5EVM -- TI OMAP 543x Eval Board Kernel
#
@@ -17,7 +17,7 @@ options RTC_OFFSET=0 # hardware clock i
# CPU options
-options CPU_CORTEXA15
+options CPU_CORTEX
options OMAP_5430
#options PMAPCOUNTERS
options MULTIPROCESSOR
Index: src/sys/arch/evbarm/conf/PEPPER
diff -u src/sys/arch/evbarm/conf/PEPPER:1.19 src/sys/arch/evbarm/conf/PEPPER:1.20
--- src/sys/arch/evbarm/conf/PEPPER:1.19 Sun Sep 27 13:48:50 2020
+++ src/sys/arch/evbarm/conf/PEPPER Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: PEPPER,v 1.19 2020/09/27 13:48:50 roy Exp $
+# $NetBSD: PEPPER,v 1.20 2020/09/29 19:58:50 jmcneill Exp $
#
# PEPPER -- Gumstix. Inc. Pepper Single Board Computer platforms kernel
#
@@ -14,7 +14,7 @@ maxusers 32
# CPU options
-options CPU_CORTEXA8
+options CPU_CORTEX
options TI_AM335X
options FPU_VFP
#options PMAPCOUNTERS
Index: src/sys/arch/evbarm/conf/PANDABOARD
diff -u src/sys/arch/evbarm/conf/PANDABOARD:1.32 src/sys/arch/evbarm/conf/PANDABOARD:1.33
--- src/sys/arch/evbarm/conf/PANDABOARD:1.32 Sat Jun 13 16:51:25 2020
+++ src/sys/arch/evbarm/conf/PANDABOARD Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: PANDABOARD,v 1.32 2020/06/13 16:51:25 ad Exp $
+# $NetBSD: PANDABOARD,v 1.33 2020/09/29 19:58:50 jmcneill Exp $
#
# PANDABOARD -- TI OMAP 4430 Eval Board Kernel
#
@@ -17,7 +17,7 @@ options RTC_OFFSET=0 # hardware clock i
# CPU options
-options CPU_CORTEXA9
+options CPU_CORTEX
options OMAP_4430
#options PMAPCOUNTERS
Index: src/sys/arch/evbarm/conf/PARALLELLA
diff -u src/sys/arch/evbarm/conf/PARALLELLA:1.8 src/sys/arch/evbarm/conf/PARALLELLA:1.9
--- src/sys/arch/evbarm/conf/PARALLELLA:1.8 Sat Apr 18 11:00:38 2020
+++ src/sys/arch/evbarm/conf/PARALLELLA Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: PARALLELLA,v 1.8 2020/04/18 11:00:38 skrll Exp $
+# $NetBSD: PARALLELLA,v 1.9 2020/09/29 19:58:50 jmcneill Exp $
#
# Parallella -- Xilinx Zynq Eval Board Kernel
#
@@ -17,7 +17,6 @@ options ZYNQ7000
options ZYNQ7010
options MULTIPROCESSOR
options CPU_CORTEX
-options CPU_CORTEXA9
options MEMSIZE=1024
# Architecture options
Index: src/sys/arch/evbarm/conf/VTC100
diff -u src/sys/arch/evbarm/conf/VTC100:1.23 src/sys/arch/evbarm/conf/VTC100:1.24
--- src/sys/arch/evbarm/conf/VTC100:1.23 Sat Jun 13 16:51:25 2020
+++ src/sys/arch/evbarm/conf/VTC100 Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: VTC100,v 1.23 2020/06/13 16:51:25 ad Exp $
+# $NetBSD: VTC100,v 1.24 2020/09/29 19:58:50 jmcneill Exp $
#
# VTC100 -- NEXCOM VTC100 Kernel
#
@@ -17,7 +17,7 @@ options RTC_OFFSET=0 # hardware clock i
# CPU options
-options CPU_CORTEXA8
+options CPU_CORTEX
options TI_AM335X
#options PMAPCOUNTERS
Index: src/sys/arch/evbarm/conf/ZEDBOARD
diff -u src/sys/arch/evbarm/conf/ZEDBOARD:1.7 src/sys/arch/evbarm/conf/ZEDBOARD:1.8
--- src/sys/arch/evbarm/conf/ZEDBOARD:1.7 Sat Apr 18 11:00:38 2020
+++ src/sys/arch/evbarm/conf/ZEDBOARD Tue Sep 29 19:58:50 2020
@@ -1,5 +1,5 @@
#
-# $NetBSD: ZEDBOARD,v 1.7 2020/04/18 11:00:38 skrll Exp $
+# $NetBSD: ZEDBOARD,v 1.8 2020/09/29 19:58:50 jmcneill Exp $
#
# ZedBoard -- Xilinx Zynq Eval Board Kernel
#
@@ -16,7 +16,6 @@ options EVBARM_BOARDTYPE=zedboard
options ZYNQ7000
options MULTIPROCESSOR
options CPU_CORTEX
-options CPU_CORTEXA9
options MEMSIZE=512
# Architecture options
Index: src/sys/arch/evbarm/gumstix/gumstix_machdep.c
diff -u src/sys/arch/evbarm/gumstix/gumstix_machdep.c:1.66 src/sys/arch/evbarm/gumstix/gumstix_machdep.c:1.67
--- src/sys/arch/evbarm/gumstix/gumstix_machdep.c:1.66 Sat Apr 18 11:00:39 2020
+++ src/sys/arch/evbarm/gumstix/gumstix_machdep.c Tue Sep 29 19:58:50 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: gumstix_machdep.c,v 1.66 2020/04/18 11:00:39 skrll Exp $ */
+/* $NetBSD: gumstix_machdep.c,v 1.67 2020/09/29 19:58:50 jmcneill Exp $ */
/*
* Copyright (C) 2005, 2006, 2007 WIDE Project and SOUM Corporation.
* All rights reserved.
@@ -154,6 +154,9 @@
#include "prcm.h"
#endif
+#include "arma9tmr.h"
+#include "armgtmr.h"
+
#include <sys/param.h>
#include <sys/conf.h>
#include <sys/device.h>
@@ -198,17 +201,13 @@
#include <evbarm/gumstix/gumstixreg.h>
#include <evbarm/gumstix/gumstixvar.h>
-#if defined(CPU_CORTEXA9)
#include <arm/cortex/pl310_var.h>
#include <arm/cortex/pl310_reg.h>
#include <arm/cortex/scu_reg.h>
#include <arm/cortex/a9tmr_var.h>
-#endif
-#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
#include <arm/cortex/gtmr_var.h>
-#endif
#include <dev/cons.h>
@@ -479,10 +478,16 @@ void gumstix_cpu_hatch(struct cpu_info *
void
gumstix_cpu_hatch(struct cpu_info *ci)
{
-#if defined(CPU_CORTEXA9)
- a9tmr_init_cpu_clock(ci);
-#elif defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
- gtmr_init_cpu_clock(ci);
+#if NARMA9TMR > 0
+ if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) {
+ a9tmr_init_cpu_clock(ci);
+ }
+#endif
+#if NARMGTMR > 0
+ if (CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid) ||
+ CPU_ID_CORTEX_A15_P(curcpu()->ci_arm_cpuid)) {
+ gtmr_init_cpu_clock(ci);
+ }
#endif
}
#endif
@@ -495,27 +500,28 @@ gumstix_mpstart(void)
const bus_space_tag_t iot = &omap_bs_tag;
int error;
-#if defined(CPU_CORTEXA9)
- bus_space_handle_t scu_ioh;
- error = bus_space_map(iot, OMAP4_SCU_BASE, OMAP4_SCU_SIZE, 0, &scu_ioh);
- if (error)
- panic("Could't map OMAP4_SCU_BASE");
+ if (CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid)) {
+ bus_space_handle_t scu_ioh;
+ error = bus_space_map(iot, OMAP4_SCU_BASE, OMAP4_SCU_SIZE, 0, &scu_ioh);
+ if (error)
+ panic("Could't map OMAP4_SCU_BASE");
- /*
- * Invalidate all SCU cache tags. That is, for all cores (0-3)
- */
- bus_space_write_4(iot, scu_ioh, SCU_INV_ALL_REG, 0xffff);
+ /*
+ * Invalidate all SCU cache tags. That is, for all cores (0-3)
+ */
+ bus_space_write_4(iot, scu_ioh, SCU_INV_ALL_REG, 0xffff);
- uint32_t diagctl = bus_space_read_4(iot, scu_ioh, SCU_DIAG_CONTROL);
- diagctl |= SCU_DIAG_DISABLE_MIGBIT;
- bus_space_write_4(iot, scu_ioh, SCU_DIAG_CONTROL, diagctl);
+ uint32_t diagctl = bus_space_read_4(iot, scu_ioh, SCU_DIAG_CONTROL);
+ diagctl |= SCU_DIAG_DISABLE_MIGBIT;
+ bus_space_write_4(iot, scu_ioh, SCU_DIAG_CONTROL, diagctl);
- uint32_t scu_ctl = bus_space_read_4(iot, scu_ioh, SCU_CTL);
- scu_ctl |= SCU_CTL_SCU_ENA;
- bus_space_write_4(iot, scu_ioh, SCU_CTL, scu_ctl);
+ uint32_t scu_ctl = bus_space_read_4(iot, scu_ioh, SCU_CTL);
+ scu_ctl |= SCU_CTL_SCU_ENA;
+ bus_space_write_4(iot, scu_ioh, SCU_CTL, scu_ctl);
+
+ armv7_dcache_wbinv_all();
+ }
- armv7_dcache_wbinv_all();
-#endif
bus_space_handle_t wugen_ioh;
error = bus_space_map(iot, OMAP4_WUGEN_BASE, OMAP4_WUGEN_SIZE, 0,
&wugen_ioh);
