Module Name: src Committed By: rin Date: Thu Oct 15 22:41:02 UTC 2020
Modified Files: src/sys/arch/aarch64/aarch64: netbsd32_machdep.c Log Message: For rev 1.14 and before, netbsd32_process_write_regs() returns EINVAL if non-modifiable bits are set in CPSR. Instead, mask out non-modifiable bits and make this function success regardless of value in CPSR. New behavior matches that of arm: https://nxr.netbsd.org/xref/src/sys/arch/arm/arm/process_machdep.c#187 This fixes lib/libc/sys/t_ptrace_wait*:access_regs6 tests, in which register contents retrieved by PT_GETREGS are set back by PT_SETREGS. No new regression is observed in full ATF run. OK ryo To generate a diff of this commit: cvs rdiff -u -r1.14 -r1.15 src/sys/arch/aarch64/aarch64/netbsd32_machdep.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/aarch64/aarch64/netbsd32_machdep.c diff -u src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.14 src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.15 --- src/sys/arch/aarch64/aarch64/netbsd32_machdep.c:1.14 Thu Jul 2 13:04:46 2020 +++ src/sys/arch/aarch64/aarch64/netbsd32_machdep.c Thu Oct 15 22:41:02 2020 @@ -1,4 +1,4 @@ -/* $NetBSD: netbsd32_machdep.c,v 1.14 2020/07/02 13:04:46 rin Exp $ */ +/* $NetBSD: netbsd32_machdep.c,v 1.15 2020/10/15 22:41:02 rin Exp $ */ /* * Copyright (c) 2018 Ryo Shimizu <r...@nerv.org> @@ -27,7 +27,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.14 2020/07/02 13:04:46 rin Exp $"); +__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.15 2020/10/15 22:41:02 rin Exp $"); #if defined(_KERNEL_OPT) #include "opt_compat_netbsd.h" @@ -198,8 +198,7 @@ netbsd32_process_write_regs(struct lwp * if ((p->p_flag & PK_32) == 0) return EINVAL; - if ((regs->r_cpsr & ~(SPSR_NZCV | SPSR_A32_T)) != 0 || - regs->r_pc >= VM_MAXUSER_ADDRESS32 || + if (regs->r_pc >= VM_MAXUSER_ADDRESS32 || regs->r_sp >= VM_MAXUSER_ADDRESS32) return EINVAL; @@ -209,7 +208,7 @@ netbsd32_process_write_regs(struct lwp * tf->tf_reg[14] = regs->r_lr; /* r14 = lr */ tf->tf_pc = regs->r_pc; /* r15 = pc */ tf->tf_spsr &= ~(SPSR_NZCV | SPSR_A32_T); - tf->tf_spsr |= regs->r_cpsr; + tf->tf_spsr |= regs->r_cpsr & (SPSR_NZCV | SPSR_A32_T); /* THUMB CODE? */ if (regs->r_pc & 1)