Module Name: src
Committed By: nakayama
Date: Sat Feb 13 11:55:48 UTC 2010
Modified Files:
src/sys/arch/sparc64/dev: schizo.c schizoreg.h
Log Message:
Make 32-bit kernels compilable.
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/sparc64/dev/schizo.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/sparc64/dev/schizoreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/dev/schizo.c
diff -u src/sys/arch/sparc64/dev/schizo.c:1.13 src/sys/arch/sparc64/dev/schizo.c:1.14
--- src/sys/arch/sparc64/dev/schizo.c:1.13 Sat Feb 6 00:23:30 2010
+++ src/sys/arch/sparc64/dev/schizo.c Sat Feb 13 11:55:48 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: schizo.c,v 1.13 2010/02/06 00:23:30 mrg Exp $ */
+/* $NetBSD: schizo.c,v 1.14 2010/02/13 11:55:48 nakayama Exp $ */
/* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */
/*
@@ -141,7 +141,7 @@
int *busranges = NULL, nranges;
char *str;
- printf(": addr %lx", ma->ma_reg[0].ur_paddr);
+ printf(": addr %" PRIx64, ma->ma_reg[0].ur_paddr);
str = prom_getpropstring(ma->ma_node, "compatible");
if (strcmp(str, "pci108e,a801") == 0)
sc->sc_tomatillo = 1;
@@ -315,7 +315,7 @@
snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr);
printf("PCIAFSR=%s\n", bits);
- printf("PCIAFAR=%lx\n", afar);
+ printf("PCIAFAR=%" PRIx64 "\n", afar);
snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl);
printf("PCICTRL=%s\n", bits);
#ifdef PCI_COMMAND_STATUS_BITS
@@ -325,14 +325,14 @@
if (ctrl & SCZ_PCICTRL_MMU_ERR) {
ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL);
- printf("IOMMUCTRL=%lx\n", ctrl);
+ printf("IOMMUCTRL=%" PRIx64 "\n", ctrl);
if ((ctrl & TOM_IOMMU_ERR) == 0)
goto clear_error;
if (sc->sc_tomatillo) {
tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR);
- printf("IOMMUTFAR=%lx\n", tfar);
+ printf("IOMMUTFAR=%" PRIx64 "\n", tfar);
}
/* These are non-fatal if target abort was signalled. */
@@ -362,11 +362,11 @@
printf("%s: safari error\n", sc->sc_dv.dv_xname);
- printf("ERRLOG=%lx\n", schizo_read(sc, SCZ_SAFARI_ERRLOG));
- printf("UE_AFSR=%lx\n", schizo_read(sc, SCZ_UE_AFSR));
- printf("UE_AFAR=%lx\n", schizo_read(sc, SCZ_UE_AFAR));
- printf("CE_AFSR=%lx\n", schizo_read(sc, SCZ_CE_AFSR));
- printf("CE_AFAR=%lx\n", schizo_read(sc, SCZ_CE_AFAR));
+ printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG));
+ printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR));
+ printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR));
+ printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR));
+ printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR));
panic("%s: fatal", sc->sc_dv.dv_xname);
return (1);
@@ -494,7 +494,8 @@
clroff = offsetof(struct schizo_pbm_regs, iclr[ino]);
ino |= sc->sc_ign;
- DPRINTF(SDB_INTR, (" mapoff %lx clroff %lx\n", mapoff, clroff));
+ DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n",
+ mapoff, clroff));
ih = (struct intrhand *)
malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT);
@@ -502,8 +503,8 @@
return;
ih->ih_arg = arg;
intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh);
- ih->ih_map = (uint64_t *)(intrregs + mapoff);
- ih->ih_clr = (uint64_t *)(intrregs + clroff);
+ ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff);
+ ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff);
ih->ih_fun = handler;
ih->ih_pil = (1<<ipl);
ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff));
@@ -739,12 +740,12 @@
mapoff = offsetof(struct schizo_pbm_regs, imap[ino]);
clroff = offsetof(struct schizo_pbm_regs, iclr[ino]);
- DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %lx clroff %lx\n",
- __func__, ino, intrlev[ino], mapoff, clroff));
+ DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %"
+ PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff));
intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh);
- intrmapptr = (uint64_t *)(intrregs + mapoff);
- intrclrptr = (uint64_t *)(intrregs + clroff);
+ intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff);
+ intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff);
if (INTIGN(vec) == 0)
ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN;
Index: src/sys/arch/sparc64/dev/schizoreg.h
diff -u src/sys/arch/sparc64/dev/schizoreg.h:1.5 src/sys/arch/sparc64/dev/schizoreg.h:1.6
--- src/sys/arch/sparc64/dev/schizoreg.h:1.5 Sat Dec 13 21:00:09 2008
+++ src/sys/arch/sparc64/dev/schizoreg.h Sat Feb 13 11:55:48 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: schizoreg.h,v 1.5 2008/12/13 21:00:09 mrg Exp $ */
+/* $NetBSD: schizoreg.h,v 1.6 2010/02/13 11:55:48 nakayama Exp $ */
/* $OpenBSD: schizoreg.h,v 1.20 2008/07/12 13:08:04 kettenis Exp $ */
/*
@@ -201,17 +201,17 @@
#define SCZ_CEAFAR_PIO_PCIAC 0x0000038000000000UL /* pcib: config / i/o */
#define SCZ_CEAFAR_MEMADDR 0x000007fffffffff0UL /* memory address */
-#define SCZ_PCICTRL_BUS_UNUS (1UL << 63UL) /* bus unusable */
-#define TOM_PCICTRL_DTO_ERR (1UL << 62UL) /* pci discard timeout */
-#define TOM_PCICTRL_DTO_INT (1UL << 61UL) /* discard intr en */
-#define SCZ_PCICTRL_ESLCK (1UL << 51UL) /* error slot locked */
-#define SCZ_PCICTRL_ERRSLOT (7UL << 48UL) /* error slot */
-#define SCZ_PCICTRL_TTO_ERR (1UL << 38UL) /* pci trdy# timeout */
-#define SCZ_PCICTRL_RTRY_ERR (1UL << 37UL) /* pci rtry# timeout */
-#define SCZ_PCICTRL_MMU_ERR (1UL << 36UL) /* pci mmu error */
-#define SCZ_PCICTRL_SBH_ERR (1UL << 35UL) /* pci strm hole */
-#define SCZ_PCICTRL_SERR (1UL << 34UL) /* pci serr# sampled */
-#define SCZ_PCICTRL_PCISPD (1UL << 33UL) /* speed (0=clk/2,1=clk) */
+#define SCZ_PCICTRL_BUS_UNUS (1ULL << 63UL) /* bus unusable */
+#define TOM_PCICTRL_DTO_ERR (1ULL << 62UL) /* pci discard timeout */
+#define TOM_PCICTRL_DTO_INT (1ULL << 61UL) /* discard intr en */
+#define SCZ_PCICTRL_ESLCK (1ULL << 51UL) /* error slot locked */
+#define SCZ_PCICTRL_ERRSLOT (7ULL << 48UL) /* error slot */
+#define SCZ_PCICTRL_TTO_ERR (1ULL << 38UL) /* pci trdy# timeout */
+#define SCZ_PCICTRL_RTRY_ERR (1ULL << 37UL) /* pci rtry# timeout */
+#define SCZ_PCICTRL_MMU_ERR (1ULL << 36UL) /* pci mmu error */
+#define SCZ_PCICTRL_SBH_ERR (1ULL << 35UL) /* pci strm hole */
+#define SCZ_PCICTRL_SERR (1ULL << 34UL) /* pci serr# sampled */
+#define SCZ_PCICTRL_PCISPD (1ULL << 33UL) /* speed (0=clk/2,1=clk) */
#define SCZ_PCICTRL_PTO (3UL << 24UL) /* pci timeout interval */
#define SCZ_PCICTRL_MMU_INT (1UL << 19UL) /* mmu intr en */
#define SCZ_PCICTRL_SBH_INT (1UL << 18UL) /* strm byte hole intr en */
