Module Name: src
Committed By: skrll
Date: Sat Nov 21 19:46:13 UTC 2020
Modified Files:
src/sys/arch/arm/arm32: exception.S irq_dispatch.S
Log Message:
Sprinkle some comments about ENABLE_ALIGNMENT_FAULTS leaving curcpu in r4
and curlwp in r5
To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/arm/arm32/exception.S
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/arm/arm32/irq_dispatch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/exception.S
diff -u src/sys/arch/arm/arm32/exception.S:1.25 src/sys/arch/arm/arm32/exception.S:1.26
--- src/sys/arch/arm/arm32/exception.S:1.25 Sun Aug 11 06:49:31 2019
+++ src/sys/arch/arm/arm32/exception.S Sat Nov 21 19:46:13 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: exception.S,v 1.25 2019/08/11 06:49:31 skrll Exp $ */
+/* $NetBSD: exception.S,v 1.26 2020/11/21 19:46:13 skrll Exp $ */
/*
* Copyright (c) 1994-1997 Mark Brinicombe.
@@ -51,7 +51,7 @@
#include <arm/locore.h>
- RCSID("$NetBSD: exception.S,v 1.25 2019/08/11 06:49:31 skrll Exp $")
+ RCSID("$NetBSD: exception.S,v 1.26 2020/11/21 19:46:13 skrll Exp $")
.text
.align 0
@@ -80,7 +80,7 @@ ASEND(reset_entry)
*/
ARM_ASENTRY_NP(swi_entry)
PUSHFRAME
- ENABLE_ALIGNMENT_FAULTS
+ ENABLE_ALIGNMENT_FAULTS /* puts cur{cpu,lwp} in r4/r5 */
mov r0, sp /* Pass the frame to any function */
bl _C_LABEL(swi_handler) /* It's a SWI ! */
@@ -111,7 +111,7 @@ ARM_ASENTRY_NP(prefetch_abort_entry)
clrex
#endif
PUSHFRAMEINSVC
- ENABLE_ALIGNMENT_FAULTS
+ ENABLE_ALIGNMENT_FAULTS /* puts cur{cpu,lwp} in r4/r5 */
ldr r1, .Lprefetch_abort_handler_address
adr lr, .Lexception_exit
@@ -158,7 +158,7 @@ ASENTRY_NP(data_abort_entry)
#endif
PUSHFRAMEINSVC /* Push trap frame and switch */
/* to SVC32 mode */
- ENABLE_ALIGNMENT_FAULTS
+ ENABLE_ALIGNMENT_FAULTS /* puts cur{cpu,lwp} in r4/r5 */
ldr r1, .Ldata_abort_handler_address
adr lr, .Lexception_exit
@@ -261,7 +261,7 @@ ENTRY_NP(undefinedinstruction_bounce)
PUSHXXXREGSANDSWITCH
PUSHDTRACEGAP
PUSHTRAPFRAME(r2)
- ENABLE_ALIGNMENT_FAULTS
+ ENABLE_ALIGNMENT_FAULTS /* puts cur{cpu,lwp} in r4/r5 */
mov r0, sp
adr lr, .Lexception_exit
Index: src/sys/arch/arm/arm32/irq_dispatch.S
diff -u src/sys/arch/arm/arm32/irq_dispatch.S:1.16 src/sys/arch/arm/arm32/irq_dispatch.S:1.17
--- src/sys/arch/arm/arm32/irq_dispatch.S:1.16 Tue Jun 2 14:06:16 2015
+++ src/sys/arch/arm/arm32/irq_dispatch.S Sat Nov 21 19:46:13 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: irq_dispatch.S,v 1.16 2015/06/02 14:06:16 matt Exp $ */
+/* $NetBSD: irq_dispatch.S,v 1.17 2020/11/21 19:46:13 skrll Exp $ */
/*
* Copyright (c) 2002 Fujitsu Component Limited
@@ -95,7 +95,7 @@ ARM_ASENTRY_NP(irq_entry)
sub lr, lr, #0x00000004 /* Adjust the lr */
PUSHFRAMEINSVC /* Push an interrupt frame */
- ENABLE_ALIGNMENT_FAULTS /* finishes with curcpu() in r4 */
+ ENABLE_ALIGNMENT_FAULTS /* puts cur{cpu,lwp} in r4/r5 */
#ifdef _ARM_ARCH_7
clrex /* force all strex to fail */
@@ -108,7 +108,8 @@ ARM_ASENTRY_NP(irq_entry)
* callee-saved regs here. We use the following registers, which
* we expect to persist:
*
- * r4 address of current cpu_info
+ * r4 address of current cpu_info (curcpu)
+ * r5 address of current lwp (curlwp)
* r6 old value of `ci_intr_depth'
*/
ldr r6, [r4, #CI_INTR_DEPTH]
