Module Name: src
Committed By: skrll
Date: Mon Dec 28 13:12:24 UTC 2020
Modified Files:
src/sys/dev/pci: pcireg.h
Log Message:
Add second space indentation for bit field values for Enhanced Allocation
capabilities. From thorpej.
To generate a diff of this commit:
cvs rdiff -u -r1.152 -r1.153 src/sys/dev/pci/pcireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/pcireg.h
diff -u src/sys/dev/pci/pcireg.h:1.152 src/sys/dev/pci/pcireg.h:1.153
--- src/sys/dev/pci/pcireg.h:1.152 Mon Dec 28 12:38:44 2020
+++ src/sys/dev/pci/pcireg.h Mon Dec 28 13:12:24 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: pcireg.h,v 1.152 2020/12/28 12:38:44 skrll Exp $ */
+/* $NetBSD: pcireg.h,v 1.153 2020/12/28 13:12:24 skrll Exp $ */
/*
* Copyright (c) 1995, 1996, 1999, 2000
@@ -1878,38 +1878,36 @@ struct pci_rom {
/* Bit definitions for the first DW of each entry */
#define PCI_EA_ES __BITS(2, 0) /* Entry Size */
#define PCI_EA_BEI __BITS(7, 4) /* BAR Equivalent Indicator */
-#define PCI_EA_BEI_BAR0 0 /* BAR0 (10h) */
-#define PCI_EA_BEI_BAR1 1 /* BAR1 (14h) */
-#define PCI_EA_BEI_BAR2 2 /* BAR2 (18h) */
-#define PCI_EA_BEI_BAR3 3 /* BAR3 (1ch) */
-#define PCI_EA_BEI_BAR4 4 /* BAR4 (20h) */
-#define PCI_EA_BEI_BAR5 5 /* BAR5 (24h) */
-#define PCI_EA_BEI_BEHIND 6 /* Behind the function (for type1) */
-#define PCI_EA_BEI_NOTIND 7 /* Not Indicated */
-#define PCI_EA_BEI_EXPROM 8 /* Expansion ROM */
-#define PCI_EA_BEI_VFBAR0 9 /* VF BAR0 */
-#define PCI_EA_BEI_VFBAR1 10 /* VF BAR1 */
-#define PCI_EA_BEI_VFBAR2 11 /* VF BAR2 */
-#define PCI_EA_BEI_VFBAR3 12 /* VF BAR3 */
-#define PCI_EA_BEI_VFBAR4 13 /* VF BAR4 */
-#define PCI_EA_BEI_VFBAR5 14 /* VF BAR5 */
-#define PCI_EA_BEI_RESERVED 15 /* Reserved (treat as Not Indicated) */
-
+#define PCI_EA_BEI_BAR0 0 /* BAR0 (10h) */
+#define PCI_EA_BEI_BAR1 1 /* BAR1 (14h) */
+#define PCI_EA_BEI_BAR2 2 /* BAR2 (18h) */
+#define PCI_EA_BEI_BAR3 3 /* BAR3 (1ch) */
+#define PCI_EA_BEI_BAR4 4 /* BAR4 (20h) */
+#define PCI_EA_BEI_BAR5 5 /* BAR5 (24h) */
+#define PCI_EA_BEI_BEHIND 6 /* Behind the function (for type1) */
+#define PCI_EA_BEI_NOTIND 7 /* Not Indicated */
+#define PCI_EA_BEI_EXPROM 8 /* Expansion ROM */
+#define PCI_EA_BEI_VFBAR0 9 /* VF BAR0 */
+#define PCI_EA_BEI_VFBAR1 10 /* VF BAR1 */
+#define PCI_EA_BEI_VFBAR2 11 /* VF BAR2 */
+#define PCI_EA_BEI_VFBAR3 12 /* VF BAR3 */
+#define PCI_EA_BEI_VFBAR4 13 /* VF BAR4 */
+#define PCI_EA_BEI_VFBAR5 14 /* VF BAR5 */
+#define PCI_EA_BEI_RESERVED 15 /* Reserved (treat as Not Indicated) */
#define PCI_EA_PP __BITS(15, 8) /* Primary Properties */
#define PCI_EA_SP __BITS(23, 16) /* Secondary Properties */
/* PP and SP's values */
-#define PCI_EA_PROP_MEM_NONPREF 0x00 /* Memory Space, Non-Prefetchable */
-#define PCI_EA_PROP_MEM_PREF 0x01 /* Memory Space, Prefetchable */
-#define PCI_EA_PROP_IO 0x02 /* I/O Space */
-#define PCI_EA_PROP_VF_MEM_NONPREF 0x03 /* Resorce for VF use. Mem. Non-Pref */
-#define PCI_EA_PROP_VF_MEM_PREF 0x04 /* Resorce for VF use. Mem. Prefetch */
-#define PCI_EA_PROP_BB_MEM_NONPREF 0x05 /* Behind Bridge: MEM. Non-Pref */
-#define PCI_EA_PROP_BB_MEM_PREF 0x06 /* Behind Bridge: MEM. Prefetch */
-#define PCI_EA_PROP_BB_IO 0x07 /* Behind Bridge: I/O Space */
-#define PCI_EA_PROP_MEM_UNAVAIL 0xfd /* Memory Space Unavailable */
-#define PCI_EA_PROP_IO_UNAVAIL 0xfe /* IO Space Unavailable */
-#define PCI_EA_PROP_UNAVAIL 0xff /* Entry Unavailable for use */
-
+#define PCI_EA_PROP_MEM_NONPREF 0x00 /* Memory Space, Non-Prefetchable */
+#define PCI_EA_PROP_MEM_PREF 0x01 /* Memory Space, Prefetchable */
+#define PCI_EA_PROP_IO 0x02 /* I/O Space */
+#define PCI_EA_PROP_VF_MEM_NONPREF 0x03 /* Resorce for VF use. Mem. Non-Pref */
+#define PCI_EA_PROP_VF_MEM_PREF 0x04 /* Resorce for VF use. Mem. Prefetch */
+#define PCI_EA_PROP_BB_MEM_NONPREF 0x05 /* Behind Bridge: MEM. Non-Pref */
+#define PCI_EA_PROP_BB_MEM_PREF 0x06 /* Behind Bridge: MEM. Prefetch */
+#define PCI_EA_PROP_BB_IO 0x07 /* Behind Bridge: I/O Space */
+#define PCI_EA_PROP_MEM_UNAVAIL 0xfd /* Memory Space Unavailable */
+#define PCI_EA_PROP_IO_UNAVAIL 0xfe /* IO Space Unavailable */
+#define PCI_EA_PROP_UNAVAIL 0xff /* Entry Unavailable for use */
#define PCI_EA_W __BIT(30) /* Writable */
#define PCI_EA_E __BIT(31) /* Enable for this entry */
