Module Name: src
Committed By: mrg
Date: Tue Feb 23 05:32:09 UTC 2010
Modified Files:
src/sys/arch/sparc64/sparc64: db_interface.c db_tlb_access.S
Log Message:
change print_dtlb() and print_itlb() to take (tlb_size, tlb_selectbits).
for cheetah, print the 3 dtlb's and 2 itlb's.
now "mach dtlb" and "mach itlb" work for cheetah.
To generate a diff of this commit:
cvs rdiff -u -r1.121 -r1.122 src/sys/arch/sparc64/sparc64/db_interface.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/sparc64/sparc64/db_tlb_access.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/sparc64/db_interface.c
diff -u src/sys/arch/sparc64/sparc64/db_interface.c:1.121 src/sys/arch/sparc64/sparc64/db_interface.c:1.122
--- src/sys/arch/sparc64/sparc64/db_interface.c:1.121 Tue Feb 2 04:28:56 2010
+++ src/sys/arch/sparc64/sparc64/db_interface.c Tue Feb 23 05:32:08 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.121 2010/02/02 04:28:56 mrg Exp $ */
+/* $NetBSD: db_interface.c,v 1.122 2010/02/23 05:32:08 mrg Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath. All rights reserved.
@@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.121 2010/02/02 04:28:56 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.122 2010/02/23 05:32:08 mrg Exp $");
#include "opt_ddb.h"
#include "opt_multiprocessor.h"
@@ -571,20 +571,49 @@
prom_abort();
}
+/*
+ * Dump the [ID]TLB's.
+ *
+ * Spitfire has 64 entry TLBs for instruction and data.
+ *
+ * Cheetah has 5 TLBs in total:
+ * instruction tlbs - it16, it128 -- 16 and 128 entry TLBs
+ * data tlbs - dt16, dt512_0, dt512_1 -- 16, and 2*512 entry TLBs
+ *
+ * The TLB chosen is chosen depending on the values in bits 16/17,
+ * and the address is the index shifted 3 bits left.
+ *
+ * These are in db_tlb_access.S:
+ * void print_dtlb(size_t tlbsize, int tlbmask)
+ * void print_itlb(size_t tlbsize, int tlbmask)
+ */
+
void
db_dump_dtlb(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
{
- extern void print_dtlb(void);
+ extern void print_dtlb(size_t, int);
- print_dtlb();
+ if (CPU_IS_USIII_UP()) {
+ print_dtlb(TLB_SIZE_CHEETAH_D16, TLB_CHEETAH_D16);
+ db_printf("DT512_0:\n");
+ print_dtlb(TLB_SIZE_CHEETAH_D512_0, TLB_CHEETAH_D512_0);
+ db_printf("DT512_1:\n");
+ print_dtlb(TLB_SIZE_CHEETAH_D512_1, TLB_CHEETAH_D512_1);
+ } else
+ print_dtlb(TLB_SIZE_SPITFIRE, 0);
}
void
db_dump_itlb(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
{
- extern void print_itlb(void);
+ extern void print_itlb(size_t, int);
- print_itlb();
+ if (CPU_IS_USIII_UP()) {
+ print_itlb(TLB_SIZE_CHEETAH_I16, TLB_CHEETAH_I16);
+ db_printf("IT128:\n");
+ print_itlb(TLB_SIZE_CHEETAH_I128, TLB_CHEETAH_I128);
+ } else
+ print_itlb(TLB_SIZE_SPITFIRE, 0);
}
void
@@ -679,7 +708,7 @@
if ((data = pseg_get(pmap_kernel(), (vaddr_t)addr))) {
db_printf("pmap_kernel(%p)->pm_segs[%lx][%lx][%lx]=>%qx\n",
- (void *)(uintptr_t)addr, (u_long)va_to_seg(addr),
+ (void *)(uintptr_t)addr, (u_long)va_to_seg(addr),
(u_long)va_to_dir(addr), (u_long)va_to_pte(addr),
(unsigned long long)data);
} else {
@@ -815,7 +844,7 @@
struct lwp *l;
l = curlwp;
- if (have_addr)
+ if (have_addr)
l = (struct lwp*)(uintptr_t)addr;
if (l == NULL) {
db_printf("no current lwp\n");
@@ -836,7 +865,7 @@
if (curlwp)
p = curlwp->l_proc;
- if (have_addr)
+ if (have_addr)
p = (struct proc*)(uintptr_t)addr;
if (p == NULL) {
db_printf("no current process\n");
@@ -847,7 +876,7 @@
p->p_pid, p->p_vmspace, p->p_vmspace->vm_map.pmap,
pmap_ctx(p->p_vmspace->vm_map.pmap));
db_printf("maxsaddr:%p ssiz:%dpg or %llxB\n",
- p->p_vmspace->vm_maxsaddr, p->p_vmspace->vm_ssize,
+ p->p_vmspace->vm_maxsaddr, p->p_vmspace->vm_ssize,
(unsigned long long)ctob(p->p_vmspace->vm_ssize));
db_printf("profile timer: %" PRId64 " sec %ld nsec\n",
p->p_stats->p_timer[ITIMER_PROF].it_value.tv_sec,
@@ -889,7 +918,7 @@
int i;
pcb = curpcb;
- if (have_addr)
+ if (have_addr)
pcb = (struct pcb*)(uintptr_t)addr;
db_printf("p...@%p sp:%p pc:%p cwp:%d pil:%d nsaved:%x onfault:%p\nlastcall:%s\nfull windows:\n",
@@ -898,7 +927,7 @@
(pcb->lastcall)?pcb->lastcall:"Null");
for (i=0; i<pcb->pcb_nsaved; i++) {
- db_printf("win %d: at %llx local, in\n", i,
+ db_printf("win %d: at %llx local, in\n", i,
(unsigned long long)pcb->pcb_rw[i+1].rw_in[6]);
db_printf("%16llx %16llx %16llx %16llx\n",
(unsigned long long)pcb->pcb_rw[i].rw_local[0],
@@ -934,7 +963,7 @@
db_printf("What PID do you want to map in?\n");
return;
}
-
+
LIST_FOREACH(p, &allproc, p_list) {
pp = p->p_pptr;
if (p->p_stat && p->p_pid == addr) {
@@ -976,9 +1005,9 @@
static void
db_print_trace_entry(struct traptrace *te, int i)
{
- db_printf("%d:%d p:%d tt:%x:%llx:%llx %llx:%llx ", i,
- (int)te->tl, (int)te->pid,
- (int)te->tt, (unsigned long long)te->tstate,
+ db_printf("%d:%d p:%d tt:%x:%llx:%llx %llx:%llx ", i,
+ (int)te->tl, (int)te->pid,
+ (int)te->tt, (unsigned long long)te->tstate,
(unsigned long long)te->tfault, (unsigned long long)te->tsp,
(unsigned long long)te->tpc);
db_printsym((u_long)te->tpc, DB_STGY_PROC, db_printf);
@@ -1041,12 +1070,12 @@
}
}
-/*
+/*
* Use physical or virtul watchpoint registers -- ugh
*
* UltraSPARC I and II have both a virtual and physical
- * watchpoint register. They are controlled by the LSU
- * control register.
+ * watchpoint register. They are controlled by the LSU
+ * control register.
*/
void
db_watch(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
Index: src/sys/arch/sparc64/sparc64/db_tlb_access.S
diff -u src/sys/arch/sparc64/sparc64/db_tlb_access.S:1.1 src/sys/arch/sparc64/sparc64/db_tlb_access.S:1.2
--- src/sys/arch/sparc64/sparc64/db_tlb_access.S:1.1 Mon Feb 22 22:28:58 2010
+++ src/sys/arch/sparc64/sparc64/db_tlb_access.S Tue Feb 23 05:32:08 2010
@@ -1,10 +1,10 @@
-/* $NetBSD: db_tlb_access.S,v 1.1 2010/02/22 22:28:58 mrg Exp $ */
+/* $NetBSD: db_tlb_access.S,v 1.2 2010/02/23 05:32:08 mrg Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
+ * Copyright (c) 2010 Matthew R. Green
* All rights reserved.
*
- *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@@ -25,65 +25,19 @@
*
*/
-#include "opt_ddb.h"
-
#include <machine/ctlreg.h>
#include <machine/asm.h>
-#ifdef DDB
-!!!
-!!! Dump the DTLB to phys address in %o0 and print it
-!!!
-!!! Only toast a few %o registers
-!!!
-
-ENTRY_NOPROFILE(dump_dtlb)
- clr %o1
- add %o1, (64 * 8), %o3 ! XXX TLB_SIZE
-1:
- ldxa [%o1] ASI_DMMU_TLB_TAG, %o2
- membar #Sync
- stx %o2, [%o0]
- membar #Sync
- inc 8, %o0
- ldxa [%o1] ASI_DMMU_TLB_DATA, %o4
- membar #Sync
- inc 8, %o1
- stx %o4, [%o0]
- cmp %o1, %o3
- membar #Sync
- bl 1b
- inc 8, %o0
-
- retl
- nop
-
-ENTRY_NOPROFILE(dump_itlb)
- clr %o1
- add %o1, (64 * 8), %o3 ! XXX TLB_SIZE
-1:
- ldxa [%o1] ASI_IMMU_TLB_TAG, %o2
- membar #Sync
- stx %o2, [%o0]
- membar #Sync
- inc 8, %o0
- ldxa [%o1] ASI_IMMU_TLB_DATA, %o4
- membar #Sync
- inc 8, %o1
- stx %o4, [%o0]
- cmp %o1, %o3
- membar #Sync
- bl 1b
- inc 8, %o0
-
- retl
- nop
+/*
+ * Basic routines to print the I/D-TLB tag & data info.
+ */
#ifdef _LP64
ENTRY_NOPROFILE(print_dtlb)
save %sp, -CC64FSZ, %sp
- clr %l1
- add %l1, (64 * 8), %l3 ! XXX TLB_SIZE
+ sll %i0, 3, %l3
+ or %l3, %i1, %l3
+ mov %i1, %l1
clr %l2
1:
ldxa [%l1] ASI_DMMU_TLB_TAG, %o2
@@ -113,11 +67,11 @@
ret
restore
-
ENTRY_NOPROFILE(print_itlb)
save %sp, -CC64FSZ, %sp
- clr %l1
- add %l1, (64 * 8), %l3 ! XXX TLB_SIZE
+ sll %i0, 3, %l3
+ or %l3, %i1, %l3
+ mov %i1, %l1
clr %l2
1:
ldxa [%l1] ASI_IMMU_TLB_TAG, %o2
@@ -156,8 +110,9 @@
#else
ENTRY_NOPROFILE(print_dtlb)
save %sp, -CC64FSZ, %sp
- clr %l1
- add %l1, (64 * 8), %l3 ! XXX TLB_SIZE
+ sll %i0, 3, %l3
+ or %l3, %i1, %l3
+ mov %i1, %l1
clr %l2
1:
ldxa [%l1] ASI_DMMU_TLB_TAG, %o2
@@ -197,8 +152,9 @@
ENTRY_NOPROFILE(print_itlb)
save %sp, -CC64FSZ, %sp
- clr %l1
- add %l1, (64 * 8), %l3 ! XXX TLB_SIZE
+ sll %i0, 3, %l3
+ or %l3, %i1, %l3
+ mov %i1, %l1
clr %l2
1:
ldxa [%l1] ASI_IMMU_TLB_TAG, %o2
@@ -243,4 +199,3 @@
.asciz "%2d:%08x:%08x %08x:%08x\r\n"
.text
#endif
-#endif
