Module Name: src
Committed By: simonb
Date: Wed Jan 27 05:24:16 UTC 2021
Added Files:
src/sys/arch/evbmips/conf: MIPSSIM MIPSSIM64 files.mipssim std.mipssim
src/sys/arch/evbmips/mipssim: autoconf.c autoconf.h com_mainbus.c
if_mipsnetreg.h machdep.c mainbus.c mipssim_bus_io.c mipssim_intr.c
mipssimreg.h mipssimvar.h
Log Message:
Add support for the QEMU MIPS "mipssim" simulator.
TODO- mipsnet network driver (root on md(4) only for now).
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbmips/conf/MIPSSIM \
src/sys/arch/evbmips/conf/MIPSSIM64 \
src/sys/arch/evbmips/conf/files.mipssim \
src/sys/arch/evbmips/conf/std.mipssim
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbmips/mipssim/autoconf.c \
src/sys/arch/evbmips/mipssim/autoconf.h \
src/sys/arch/evbmips/mipssim/com_mainbus.c \
src/sys/arch/evbmips/mipssim/if_mipsnetreg.h \
src/sys/arch/evbmips/mipssim/machdep.c \
src/sys/arch/evbmips/mipssim/mainbus.c \
src/sys/arch/evbmips/mipssim/mipssim_bus_io.c \
src/sys/arch/evbmips/mipssim/mipssim_intr.c \
src/sys/arch/evbmips/mipssim/mipssimreg.h \
src/sys/arch/evbmips/mipssim/mipssimvar.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/evbmips/conf/MIPSSIM
diff -u /dev/null src/sys/arch/evbmips/conf/MIPSSIM:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/conf/MIPSSIM Wed Jan 27 05:24:16 2021
@@ -0,0 +1,128 @@
+# $NetBSD: MIPSSIM,v 1.1 2021/01/27 05:24:16 simonb Exp $
+#
+# Kernel config for the QEMU MIPS "mipssim" simulator
+
+include "arch/evbmips/conf/std.mipssim"
+
+#ident "GENERIC-$Revision: 1.1 $"
+
+maxusers 32
+
+options MIPS32
+options MIPS32R2
+options NOFPU # No FPU
+options FPEMUL # emulate FPU insn
+options HZ=512 # for profiling
+
+#options LOCKDEBUG
+options SOSEND_COUNTERS
+options INET_CSUM_COUNTERS
+options TCP_CSUM_COUNTERS
+options UDP_CSUM_COUNTERS
+options TCP_OUTPUT_COUNTERS
+
+#options NTP # network time protocol
+
+# Debugging options
+options DIAGNOSTIC # extra kernel sanity checking
+options DEBUG # extra kernel debugging support
+options DDB # kernel dynamic debugger
+options DDB_HISTORY_SIZE=100 # enable history editing in DDB
+makeoptions DEBUG="-g" # compile full symbol table
+makeoptions COPY_SYMTAB=1 # size for embedded symbol table
+
+pseudo-device md # memory disk device
+options MEMORY_DISK_HOOKS
+options MEMORY_DISK_IS_ROOT # Force root on ram-disk
+options MEMORY_DISK_ROOT_SIZE=32768 # size of memory disk, in blocks
+
+# Compatibility options
+include "conf/compat_netbsd50.config"
+#options EXEC_ECOFF # exec ECOFF binaries
+#options COMPAT_ULTRIX # binary compatibility with Ultrix
+
+# File systems
+file-system FFS # Berkeley Fast Filesystem
+#file-system MFS # memory-based filesystem
+#file-system EXT2FS # second extended file system (linux)
+file-system NFS # Sun NFS-compatible filesystem client
+#file-system KERNFS # kernel data-structure filesystem
+#file-system NULLFS # NULL layered filesystem
+#file-system OVERLAY # overlay file system
+#file-system FDESC # user file descriptor filesystem
+#file-system UMAPFS # uid/gid remapping filesystem
+#file-system LFS # Log-based filesystem (still experimental)
+#file-system PROCFS # /proc
+#file-system CD9660 # ISO 9660 + Rock Ridge file system
+#file-system UNION # union file system
+#file-system MSDOSFS # MS-DOS FAT filesystem(s).
+#file-system CODA # Coda File System; also needs vcoda (below)
+file-system PTYFS # /dev/pts/N support
+
+# File system options
+#options NFSSERVER # Sun NFS-compatible filesystem server
+#options QUOTA # legacy UFS quotas
+#options QUOTA2 # new, in-filesystem UFS quotas
+#options DISKLABEL_EI # disklabel Endian Independent support
+#options FFS_EI # FFS Endian Independent support
+#options WAPBL # File system journaling support
+#options EXT2FS_SYSTEM_FLAGS # makes ext2fs file flags (append and
+ # immutable) behave as system flags.
+
+# Alternate buffer queue strategies for better responsiveness under high
+# disk I/O load.
+#options BUFQ_READPRIO
+#options BUFQ_PRIOCSCAN
+
+# Networking options
+#options GATEWAY # IP packet forwarding
+options INET # Internet protocols
+#options INET6 # IPV6
+#options IPSEC # IP security
+#options IPSEC_DEBUG # debug for IP security
+#options MROUTING # packet forwarding of multicast packets
+#options NETATALK # AppleTalk (over Ethernet) protocol
+#options PIM # Protocol Independent Multicast
+#options PPP_BSDCOMP # BSD-Compress compression support for PPP
+#options PPP_DEFLATE # Deflate compression support for PPP
+#options PPP_FILTER # Active filter support for PPP (requires bpf)
+
+# JIT compiler for bpfilter
+#options SLJIT
+#options BPFJIT
+
+# These options enable verbose messages for several subsystems.
+# Warning, these may compile large string tables into the kernel!
+#options MIIVERBOSE # verbose PHY autoconfig messages
+
+options NFS_BOOT_DHCP
+
+config netbsd root on ? type ?
+
+mainbus0 at root
+cpu* at mainbus?
+com* at mainbus?
+# mipsnet* at mainbus?
+# options MIPSSIM_ETH_MACADDR="ba:bb:1e:01:23:45"
+
+# Network pseudo-devices
+pseudo-device bpfilter # Berkeley packet filter
+#pseudo-device carp # Common Address Redundancy Protocol
+pseudo-device loop # network loopback
+#pseudo-device ppp # Point-to-Point Protocol
+#pseudo-device sl # Serial Line IP
+#pseudo-device tun # network tunneling over tty
+#pseudo-device gre # generic L3 over IP tunnel
+#pseudo-device ipip # RFC 2003 IP Encapsulation
+#pseudo-device gif # RFC1933 tunnel
+#pseudo-device faith # IPv[46] tcp relay translation
+# Miscellaneous pseudo-devices
+pseudo-device pty # pseudo-terminals
+#pseudo-device sequencer # MIDI sequencer
+
+# A pseudo device needed for Coda # also needs CODA (above)
+#pseudo-device vcoda # coda minicache <-> venus comm.
+pseudo-device clockctl # user control of clock subsystem
+pseudo-device ksyms # /dev/ksyms
+
+include "dev/veriexec.config"
Index: src/sys/arch/evbmips/conf/MIPSSIM64
diff -u /dev/null src/sys/arch/evbmips/conf/MIPSSIM64:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/conf/MIPSSIM64 Wed Jan 27 05:24:16 2021
@@ -0,0 +1,13 @@
+# $NetBSD: MIPSSIM64,v 1.1 2021/01/27 05:24:16 simonb Exp $
+#
+include "arch/evbmips/conf/MIPSSIM"
+
+makeoptions LP64="yes"
+
+no options MIPS32
+no options MIPS32R2
+
+options MIPS64
+options MIPS64R2
+options EXEC_ELF64
+options COMPAT_NETBSD32
Index: src/sys/arch/evbmips/conf/files.mipssim
diff -u /dev/null src/sys/arch/evbmips/conf/files.mipssim:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/conf/files.mipssim Wed Jan 27 05:24:16 2021
@@ -0,0 +1,31 @@
+# $NetBSD: files.mipssim,v 1.1 2021/01/27 05:24:16 simonb Exp $
+
+file arch/evbmips/mipssim/autoconf.c
+file arch/evbmips/mipssim/machdep.c
+file arch/evbmips/mipssim/mipssim_intr.c
+file arch/evbmips/mipssim/mipssim_bus_io.c
+
+file arch/evbmips/evbmips/interrupt.c
+
+file arch/mips/mips/mips3_clock.c
+file arch/mips/mips/mips3_clockintr.c
+
+# System bus
+device mainbus {}
+attach mainbus at root
+file arch/evbmips/mipssim/mainbus.c mainbus
+
+device cpu
+attach cpu at mainbus
+file arch/evbmips/evbmips/cpu.c cpu
+
+attach com at mainbus with com_mainbus
+file arch/evbmips/mipssim/com_mainbus.c com_mainbus
+
+device mipsnet: ether, ifnet, arp, mii
+attach mipsnet at mainbus
+file arch/evbmips/mipssim/if_mipsnet.c mipsnet
+defparam opt_mipsnet.h MIPSSIM_ETH_MACADDR
+
+# Memory Disk
+file dev/md_root.c memory_disk_hooks
Index: src/sys/arch/evbmips/conf/std.mipssim
diff -u /dev/null src/sys/arch/evbmips/conf/std.mipssim:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/conf/std.mipssim Wed Jan 27 05:24:16 2021
@@ -0,0 +1,15 @@
+# $NetBSD: std.mipssim,v 1.1 2021/01/27 05:24:16 simonb Exp $
+
+machine evbmips mips
+include "conf/std" # MI standard options
+
+options MIPS3_ENABLE_CLOCK_INTR
+options EVBMIPS_CLOCKSUBR
+
+options EXEC_ELF32 # exec ELF32 binaries
+options EXEC_SCRIPT # exec #! scripts
+
+makeoptions DEFTEXTADDR="0x80010000"
+makeoptions BOARDTYPE="mipssim"
+
+include "arch/evbmips/conf/files.mipssim"
Index: src/sys/arch/evbmips/mipssim/autoconf.c
diff -u /dev/null src/sys/arch/evbmips/mipssim/autoconf.c:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/mipssim/autoconf.c Wed Jan 27 05:24:16 2021
@@ -0,0 +1,70 @@
+/* $NetBSD: autoconf.c,v 1.1 2021/01/27 05:24:16 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2001,2021 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe and Simon Burge.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.1 2021/01/27 05:24:16 simonb Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+#include <sys/bus.h>
+
+/*
+ * Configure all devices on system
+ */
+void
+cpu_configure(void)
+{
+
+ intr_init();
+
+ /* Kick off autoconfiguration. */
+ (void)splhigh();
+ if (config_rootfound("mainbus", NULL) == NULL)
+ panic("no mainbus found");
+
+ spl0();
+}
+
+void
+cpu_rootconf(void)
+{
+
+ rootconf();
+}
+
+void
+device_register(device_t dev, void *aux)
+{
+
+ /* nothing to do here */
+}
Index: src/sys/arch/evbmips/mipssim/autoconf.h
diff -u /dev/null src/sys/arch/evbmips/mipssim/autoconf.h:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/mipssim/autoconf.h Wed Jan 27 05:24:16 2021
@@ -0,0 +1,45 @@
+/* $NetBSD: autoconf.h,v 1.1 2021/01/27 05:24:16 simonb Exp $ */
+
+/*
+ * Copyright 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/bus.h>
+
+struct mainbus_attach_args {
+ const char *ma_name;
+ unsigned long ma_addr;
+ int ma_irq;
+ bus_space_tag_t ma_iot;
+};
Index: src/sys/arch/evbmips/mipssim/com_mainbus.c
diff -u /dev/null src/sys/arch/evbmips/mipssim/com_mainbus.c:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/mipssim/com_mainbus.c Wed Jan 27 05:24:16 2021
@@ -0,0 +1,97 @@
+/* $NetBSD: com_mainbus.c,v 1.1 2021/01/27 05:24:16 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2001, 2021 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe and Simon Burge.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
+
+__KERNEL_RCSID(0, "$NetBSD: com_mainbus.c,v 1.1 2021/01/27 05:24:16 simonb Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+#include <sys/file.h>
+#include <sys/tty.h>
+
+#include <evbmips/mipssim/autoconf.h>
+
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+
+struct com_mainbus_softc {
+ struct com_softc sc_com; /* real "com" softc */
+
+ /* mainbus-specific goo. */
+ void *sc_ih; /* interrupt handler */
+};
+
+static int com_mainbus_match(device_t, cfdata_t , void *);
+static void com_mainbus_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(com_mainbus, sizeof(struct com_mainbus_softc),
+ com_mainbus_match, com_mainbus_attach, NULL, NULL);
+
+int
+com_mainbus_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct mainbus_attach_args *ma = aux;
+
+ /* Always present. */
+ if (strcmp(ma->ma_name, match->cf_name) == 0)
+ return (1);
+
+ return (0);
+}
+
+void
+com_mainbus_attach(device_t parent, device_t self, void *aux)
+{
+ struct com_mainbus_softc *msc = device_private(self);
+ struct com_softc *sc = &msc->sc_com;
+ struct mainbus_attach_args *ma = aux;
+ bus_space_handle_t ioh;
+
+ sc->sc_dev = self;
+ if (com_is_console(ma->ma_iot, ma->ma_addr, &ioh) == 0 &&
+ bus_space_map(ma->ma_iot, ma->ma_addr, COM_NPORTS, 0, &ioh) != 0) {
+ aprint_error(": can't map i/o space\n");
+ return;
+ }
+ com_init_regs(&sc->sc_regs, ma->ma_iot, ioh, ma->ma_addr);
+ sc->sc_frequency = COM_FREQ;
+
+ com_attach_subr(sc);
+
+ msc->sc_ih = evbmips_intr_establish(ma->ma_irq, comintr, sc);
+ if (msc->sc_ih == NULL) {
+ aprint_error_dev(self, "unable to establish interrupt\n");
+ return;
+ }
+}
Index: src/sys/arch/evbmips/mipssim/if_mipsnetreg.h
diff -u /dev/null src/sys/arch/evbmips/mipssim/if_mipsnetreg.h:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/mipssim/if_mipsnetreg.h Wed Jan 27 05:24:16 2021
@@ -0,0 +1,54 @@
+/* $NetBSD: if_mipsnetreg.h,v 1.1 2021/01/27 05:24:16 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2021 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Simon Burge.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * MIPSSIM emulator MIPSNET ethernet registers
+ */
+
+#define MN_DEVID0 0x00 /* device info */
+#define MN_DEVID1 0x00 /* device info */
+#define MN_BUSY 0x08 /* rx/tx in progress */
+#define MN_RXDATACOUNT 0x0c /* bytes in rx data buffer */
+#define MN_TXDATACOUNT 0x10 /* bytes for tx data buffer */
+#define MN_INTR 0x14 /* interrupt control */
+#define MN_INTR_TXDONE __BIT(0) /* tx done interrupt */
+#define MN_INTR_RXDONE __BIT(1) /* rx data available interrupt */
+#define MN_INTR_TEST __BIT(31) /* interrupt test */
+#define MN_INTRINFO 0x18 /* core-specific interrupt info */
+#define MN_RXDATA 0x1c /* rx data fifo */
+#define MN_TXDATA 0x20 /* tx data fifo */
+
+#define MN_NPORTS 0x24 /* size to map for registers */
+
+#define MN_MAXDATA 32768 /* largest transfer size */
+
+#define MIPSNET_DEVID0 0x4d495053 /* ascii "MIPS" */
+#define MIPSNET_DEVID1 0x4e455430 /* ascii "NET0" */
Index: src/sys/arch/evbmips/mipssim/machdep.c
diff -u /dev/null src/sys/arch/evbmips/mipssim/machdep.c:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/mipssim/machdep.c Wed Jan 27 05:24:16 2021
@@ -0,0 +1,331 @@
+/* $NetBSD: machdep.c,v 1.1 2021/01/27 05:24:16 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2001,2021 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe and Simon Burge.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.1 2021/01/27 05:24:16 simonb Exp $");
+
+#include "opt_ddb.h"
+#include "opt_kgdb.h"
+#include "opt_modular.h"
+
+#include <sys/param.h>
+#include <sys/boot_flag.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+#include <sys/kcore.h>
+#include <sys/kernel.h>
+#include <sys/ksyms.h>
+#include <sys/mount.h>
+#include <sys/mutex.h>
+#include <sys/reboot.h>
+#include <sys/termios.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <dev/cons.h>
+#include <dev/ic/comvar.h>
+#include <dev/ic/ns16450reg.h>
+
+#include <evbmips/mipssim/mipssimreg.h>
+#include <evbmips/mipssim/mipssimvar.h>
+
+#include "ksyms.h"
+
+#if NKSYMS || defined(DDB) || defined(MODULAR)
+#include <mips/db_machdep.h>
+#include <ddb/db_extern.h>
+#endif
+
+#include <mips/cache.h>
+#include <mips/locore.h>
+#include <mips/cpuregs.h>
+
+
+#define COMCNRATE 115200 /* not important, emulated device */
+#define COM_FREQ 1843200 /* not important, emulated device */
+
+/* XXX move phys map decl to a general mips location */
+/* Maps for VM objects. */
+struct vm_map *phys_map = NULL;
+
+struct mipssim_config mipssim_configuration;
+
+/* XXX move mem cluster decls to a general mips location */
+int mem_cluster_cnt;
+phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
+
+/* XXX move mach_init() prototype to general mips header file */
+void mach_init(u_long, u_long, u_long, u_long);
+static void mach_init_memory(void);
+
+/*
+ * Provide a very simple output-only console driver so that we can
+ * use printf() before the "real" console is initialised.
+ */
+static void uart_putc(dev_t, int);
+static struct consdev early_console = {
+ .cn_putc = uart_putc,
+ .cn_dev = makedev(0, 0),
+ .cn_pri = CN_DEAD
+};
+
+static void
+uart_putc(dev_t dev, int c)
+{
+ volatile uint8_t *data = (void *)MIPS_PHYS_TO_KSEG1(
+ MIPSSIM_ISA_IO_BASE + MIPSSIM_UART0_ADDR + com_data);
+
+ *data = (uint8_t)c;
+ /* emulated UART, don't need to wait for output to drain */
+}
+
+static void
+cal_timer(void)
+{
+ uint32_t cntfreq;
+
+ /* Pick a random clock frequency. XXX Any better way? */
+ cntfreq = curcpu()->ci_cpu_freq = 10 * 1000 * 1000;
+
+ if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
+ cntfreq /= 2;
+
+ curcpu()->ci_cctr_freq = cntfreq;
+ curcpu()->ci_cycles_per_hz = (cntfreq + hz / 2) / hz;
+
+ /* Compute number of cycles per 1us (1/MHz). 0.5MHz is for roundup. */
+ curcpu()->ci_divisor_delay = ((cntfreq + 500000) / 1000000);
+}
+
+/*
+ *
+ */
+void
+mach_init(u_long arg0, u_long arg1, u_long arg2, u_long arg3)
+{
+ struct mipssim_config *mcp = &mipssim_configuration;
+ void *kernend;
+ extern char edata[], end[]; /* XXX */
+
+ kernend = (void *)mips_round_page(end);
+
+ /* Zero BSS. QEMU appears to leave some memory uninitialised. */
+ memset(edata, 0, end - edata);
+
+ /* enough of a console for printf() to work */
+ cn_tab = &early_console;
+
+ cal_timer();
+
+ /* set CPU model info for sysctl_hw */
+ cpu_setmodel("MIPSSIM");
+
+ mips_vector_init(NULL, false);
+
+ uvm_md_init();
+
+ /*
+ * Initialize bus space tags and bring up the main console.
+ */
+ mipssim_bus_io_init(&mcp->mc_iot, mcp);
+ if (comcnattach(&mcp->mc_iot, MIPSSIM_UART0_ADDR, COMCNRATE,
+ COM_FREQ, COM_TYPE_NORMAL,
+ (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) != 0)
+ panic("unable to initialize serial console");
+
+ /*
+ * No way of passing arguments in mipssim.
+ */
+ boothowto = RB_AUTOBOOT;
+#ifdef KADB
+ boothowto |= RB_KDB;
+#endif
+
+ mach_init_memory();
+
+ /*
+ * Load the available pages into the VM system.
+ */
+ mips_page_physload(MIPS_KSEG0_START, (vaddr_t)kernend,
+ mem_clusters, mem_cluster_cnt, NULL, 0);
+
+ /*
+ * Initialize message buffer (at end of core).
+ */
+ mips_init_msgbuf();
+
+ /*
+ * Initialize the virtual memory system.
+ */
+ pmap_bootstrap();
+
+ /*
+ * Allocate uarea page for lwp0 and set it.
+ */
+ mips_init_lwp0_uarea();
+
+ /*
+ * Initialize debuggers, and break into them, if appropriate.
+ */
+#ifdef DDB
+ if (boothowto & RB_KDB)
+ Debugger();
+#endif
+}
+
+/*
+ * qemu for mipssim doesn't have a way of passing in the memory size, so
+ * we probe. lwp0 hasn't been set up this early, so use a dummy pcb to
+ * allow badaddr() to function. Limit total RAM to just before the IO
+ * memory at MIPSSIM_ISA_IO_BASE.
+ */
+static void
+mach_init_memory(void)
+{
+ struct lwp *l = curlwp;
+ struct pcb dummypcb;
+ psize_t memsize;
+ size_t addr;
+ uint32_t *memptr;
+ extern char end[]; /* XXX */
+
+ l->l_addr = &dummypcb;
+ memsize = roundup2(MIPS_KSEG0_TO_PHYS((uintptr_t)(end)), 1024 * 1024);
+
+ for (addr = memsize; addr < MIPSSIM_ISA_IO_BASE; addr += 1024 * 1024) {
+#ifdef MEM_DEBUG
+ printf("test %zd MB\n", addr / 1024 * 1024);
+#endif
+ memptr = (void *)MIPS_PHYS_TO_KSEG1(addr - sizeof(*memptr));
+
+ if (badaddr(memptr, sizeof(uint32_t)) < 0)
+ break;
+
+ memsize = addr;
+ }
+ l->l_addr = NULL;
+
+ printf("Memory size: 0x%" PRIxPSIZE " (%" PRIdPSIZE " MB)\n",
+ memsize, memsize / 1024 / 1024);
+ physmem = btoc(memsize);
+
+ mem_clusters[0].start = PAGE_SIZE;
+ mem_clusters[0].size = memsize - PAGE_SIZE;
+ mem_cluster_cnt = 1;
+}
+
+void
+consinit(void)
+{
+ /*
+ * Everything related to console initialization is done
+ * in mach_init().
+ */
+}
+
+void
+cpu_startup(void)
+{
+
+ /*
+ * Do the common startup items.
+ */
+ cpu_startup_common();
+}
+
+/* XXX try to make this evbmips generic */
+void
+cpu_reboot(int howto, char *bootstr)
+{
+ static int waittime = -1;
+
+ /* Take a snapshot before clobbering any registers. */
+ savectx(curpcb);
+
+ /* If "always halt" was specified as a boot flag, obey. */
+ if (boothowto & RB_HALT)
+ howto |= RB_HALT;
+
+ boothowto = howto;
+
+ /* If system is cold, just halt. */
+ if (cold) {
+ boothowto |= RB_HALT;
+ goto haltsys;
+ }
+
+ if ((boothowto & RB_NOSYNC) == 0 && waittime < 0) {
+ waittime = 0;
+
+ /*
+ * Synchronize the disks....
+ */
+ vfs_shutdown();
+
+ /*
+ * If we've been adjusting the clock, the todr
+ * will be out of synch; adjust it now.
+ */
+ resettodr();
+ }
+
+ /* Disable interrupts. */
+ splhigh();
+
+ if (boothowto & RB_DUMP)
+ dumpsys();
+
+haltsys:
+ /* Run any shutdown hooks. */
+ doshutdownhooks();
+
+ /*
+ * Firmware may autoboot (depending on settings), and we cannot pass
+ * flags to it (at least I haven't figured out how to yet), so
+ * we "pseudo-halt" now.
+ */
+ if (boothowto & RB_HALT) {
+ printf("\n");
+ printf("The operating system has halted.\n");
+ printf("Please press any key to reboot.\n\n");
+ cnpollc(1); /* For proper keyboard command handling */
+ cngetc();
+ cnpollc(0);
+ }
+
+ printf("resetting...\n\n");
+ __asm volatile("jr %0" :: "r"(MIPS_RESET_EXC_VEC));
+ printf("Oops, back from reset\n\nSpinning...");
+ for (;;)
+ /* spin forever */ ; /* XXX */
+ /*NOTREACHED*/
+}
Index: src/sys/arch/evbmips/mipssim/mainbus.c
diff -u /dev/null src/sys/arch/evbmips/mipssim/mainbus.c:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/mipssim/mainbus.c Wed Jan 27 05:24:16 2021
@@ -0,0 +1,101 @@
+/* $NetBSD: mainbus.c,v 1.1 2021/01/27 05:24:16 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2021 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Simon Burge.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.1 2021/01/27 05:24:16 simonb Exp $");
+
+#include <sys/param.h>
+#include <sys/device.h>
+
+#include <evbmips/mipssim/autoconf.h>
+#include <evbmips/mipssim/mipssimreg.h>
+#include <evbmips/mipssim/mipssimvar.h>
+
+static int mainbus_match(device_t, cfdata_t, void *);
+static void mainbus_attach(device_t, device_t, void *);
+static int mainbus_print(void *, const char *);
+
+CFATTACH_DECL_NEW(mainbus, 0,
+ mainbus_match, mainbus_attach, NULL, NULL);
+
+/* There can be only one. */
+static int mainbus_found;
+
+struct mainbusdev {
+ const char *md_name;
+ paddr_t md_addr;
+ int md_irq;
+};
+
+static struct mainbusdev mainbusdevs[] = {
+ { "cpu", },
+ { "com", MIPSSIM_UART0_ADDR, 2 },
+#ifdef notyet
+ { "mipsnet", MIPSSIM_MIPSNET0_ADDR, 0 },
+#endif
+ { NULL, }
+};
+
+static int
+mainbus_match(device_t parent, cfdata_t match, void *aux)
+{
+
+ if (mainbus_found)
+ return (0);
+
+ return (1);
+}
+
+static void
+mainbus_attach(device_t parent, device_t self, void *aux)
+{
+ struct mainbus_attach_args maa;
+ struct mipssim_config *mcp = &mipssim_configuration;
+ const struct mainbusdev *md;
+
+ mainbus_found = 1;
+ printf("\n");
+
+ for (md = mainbusdevs; md->md_name != NULL; md++) {
+ maa.ma_name = md->md_name;
+ maa.ma_addr = md->md_addr;
+ maa.ma_irq = md->md_irq;
+ maa.ma_iot = &mcp->mc_iot;
+ config_found_ia(self, "mainbus", &maa, mainbus_print);
+ }
+}
+
+static int
+mainbus_print(void *aux, const char *pnp)
+{
+
+ return (QUIET);
+}
Index: src/sys/arch/evbmips/mipssim/mipssim_bus_io.c
diff -u /dev/null src/sys/arch/evbmips/mipssim/mipssim_bus_io.c:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/mipssim/mipssim_bus_io.c Wed Jan 27 05:24:16 2021
@@ -0,0 +1,56 @@
+/* $NetBSD: mipssim_bus_io.c,v 1.1 2021/01/27 05:24:16 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Platform-specific PCI bus I/O support for the MIPS Malta.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mipssim_bus_io.c,v 1.1 2021/01/27 05:24:16 simonb Exp $");
+
+#include <sys/param.h>
+
+#include <evbmips/mipssim/mipssimreg.h>
+#include <evbmips/mipssim/mipssimvar.h>
+
+#define CHIP mipssim
+#define CHIP_IO /* defined */
+
+#define CHIP_EX_MALLOC_SAFE(v) (((struct mipssim_config *)(v))->mc_mallocsafe)
+#define CHIP_EXTENT(v) (((struct mipssim_config *)(v))->mc_io_ex)
+
+/* IO region 1 */
+#define CHIP_W1_BUS_START(v) 0
+#define CHIP_W1_BUS_END(v) MIPSSIM_ISA_IO_SIZE
+#define CHIP_W1_SYS_START(v) MIPSSIM_ISA_IO_BASE
+#define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + CHIP_W1_SYS_START(v))
+
+#include <mips/mips/bus_space_alignstride_chipdep.c>
Index: src/sys/arch/evbmips/mipssim/mipssim_intr.c
diff -u /dev/null src/sys/arch/evbmips/mipssim/mipssim_intr.c:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/mipssim/mipssim_intr.c Wed Jan 27 05:24:16 2021
@@ -0,0 +1,164 @@
+/* $NetBSD: mipssim_intr.c,v 1.1 2021/01/27 05:24:16 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2014 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mipssim_intr.c,v 1.1 2021/01/27 05:24:16 simonb Exp $");
+
+#define __INTR_PRIVATE
+
+#include <sys/param.h>
+#include <sys/cpu.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+
+#include <mips/locore.h>
+#include <machine/intr.h>
+
+/*
+ * This is a mask of bits to clear in the SR when we go to a
+ * given hardware interrupt priority level.
+ */
+static const struct ipl_sr_map mipssim_ipl_sr_map = {
+ .sr_bits = {
+ [IPL_NONE] = 0,
+ [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
+ [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
+ [IPL_VM] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_0 | MIPS_INT_MASK_2,
+ [IPL_SCHED] = MIPS_SOFT_INT_MASK
+ | MIPS_INT_MASK_0 | MIPS_INT_MASK_2
+ | MIPS_INT_MASK_5,
+ [IPL_DDB] = MIPS_INT_MASK,
+ [IPL_HIGH] = MIPS_INT_MASK,
+ },
+};
+
+/* XXX - add evcnt bits to <machine/intr.h> struct evbmips_intrhand */
+struct intrhand {
+ LIST_ENTRY(intrhand) ih_q;
+ struct evcnt ih_count;
+ int (*ih_func)(void *);
+ void *ih_arg;
+ int ih_irq;
+};
+
+
+/*
+ * Use CPU interrupts INT0 .. INT4. Clock interrupts (INT5)
+ * are handled in cpu_intr() before evbmips_iointr() is called.
+ */
+#define NINTR 5 /* MIPS INT0 - INT4 */
+
+struct intrhand intrs[NINTR];
+const char * const intrnames[NINTR] = {
+ "int 0 (mipsnet)",
+ "int 1 (unused)",
+ "int 2 (uart)",
+ "int 3 (unused)",
+ "int 4 (unused)",
+};
+
+void mipssim_irq(int);
+
+void
+evbmips_intr_init(void)
+{
+ int i;
+
+ ipl_sr_map = mipssim_ipl_sr_map;
+
+ /* zero all handlers */
+ for (i = 0; i < NINTR; i++) {
+ intrs[i].ih_func = NULL;
+ intrs[i].ih_arg = NULL;
+ intrs[i].ih_irq = i;
+ evcnt_attach_dynamic(&intrs[i].ih_count, EVCNT_TYPE_INTR,
+ NULL, "cpu", intrnames[i]);
+ }
+}
+
+void
+evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
+{
+
+ for (int level = NINTR - 1; level >= 0; level--) {
+ struct intrhand *ih;
+
+ if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
+ continue;
+
+ ih = &intrs[level];
+
+ ih->ih_count.ev_count++;
+ if (ih->ih_func) {
+ (*ih->ih_func)(ih->ih_arg);
+ }
+ }
+}
+
+void *
+evbmips_intr_establish(int irq, int (*func)(void *), void *arg)
+{
+ struct intrhand *ih;
+ int s;
+
+ if ((irq < 0) || (irq >= NINTR)) {
+ aprint_error("%s: invalid irq %d\n", __func__, irq);
+ return NULL;
+ }
+
+ ih = &intrs[irq];
+
+ s = splhigh();
+ ih->ih_func = func;
+ ih->ih_arg = arg;
+
+ /* now enable the IRQ (nothing to do here?) */
+
+ splx(s);
+
+ return ih;
+}
+
+void
+evbmips_intr_disestablish(void *cookie)
+{
+ panic("untested %s", __func__); /* XXX! */
+
+ struct intrhand *ih = cookie;
+ int s;
+
+ s = splhigh();
+
+ /* now disable the IRQ (nothing to do here?) */
+
+ ih->ih_func = NULL;
+ ih->ih_arg = NULL;
+
+ splx(s);
+}
Index: src/sys/arch/evbmips/mipssim/mipssimreg.h
diff -u /dev/null src/sys/arch/evbmips/mipssim/mipssimreg.h:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/mipssim/mipssimreg.h Wed Jan 27 05:24:16 2021
@@ -0,0 +1,49 @@
+/* $NetBSD: mipssimreg.h,v 1.1 2021/01/27 05:24:16 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2021 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Simon Burge.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/*
+ * Memory Map
+ *
+ * 0000.0000 128MB RAM (max ~500MB)
+ * 1fd0.0000 64kB ISA IO space
+ *
+ * CPU interrupts
+ *
+ * 0 mipsnet
+ * 2 16450 UART
+ */
+
+#define MIPSSIM_UART0_ADDR 0x3f8
+#define MIPSSIM_MIPSNET0_ADDR 0x4200
+
+#define MIPSSIM_ISA_IO_BASE 0x1fd00000 /* ISA IO memory: */
+#define MIPSSIM_ISA_IO_SIZE 0x00010000 /* 64 kByte */
Index: src/sys/arch/evbmips/mipssim/mipssimvar.h
diff -u /dev/null src/sys/arch/evbmips/mipssim/mipssimvar.h:1.1
--- /dev/null Wed Jan 27 05:24:16 2021
+++ src/sys/arch/evbmips/mipssim/mipssimvar.h Wed Jan 27 05:24:16 2021
@@ -0,0 +1,47 @@
+/* $NetBSD: mipssimvar.h,v 1.1 2021/01/27 05:24:16 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2001,2021 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/bus.h>
+#include <dev/isa/isavar.h>
+
+struct mipssim_config {
+ struct mips_bus_space mc_iot;
+
+ struct mips_isa_chipset mc_ic;
+
+ struct extent *mc_io_ex;
+
+ int mc_mallocsafe;
+};
+
+extern struct mipssim_config mipssim_configuration;
+
+void mipssim_bus_io_init(bus_space_tag_t, void *);
