Module Name: src
Committed By: mrg
Date: Wed Feb 24 04:48:29 UTC 2010
Modified Files:
src/sys/arch/sparc64/include: pmap.h
src/sys/arch/sparc64/sparc64: cache.h
Log Message:
move the tlb flush routines into cache.h to avoid machine/pmap.h polution.
To generate a diff of this commit:
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/sparc64/include/pmap.h
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/sparc64/sparc64/cache.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/include/pmap.h
diff -u src/sys/arch/sparc64/include/pmap.h:1.49 src/sys/arch/sparc64/include/pmap.h:1.50
--- src/sys/arch/sparc64/include/pmap.h:1.49 Wed Feb 24 01:58:52 2010
+++ src/sys/arch/sparc64/include/pmap.h Wed Feb 24 04:48:28 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.49 2010/02/24 01:58:52 mrg Exp $ */
+/* $NetBSD: pmap.h,v 1.50 2010/02/24 04:48:28 mrg Exp $ */
/*-
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
@@ -204,38 +204,6 @@
void switchexit(struct lwp *, int);
void pmap_kprotect(vaddr_t, vm_prot_t);
-/* SPARC64 specific */
-/* Assembly routines to flush TLB mappings */
-void sp_tlb_flush_pte_us(vaddr_t, int);
-void sp_tlb_flush_pte_usiii(vaddr_t, int);
-void sp_tlb_flush_all_us(void);
-void sp_tlb_flush_all_usiii(void);
-
-static __inline__ void
-sp_tlb_flush_pte(vaddr_t va, int ctx)
-{
- if (CPU_IS_USIII_UP())
- sp_tlb_flush_pte_usiii(va, ctx);
- else
- sp_tlb_flush_pte_us(va, ctx);
-}
-
-static __inline__ void
-sp_tlb_flush_all(void)
-{
- if (CPU_IS_USIII_UP())
- sp_tlb_flush_all_usiii();
- else
- sp_tlb_flush_all_us();
-}
-
-#ifdef MULTIPROCESSOR
-void smp_tlb_flush_pte(vaddr_t, pmap_t);
-#define tlb_flush_pte(va,pm) smp_tlb_flush_pte(va, pm)
-#else
-#define tlb_flush_pte(va,pm) sp_tlb_flush_pte(va, (pm)->pm_ctx)
-#endif
-
/* Installed physical memory, as discovered during bootstrap. */
extern int phys_installed_size;
extern struct mem_region *phys_installed;
Index: src/sys/arch/sparc64/sparc64/cache.h
diff -u src/sys/arch/sparc64/sparc64/cache.h:1.12 src/sys/arch/sparc64/sparc64/cache.h:1.13
--- src/sys/arch/sparc64/sparc64/cache.h:1.12 Mon Feb 22 00:16:31 2010
+++ src/sys/arch/sparc64/sparc64/cache.h Wed Feb 24 04:48:29 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.h,v 1.12 2010/02/22 00:16:31 mrg Exp $ */
+/* $NetBSD: cache.h,v 1.13 2010/02/24 04:48:29 mrg Exp $ */
/*
* Copyright (c) 1996
@@ -110,6 +110,38 @@
blast_icache_us();
}
+/* SPARC64 specific */
+/* Assembly routines to flush TLB mappings */
+void sp_tlb_flush_pte_us(vaddr_t, int);
+void sp_tlb_flush_pte_usiii(vaddr_t, int);
+void sp_tlb_flush_all_us(void);
+void sp_tlb_flush_all_usiii(void);
+
+static __inline__ void
+sp_tlb_flush_pte(vaddr_t va, int ctx)
+{
+ if (CPU_IS_USIII_UP())
+ sp_tlb_flush_pte_usiii(va, ctx);
+ else
+ sp_tlb_flush_pte_us(va, ctx);
+}
+
+static __inline__ void
+sp_tlb_flush_all(void)
+{
+ if (CPU_IS_USIII_UP())
+ sp_tlb_flush_all_usiii();
+ else
+ sp_tlb_flush_all_us();
+}
+
+#ifdef MULTIPROCESSOR
+void smp_tlb_flush_pte(vaddr_t, pmap_t);
+#define tlb_flush_pte(va,pm) smp_tlb_flush_pte(va, pm)
+#else
+#define tlb_flush_pte(va,pm) sp_tlb_flush_pte(va, (pm)->pm_ctx)
+#endif
+
/* Various cache size/line sizes */
extern int ecache_min_line_size;
extern int dcache_line_size;
