Module Name: src
Committed By: jakllsch
Date: Mon Mar 1 17:48:52 UTC 2021
Modified Files:
src/sys/dev/pci: files.pci if_rge.c if_rgereg.h
Log Message:
Update rge(4) from older OpenBSD, finish porting.
Should consider merging this all into re(4) and rgephy(4) someday.
Some cleanup tasks remain here.
To generate a diff of this commit:
cvs rdiff -u -r1.434 -r1.435 src/sys/dev/pci/files.pci
cvs rdiff -u -r1.16 -r1.17 src/sys/dev/pci/if_rge.c
cvs rdiff -u -r1.4 -r1.5 src/sys/dev/pci/if_rgereg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/pci/files.pci
diff -u src/sys/dev/pci/files.pci:1.434 src/sys/dev/pci/files.pci:1.435
--- src/sys/dev/pci/files.pci:1.434 Wed Feb 17 08:15:43 2021
+++ src/sys/dev/pci/files.pci Mon Mar 1 17:48:52 2021
@@ -1,4 +1,4 @@
-# $NetBSD: files.pci,v 1.434 2021/02/17 08:15:43 knakahara Exp $
+# $NetBSD: files.pci,v 1.435 2021/03/01 17:48:52 jakllsch Exp $
#
# Config file and device description for machine-independent PCI code.
# Included by ports that need it. Requires that the SCSI files be
@@ -1183,3 +1183,8 @@ device vmx: ether, ifnet, arp
attach vmx at pci
file dev/pci/if_vmx.c vmx
+# Realtek RTL8125 2.5GBASE-T Ethernet
+device rge: ether, ifnet, arp, mii
+attach rge at pci
+file dev/pci/if_rge.c rge
+
Index: src/sys/dev/pci/if_rge.c
diff -u src/sys/dev/pci/if_rge.c:1.16 src/sys/dev/pci/if_rge.c:1.17
--- src/sys/dev/pci/if_rge.c:1.16 Wed Jan 27 14:25:22 2021
+++ src/sys/dev/pci/if_rge.c Mon Mar 1 17:48:52 2021
@@ -1,8 +1,8 @@
-/* $NetBSD: if_rge.c,v 1.16 2021/01/27 14:25:22 jakllsch Exp $ */
-/* $OpenBSD: if_rge.c,v 1.4 2020/07/10 13:26:38 patrick Exp $ */
+/* $NetBSD: if_rge.c,v 1.17 2021/03/01 17:48:52 jakllsch Exp $ */
+/* $OpenBSD: if_rge.c,v 1.9 2020/12/12 11:48:53 jan Exp $ */
/*
- * Copyright (c) 2019 Kevin Lo <[email protected]>
+ * Copyright (c) 2019, 2020 Kevin Lo <[email protected]>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -18,9 +18,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_rge.c,v 1.16 2021/01/27 14:25:22 jakllsch Exp $");
-
-/* #include "vlan.h" Sevan */
+__KERNEL_RCSID(0, "$NetBSD: if_rge.c,v 1.17 2021/03/01 17:48:52 jakllsch Exp $");
#include <sys/types.h>
@@ -46,9 +44,7 @@ __KERNEL_RCSID(0, "$NetBSD: if_rge.c,v 1
#include <netinet/in.h>
#include <net/if_ether.h>
-#if NBPFILTER > 0
#include <net/bpf.h>
-#endif
#include <sys/bus.h>
#include <machine/intr.h>
@@ -64,16 +60,10 @@ __KERNEL_RCSID(0, "$NetBSD: if_rge.c,v 1
#ifdef __NetBSD__
#define letoh32 htole32
#define nitems(x) __arraycount(x)
-#define MBUF_LIST_INITIALIZER() { NULL, NULL, 0 }
-struct mbuf_list {
- struct mbuf *ml_head;
- struct mbuf *ml_tail;
- u_int ml_len;
-};
static struct mbuf *
-MCLGETI(struct rge_softc *sc __unused, int how,
- struct ifnet *ifp __unused, u_int size)
+MCLGETL(struct rge_softc *sc __unused, int how,
+ u_int size)
{
struct mbuf *m;
@@ -97,6 +87,13 @@ MCLGETI(struct rge_softc *sc __unused, i
#endif
#endif
+#ifdef RGE_DEBUG
+#define DPRINTF(x) do { if (rge_debug > 0) printf x; } while (0)
+int rge_debug = 0;
+#else
+#define DPRINTF(x)
+#endif
+
static int rge_match(device_t, cfdata_t, void *);
static void rge_attach(device_t, device_t, void *);
int rge_intr(void *);
@@ -105,7 +102,7 @@ int rge_ioctl(struct ifnet *, u_long, v
void rge_start(struct ifnet *);
void rge_watchdog(struct ifnet *);
int rge_init(struct ifnet *);
-void rge_stop(struct ifnet *);
+void rge_stop(struct ifnet *, int);
int rge_ifmedia_upd(struct ifnet *);
void rge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
int rge_allocmem(struct rge_softc *);
@@ -119,6 +116,11 @@ void rge_reset(struct rge_softc *);
void rge_iff(struct rge_softc *);
void rge_set_phy_power(struct rge_softc *, int);
void rge_phy_config(struct rge_softc *);
+void rge_phy_config_mac_cfg2(struct rge_softc *);
+void rge_phy_config_mac_cfg3(struct rge_softc *);
+void rge_phy_config_mac_cfg4(struct rge_softc *);
+void rge_phy_config_mac_cfg5(struct rge_softc *);
+void rge_phy_config_mcu(struct rge_softc *, uint16_t);
void rge_set_macaddr(struct rge_softc *, const uint8_t *);
void rge_get_macaddr(struct rge_softc *, uint8_t *);
void rge_hw_init(struct rge_softc *);
@@ -126,6 +128,7 @@ void rge_disable_phy_ocp_pwrsave(struct
void rge_patch_phy_mcu(struct rge_softc *, int);
void rge_add_media_types(struct rge_softc *);
void rge_config_imtype(struct rge_softc *, int);
+void rge_disable_hw_im(struct rge_softc *);
void rge_disable_sim_im(struct rge_softc *);
void rge_setup_sim_im(struct rge_softc *);
void rge_setup_intr(struct rge_softc *, int);
@@ -135,7 +138,9 @@ uint32_t rge_read_csi(struct rge_softc *
void rge_write_mac_ocp(struct rge_softc *, uint16_t, uint16_t);
uint16_t rge_read_mac_ocp(struct rge_softc *, uint16_t);
void rge_write_ephy(struct rge_softc *, uint16_t, uint16_t);
+uint16_t rge_read_ephy(struct rge_softc *, uint16_t);
void rge_write_phy(struct rge_softc *, uint16_t, uint16_t, uint16_t);
+uint16_t rge_read_phy(struct rge_softc *, uint16_t, uint16_t);
void rge_write_phy_ocp(struct rge_softc *, uint16_t, uint16_t);
uint16_t rge_read_phy_ocp(struct rge_softc *, uint16_t);
int rge_get_link_status(struct rge_softc *);
@@ -146,23 +151,19 @@ void rge_link_state(struct rge_softc *)
static const struct {
uint16_t reg;
uint16_t val;
-} rtl8125_def_bps[] = {
- RTL8125_DEF_BPS
-}, rtl8125_mac_cfg2_ephy[] = {
- RTL8125_MAC_CFG2_EPHY
-}, rtl8125_mac_cfg2_mcu[] = {
+} rtl8125_mac_cfg2_mcu[] = {
RTL8125_MAC_CFG2_MCU
-}, rtl8125_mac_cfg3_ephy[] = {
- RTL8125_MAC_CFG3_EPHY
}, rtl8125_mac_cfg3_mcu[] = {
RTL8125_MAC_CFG3_MCU
+}, rtl8125_mac_cfg4_mcu[] = {
+ RTL8125_MAC_CFG4_MCU
+}, rtl8125_mac_cfg5_mcu[] = {
+ RTL8125_MAC_CFG5_MCU
};
CFATTACH_DECL_NEW(rge, sizeof(struct rge_softc), rge_match, rge_attach,
NULL, NULL); /* Sevan - detach function? */
-extern struct cfdriver rge_cd;
-
static const struct {
pci_vendor_id_t vendor;
pci_product_id_t product;
@@ -180,7 +181,7 @@ rge_match(device_t parent, cfdata_t matc
for (n =0; n < __arraycount(rge_devices); n++) {
if (PCI_VENDOR(pa->pa_id) == rge_devices[n].vendor &&
PCI_PRODUCT(pa->pa_id) == rge_devices[n].product)
- return 1;
+ return 3;
}
return 0;
@@ -192,7 +193,7 @@ rge_attach(device_t parent, device_t sel
struct rge_softc *sc = device_private(self);
struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
- pci_intr_handle_t ih;
+ pci_intr_handle_t *ihp;
char intrbuf[PCI_INTRSTR_LEN];
const char *intrstr = NULL;
struct ifnet *ifp;
@@ -200,11 +201,14 @@ rge_attach(device_t parent, device_t sel
uint32_t hwrev;
uint8_t eaddr[ETHER_ADDR_LEN];
int offset;
+ pcireg_t command;
pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
sc->sc_dev = self;
+ pci_aprint_devinfo(pa, "Ethernet controller");
+
/*
* Map control/status registers.
*/
@@ -223,17 +227,29 @@ rge_attach(device_t parent, device_t sel
}
}
+ int counts[PCI_INTR_TYPE_SIZE] = {
+ [PCI_INTR_TYPE_INTX] = 1,
+ [PCI_INTR_TYPE_MSI] = 1,
+ [PCI_INTR_TYPE_MSIX] = 1,
+ };
+ int max_type = PCI_INTR_TYPE_MSIX;
/*
* Allocate interrupt.
*/
- if (pci_intr_map(pa, &ih) == 0)
- sc->rge_flags |= RGE_FLAG_MSI;
- else if (pci_intr_map(pa, &ih) != 0) {
+ if (pci_intr_alloc(pa, &ihp, counts, max_type) != 0) {
aprint_error(": couldn't map interrupt\n");
return;
}
- intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
- sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, rge_intr,
+ switch (pci_intr_type(pc, ihp[0])) {
+ case PCI_INTR_TYPE_MSIX:
+ case PCI_INTR_TYPE_MSI:
+ sc->rge_flags |= RGE_FLAG_MSI;
+ break;
+ default:
+ break;
+ }
+ intrstr = pci_intr_string(pc, ihp[0], intrbuf, sizeof(intrbuf));
+ sc->sc_ih = pci_intr_establish_xname(pc, ihp[0], IPL_NET, rge_intr,
sc, device_xname(sc->sc_dev));
if (sc->sc_ih == NULL) {
aprint_error_dev(sc->sc_dev, ": couldn't establish interrupt");
@@ -261,6 +277,12 @@ rge_attach(device_t parent, device_t sel
case 0x60900000:
sc->rge_type = MAC_CFG3;
break;
+ case 0x64000000:
+ sc->rge_type = MAC_CFG4;
+ break;
+ case 0x64100000:
+ sc->rge_type = MAC_CFG5;
+ break;
default:
aprint_error(": unknown version 0x%08x\n", hwrev);
return;
@@ -273,10 +295,11 @@ rge_attach(device_t parent, device_t sel
*/
if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
&offset, NULL)) {
- /* Disable PCIe ASPM. */
+ /* Disable PCIe ASPM and ECPM. */
reg = pci_conf_read(pa->pa_pc, pa->pa_tag,
offset + PCIE_LCSR);
- reg &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1 );
+ reg &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1 |
+ PCIE_LCSR_ENCLKPM);
pci_conf_write(pa->pa_pc, pa->pa_tag, offset + PCIE_LCSR,
reg);
}
@@ -304,24 +327,30 @@ rge_attach(device_t parent, device_t sel
ifp->if_xflags = IFEF_MPSAFE;
#endif
ifp->if_ioctl = rge_ioctl;
+ ifp->if_stop = rge_stop;
ifp->if_start = rge_start;
+ ifp->if_init = rge_init;
ifp->if_watchdog = rge_watchdog;
- ifq_set_maxlen(&ifp->if_snd, RGE_TX_LIST_CNT);
- ifp->if_mtu = RGE_JUMBO_MTU;
+ IFQ_SET_MAXLEN(&ifp->if_snd, RGE_TX_LIST_CNT - 1);
- ifp->if_capabilities = ETHERCAP_VLAN_MTU | IFCAP_CSUM_IPv4_Rx |
+#if notyet
+ ifp->if_capabilities = IFCAP_CSUM_IPv4_Rx |
IFCAP_CSUM_IPv4_Tx |IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_TCPv4_Tx|
IFCAP_CSUM_UDPv4_Rx | IFCAP_CSUM_UDPv4_Tx;
-
-#if NVLAN > 0
- ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
#endif
+ sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
+ sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING;
+
callout_init(&sc->sc_timeout, CALLOUT_FLAGS);
callout_setfunc(&sc->sc_timeout, rge_tick, sc);
- rge_txstart(&sc->sc_task, sc);
+
+ command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
+ command |= PCI_COMMAND_MASTER_ENABLE;
+ pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
/* Initialize ifmedia structures. */
+ sc->sc_ec.ec_ifmedia = &sc->sc_media;
ifmedia_init(&sc->sc_media, IFM_IMASK, rge_ifmedia_upd,
rge_ifmedia_sts);
rge_add_media_types(sc);
@@ -347,11 +376,12 @@ rge_intr(void *arg)
/* Disable interrupts. */
RGE_WRITE_4(sc, RGE_IMR, 0);
- status = RGE_READ_4(sc, RGE_ISR);
if (!(sc->rge_flags & RGE_FLAG_MSI)) {
- if ((status & RGE_INTRS) == 0 || status == 0xffffffff)
+ if ((RGE_READ_4(sc, RGE_ISR) & sc->rge_intrs) == 0)
return (0);
}
+
+ status = RGE_READ_4(sc, RGE_ISR);
if (status)
RGE_WRITE_4(sc, RGE_ISR, status);
@@ -359,7 +389,7 @@ rge_intr(void *arg)
claimed = 1;
rx = tx = 0;
- if (status & RGE_INTRS) {
+ if (status & sc->rge_intrs) {
if (status &
(sc->rge_rx_ack | RGE_ISR_RX_ERR | RGE_ISR_RX_FIFO_OFLOW)) {
rx |= rge_rxeof(sc);
@@ -419,6 +449,7 @@ rge_encap(struct rge_softc *sc, struct m
uint32_t cmdsts, cflags = 0;
int cur, error, i, last, nsegs;
+#if notyet
/*
* Set RGE_TDEXTSTS_IPCSUM if any checksum offloading is requested.
* Otherwise, RGE_TDEXTSTS_TCPCSUM / RGE_TDEXTSTS_UDPCSUM does not
@@ -432,6 +463,7 @@ rge_encap(struct rge_softc *sc, struct m
if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT)
cflags |= RGE_TDEXTSTS_UDPCSUM;
}
+#endif
txq = &sc->rge_ldata.rge_txq[idx];
txmap = txq->txq_dmamap;
@@ -457,12 +489,10 @@ rge_encap(struct rge_softc *sc, struct m
nsegs = txmap->dm_nsegs;
/* Set up hardware VLAN tagging. */
-#if NVLAN > 0
- if (m->m_flags & M_VLANTAG)
- cflags |= swap16(m->m_pkthdr.ether_vtag | RGE_TDEXTSTS_VTAG);
-#endif
+ if (vlan_has_tag(m))
+ cflags |= bswap16(vlan_get_tag(m)) | RGE_TDEXTSTS_VTAG;
- cur = idx;
+ last = cur = idx;
cmdsts = RGE_TDCMDSTS_SOF;
for (i = 0; i < txmap->dm_nsegs; i++) {
@@ -507,18 +537,18 @@ int
rge_ioctl(struct ifnet *ifp, u_long cmd, void *data)
{
struct rge_softc *sc = ifp->if_softc;
- struct ifreq *ifr = (struct ifreq *)data;
+ //struct ifreq *ifr = (struct ifreq *)data;
int s, error = 0;
s = splnet();
switch (cmd) {
- case SIOCSIFADDR:
- ifp->if_flags |= IFF_UP;
- if (!(ifp->if_flags & IFF_RUNNING))
- rge_init(ifp);
- break;
case SIOCSIFFLAGS:
+ if ((error = ifioctl_common(ifp, cmd, data)) != 0)
+ break;
+ /* XXX set an ifflags callback and let ether_ioctl
+ * handle all of this.
+ */
if (ifp->if_flags & IFF_UP) {
if (ifp->if_flags & IFF_RUNNING)
error = ENETRESET;
@@ -526,20 +556,9 @@ rge_ioctl(struct ifnet *ifp, u_long cmd,
rge_init(ifp);
} else {
if (ifp->if_flags & IFF_RUNNING)
- rge_stop(ifp);
+ rge_stop(ifp, 1);
}
break;
- case SIOCGIFMEDIA:
- case SIOCSIFMEDIA:
- error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
- break;
- case SIOCSIFMTU:
- if (ifr->ifr_mtu > ifp->if_mtu) {
- error = EINVAL;
- break;
- }
- ifp->if_mtu = ifr->ifr_mtu;
- break;
default:
error = ether_ioctl(ifp, cmd, data);
}
@@ -566,7 +585,7 @@ rge_start(struct ifnet *ifp)
((_s) >= LINK_STATE_UP || (_s) == LINK_STATE_UNKNOWN)
if (!LINK_STATE_IS_UP(ifp->if_link_state)) {
- ifq_purge(ifq);
+ IFQ_PURGE(&ifp->if_snd);
return;
}
@@ -596,10 +615,7 @@ rge_start(struct ifnet *ifp)
KASSERT(used <= free);
free -= used;
-#if NBPFILTER > 0
- if (ifp->if_bpf)
- bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT);
-#endif
+ bpf_mtap(ifp, m, BPF_D_OUT);
idx += used;
if (idx >= RGE_TX_LIST_CNT)
@@ -615,7 +631,11 @@ rge_start(struct ifnet *ifp)
ifp->if_timer = 5;
sc->rge_ldata.rge_txq_prodidx = idx;
+#if 0
ifq_serialize(ifq, &sc->sc_task);
+#else
+ rge_txstart(&sc->sc_task, sc);
+#endif
}
void
@@ -634,33 +654,21 @@ rge_init(struct ifnet *ifp)
{
struct rge_softc *sc = ifp->if_softc;
uint32_t val;
- uint16_t max_frame_size;
int i;
- rge_stop(ifp);
+ rge_stop(ifp, 0);
/* Set MAC address. */
- rge_set_macaddr(sc, sc->sc_enaddr);
+ rge_set_macaddr(sc, CLLADDR(ifp->if_sadl));
- /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */
- if (ifp->if_mtu < ETHERMTU)
- max_frame_size = ETHERMTU;
- else
- max_frame_size = ifp->if_mtu;
-
- max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
- ETHER_CRC_LEN + 1;
-
- if (max_frame_size > RGE_JUMBO_FRAMELEN)
- max_frame_size -= 1;
-
- RGE_WRITE_2(sc, RGE_RXMAXSIZE, max_frame_size);
+ /* Set Maximum frame size. */
+ RGE_WRITE_2(sc, RGE_RXMAXSIZE, RGE_JUMBO_FRAMELEN);
/* Initialize RX descriptors list. */
if (rge_rx_list_init(sc) == ENOBUFS) {
device_printf(sc->sc_dev,
"init failed: no memory for RX buffers\n");
- rge_stop(ifp);
+ rge_stop(ifp, 1);
return (ENOBUFS);
}
@@ -686,7 +694,7 @@ rge_init(struct ifnet *ifp)
/* Clear interrupt moderation timer. */
for (i = 0; i < 64; i++)
- RGE_WRITE_4(sc, RGE_IM(i), 0);
+ RGE_WRITE_4(sc, RGE_INTMITI(i), 0);
/* Set the initial RX and TX configurations. */
RGE_WRITE_4(sc, RGE_RXCFG, RGE_RXCFG_CONFIG);
@@ -715,16 +723,22 @@ rge_init(struct ifnet *ifp)
RGE_MAC_SETBIT(sc, 0xeb58, 0x0001);
val = rge_read_mac_ocp(sc, 0xe614) & ~0x0700;
- rge_write_mac_ocp(sc, 0xe614, val | 0x0400);
+ if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3)
+ rge_write_mac_ocp(sc, 0xe614, val | 0x0400);
+ else
+ rge_write_mac_ocp(sc, 0xe614, val | 0x0200);
RGE_MAC_CLRBIT(sc, 0xe63e, 0x0c00);
- val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0030;
- rge_write_mac_ocp(sc, 0xe63e, val | 0x0020);
+ if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) {
+ val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0030;
+ rge_write_mac_ocp(sc, 0xe63e, val | 0x0020);
+ } else
+ RGE_MAC_CLRBIT(sc, 0xe63e, 0x0030);
RGE_MAC_SETBIT(sc, 0xc0b4, 0x000c);
- val = rge_read_mac_ocp(sc, 0xeb6a) & ~0x007f;
+ val = rge_read_mac_ocp(sc, 0xeb6a) & ~0x00ff;
rge_write_mac_ocp(sc, 0xeb6a, val | 0x0033);
val = rge_read_mac_ocp(sc, 0xeb50) & ~0x03e0;
@@ -735,8 +749,13 @@ rge_init(struct ifnet *ifp)
RGE_WRITE_1(sc, RGE_TDFNR, 0x10);
+ RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_TX_10M_PS_EN);
+
RGE_MAC_CLRBIT(sc, 0xe040, 0x1000);
+ val = rge_read_mac_ocp(sc, 0xea1c) & ~0x0003;
+ rge_write_mac_ocp(sc, 0xea1c, val | 0x0001);
+
val = rge_read_mac_ocp(sc, 0xe0c0) & ~0x4f0f;
rge_write_mac_ocp(sc, 0xe0c0, val | 0x4403);
@@ -749,7 +768,16 @@ rge_init(struct ifnet *ifp)
val = rge_read_mac_ocp(sc, 0xd430) & ~0x0fff;
rge_write_mac_ocp(sc, 0xd430, val | 0x047f);
- RGE_MAC_SETBIT(sc, 0xe84c, 0x00c0);
+ val = rge_read_mac_ocp(sc, 0xe84c) & ~0x0040;
+ if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3)
+ rge_write_mac_ocp(sc, 0xe84c, 0x00c0);
+ else
+ rge_write_mac_ocp(sc, 0xe84c, 0x0080);
+
+ RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_PFM_EN);
+
+ if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3)
+ RGE_SETBIT_1(sc, RGE_MCUCMD, 0x01);
/* Disable EEE plus. */
RGE_MAC_CLRBIT(sc, 0xe080, 0x0002);
@@ -764,8 +792,10 @@ rge_init(struct ifnet *ifp)
rge_write_mac_ocp(sc, 0xe098, 0xc302);
- if (ifp->if_capabilities & ETHERCAP_VLAN_HWTAGGING)
+ if ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0)
RGE_SETBIT_4(sc, RGE_RXCFG, RGE_RXCFG_VLANSTRIP);
+ else
+ RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_VLANSTRIP);
RGE_SETBIT_2(sc, RGE_CPLUSCMD, RGE_CPLUSCMD_RXCSUM);
@@ -807,12 +837,15 @@ rge_init(struct ifnet *ifp)
* Stop the adapter and free any mbufs allocated to the RX and TX lists.
*/
void
-rge_stop(struct ifnet *ifp)
+rge_stop(struct ifnet *ifp, int disable)
{
struct rge_softc *sc = ifp->if_softc;
int i;
- timeout_del(&sc->sc_timeout);
+ if (disable) {
+ callout_halt(&sc->sc_timeout, NULL);
+ } else
+ callout_stop(&sc->sc_timeout);
ifp->if_timer = 0;
ifp->if_flags &= ~IFF_RUNNING;
@@ -823,12 +856,17 @@ rge_stop(struct ifnet *ifp)
RGE_RXCFG_ERRPKT);
RGE_WRITE_4(sc, RGE_IMR, 0);
- RGE_WRITE_4(sc, RGE_ISR, 0xffffffff);
+
+ /* Clear timer interrupts. */
+ RGE_WRITE_4(sc, RGE_TIMERINT0, 0);
+ RGE_WRITE_4(sc, RGE_TIMERINT1, 0);
+ RGE_WRITE_4(sc, RGE_TIMERINT2, 0);
+ RGE_WRITE_4(sc, RGE_TIMERINT3, 0);
rge_reset(sc);
- intr_barrier(sc->sc_ih);
- ifq_barrier(&ifp->if_snd);
+// intr_barrier(sc->sc_ih);
+// ifq_barrier(&ifp->if_snd);
/* ifq_clr_oactive(&ifp->if_snd); Sevan - OpenBSD queue API */
if (sc->rge_head != NULL) {
@@ -880,27 +918,34 @@ rge_ifmedia_upd(struct ifnet *ifp)
anar = gig = 0;
switch (IFM_SUBTYPE(ifm->ifm_media)) {
case IFM_AUTO:
- anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
- gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
+ anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
+ gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
val |= RGE_ADV_2500TFDX;
break;
case IFM_2500_T:
- anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
- gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
+ anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
+ gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
val |= RGE_ADV_2500TFDX;
ifp->if_baudrate = IF_Mbps(2500);
break;
case IFM_1000_T:
- anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
- gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
+ anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
+ gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
ifp->if_baudrate = IF_Gbps(1);
break;
case IFM_100_TX:
- anar |= ANAR_TX | ANAR_TX_FD;
+ gig = rge_read_phy(sc, 0, MII_100T2CR) &
+ ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX);
+ anar = ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) ?
+ ANAR_TX | ANAR_TX_FD | ANAR_10_FD | ANAR_10 :
+ ANAR_TX | ANAR_10_FD | ANAR_10;
ifp->if_baudrate = IF_Mbps(100);
break;
case IFM_10_T:
- anar |= ANAR_10 | ANAR_10_FD;
+ gig = rge_read_phy(sc, 0, MII_100T2CR) &
+ ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX);
+ anar = ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) ?
+ ANAR_10_FD | ANAR_10 : ANAR_10;
ifp->if_baudrate = IF_Mbps(10);
break;
default:
@@ -912,7 +957,8 @@ rge_ifmedia_upd(struct ifnet *ifp)
rge_write_phy(sc, 0, MII_ANAR, anar | ANAR_PAUSE_ASYM | ANAR_FC);
rge_write_phy(sc, 0, MII_100T2CR, gig);
rge_write_phy_ocp(sc, 0xa5d4, val);
- rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
+ rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |
+ BMCR_STARTNEG);
return (0);
}
@@ -967,7 +1013,7 @@ rge_allocmem(struct rge_softc *sc)
}
error = bus_dmamem_alloc(sc->sc_dmat, RGE_TX_LIST_SZ, RGE_ALIGN, 0,
&sc->rge_ldata.rge_tx_listseg, 1, &sc->rge_ldata.rge_tx_listnseg,
- BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */
+ BUS_DMA_NOWAIT);
if (error) {
aprint_error_dev(sc->sc_dev, "can't alloc TX list\n");
return (error);
@@ -977,13 +1023,14 @@ rge_allocmem(struct rge_softc *sc)
error = bus_dmamem_map(sc->sc_dmat, &sc->rge_ldata.rge_tx_listseg,
sc->rge_ldata.rge_tx_listnseg, RGE_TX_LIST_SZ,
(void **) &sc->rge_ldata.rge_tx_list,
- BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */
+ BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
if (error) {
aprint_error_dev(sc->sc_dev, "can't map TX dma buffers\n");
bus_dmamem_free(sc->sc_dmat, &sc->rge_ldata.rge_tx_listseg,
sc->rge_ldata.rge_tx_listnseg);
return (error);
}
+ memset(sc->rge_ldata.rge_tx_list, 0, RGE_TX_LIST_SZ);
error = bus_dmamap_load(sc->sc_dmat, sc->rge_ldata.rge_tx_list_map,
sc->rge_ldata.rge_tx_list, RGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT);
if (error) {
@@ -1016,7 +1063,7 @@ rge_allocmem(struct rge_softc *sc)
}
error = bus_dmamem_alloc(sc->sc_dmat, RGE_RX_LIST_SZ, RGE_ALIGN, 0,
&sc->rge_ldata.rge_rx_listseg, 1, &sc->rge_ldata.rge_rx_listnseg,
- BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_ZERO */
+ BUS_DMA_NOWAIT);
if (error) {
aprint_error_dev(sc->sc_dev, "can't alloc RX list\n");
return (error);
@@ -1026,13 +1073,14 @@ rge_allocmem(struct rge_softc *sc)
error = bus_dmamem_map(sc->sc_dmat, &sc->rge_ldata.rge_rx_listseg,
sc->rge_ldata.rge_rx_listnseg, RGE_RX_LIST_SZ,
(void **) &sc->rge_ldata.rge_rx_list,
- BUS_DMA_NOWAIT); /* XXX OpenBSD adds BUS_DMA_COHERENT */
+ BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
if (error) {
aprint_error_dev(sc->sc_dev, "can't map RX dma buffers\n");
bus_dmamem_free(sc->sc_dmat, &sc->rge_ldata.rge_rx_listseg,
sc->rge_ldata.rge_rx_listnseg);
return (error);
}
+ memset(sc->rge_ldata.rge_rx_list, 0, RGE_RX_LIST_SZ);
error = bus_dmamap_load(sc->sc_dmat, sc->rge_ldata.rge_rx_list_map,
sc->rge_ldata.rge_rx_list, RGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT);
if (error) {
@@ -1070,7 +1118,7 @@ rge_newbuf(struct rge_softc *sc, int idx
struct rge_rxq *rxq;
bus_dmamap_t rxmap;
- m = MCLGETI(NULL, M_DONTWAIT, NULL, RGE_JUMBO_FRAMELEN);
+ m = MCLGETL(NULL, M_DONTWAIT, RGE_JUMBO_FRAMELEN);
if (m == NULL)
return (ENOBUFS);
@@ -1147,7 +1195,7 @@ rge_rx_list_init(struct rge_softc *sc)
return (ENOBUFS);
}
- sc->rge_ldata.rge_rxq_prodidx = 0;
+ sc->rge_ldata.rge_rxq_prodidx = sc->rge_ldata.rge_rxq_considx = 0;
sc->rge_head = sc->rge_tail = NULL;
return (0);
@@ -1173,7 +1221,6 @@ rge_tx_list_init(struct rge_softc *sc)
int
rge_rxeof(struct rge_softc *sc)
{
- struct mbuf_list ml = MBUF_LIST_INITIALIZER();
struct mbuf *m;
struct ifnet *ifp = &sc->sc_ec.ec_if;
struct rge_rx_desc *cur_rx;
@@ -1181,7 +1228,7 @@ rge_rxeof(struct rge_softc *sc)
uint32_t rxstat, extsts;
int i, total_len, rx = 0;
- for (i = sc->rge_ldata.rge_rxq_prodidx; ; i = RGE_NEXT_RX_DESC(i)) {
+ for (i = sc->rge_ldata.rge_rxq_considx; ; i = RGE_NEXT_RX_DESC(i)) {
/* Invalidate the descriptor memory. */
bus_dmamap_sync(sc->sc_dmat, sc->rge_ldata.rge_rx_list_map,
i * sizeof(struct rge_rx_desc), sizeof(struct rge_rx_desc),
@@ -1198,6 +1245,7 @@ rge_rxeof(struct rge_softc *sc)
total_len = RGE_RXBYTES(cur_rx);
rxq = &sc->rge_ldata.rge_rxq[i];
m = rxq->rxq_mbuf;
+ rxq->rxq_mbuf = NULL;
rx = 1;
/* Invalidate the RX mbuf and unload its map. */
@@ -1239,6 +1287,7 @@ rge_rxeof(struct rge_softc *sc)
continue;
}
+ m_set_rcvif(m, ifp);
if (sc->rge_head != NULL) {
m->m_len = total_len;
/*
@@ -1260,9 +1309,17 @@ rge_rxeof(struct rge_softc *sc)
sc->rge_head = sc->rge_tail = NULL;
m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
} else
+ #if 0
m->m_pkthdr.len = m->m_len =
(total_len - ETHER_CRC_LEN);
+ #else
+ {
+ m->m_pkthdr.len = m->m_len = total_len;
+ m->m_flags |= M_HASFCS;
+ }
+ #endif
+#if notyet
/* Check IP header checksum. */
if (!(rxstat & RGE_RDCMDSTS_IPCSUMERR) &&
(extsts & RGE_RDEXTSTS_IPV4))
@@ -1276,21 +1333,17 @@ rge_rxeof(struct rge_softc *sc)
!(rxstat & RGE_RDCMDSTS_UDPCSUMERR))))
m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK |
M_UDP_CSUM_IN_OK;
+#endif
-#if NVLAN > 0
if (extsts & RGE_RDEXTSTS_VTAG) {
- m->m_pkthdr.ether_vtag =
- ntohs(extsts & RGE_RDEXTSTS_VLAN_MASK);
- m->m_flags |= M_VLANTAG;
+ vlan_set_tag(m,
+ bswap16(extsts & RGE_RDEXTSTS_VLAN_MASK));
}
-#endif
- ml_enqueue(&ml, m);
+ if_percpuq_enqueue(ifp->if_percpuq, m);
}
- sc->rge_ldata.rge_rxq_prodidx = i;
-
- if_input(ifp, &ml);
+ sc->rge_ldata.rge_rxq_considx = i;
return (rx);
}
@@ -1348,12 +1401,24 @@ rge_txeof(struct rge_softc *sc)
sc->rge_ldata.rge_txq_considx = cons;
+#if 0
if (ifq_is_oactive(&ifp->if_snd))
ifq_restart(&ifp->if_snd);
else if (free == 2)
ifq_serialize(&ifp->if_snd, &sc->sc_task);
else
ifp->if_timer = 0;
+#else
+#if 0
+ if (!IF_IS_EMPTY(&ifp->if_snd))
+ rge_start(ifp);
+ else
+ if (free == 2)
+ if (0) { rge_txstart(&sc->sc_task, sc); }
+ else
+#endif
+ ifp->if_timer = 0;
+#endif
return (1);
}
@@ -1367,13 +1432,22 @@ rge_reset(struct rge_softc *sc)
RGE_SETBIT_1(sc, RGE_PPSW, 0x08);
DELAY(2000);
- for (i = 0; i < 10; i++) {
- DELAY(100);
+ for (i = 0; i < 3000; i++) {
+ DELAY(50);
if ((RGE_READ_1(sc, RGE_MCUCMD) & (RGE_MCUCMD_RXFIFO_EMPTY |
RGE_MCUCMD_TXFIFO_EMPTY)) == (RGE_MCUCMD_RXFIFO_EMPTY |
RGE_MCUCMD_TXFIFO_EMPTY))
break;
}
+ if (sc->rge_type == MAC_CFG4 || sc->rge_type == MAC_CFG5) {
+ for (i = 0; i < 3000; i++) {
+ DELAY(50);
+ if ((RGE_READ_2(sc, RGE_IM) & 0x0103) == 0x0103)
+ break;
+ }
+ }
+
+ DELAY(2000);
/* Soft reset. */
RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_RESET);
@@ -1391,7 +1465,7 @@ void
rge_iff(struct rge_softc *sc)
{
struct ifnet *ifp = &sc->sc_ec.ec_if;
- struct ethercom *ac = &sc->sc_ec;
+ struct ethercom *ec = &sc->sc_ec;
struct ether_multi *enm;
struct ether_multistep step;
uint32_t hashes[2];
@@ -1408,7 +1482,8 @@ rge_iff(struct rge_softc *sc)
*/
rxfilt |= RGE_RXCFG_INDIV | RGE_RXCFG_BROAD;
- if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) {
+ if (ifp->if_flags & IFF_PROMISC) {
+ allmulti:
ifp->if_flags |= IFF_ALLMULTI;
rxfilt |= RGE_RXCFG_MULTI;
if (ifp->if_flags & IFF_PROMISC)
@@ -1419,8 +1494,14 @@ rge_iff(struct rge_softc *sc)
/* Program new filter. */
memset(hashes, 0, sizeof(hashes));
- ETHER_FIRST_MULTI(step, ac, enm);
+ ETHER_LOCK(ec);
+ ETHER_FIRST_MULTI(step, ec, enm);
while (enm != NULL) {
+ if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
+ ETHER_ADDR_LEN) != 0) {
+ ETHER_UNLOCK(ec);
+ goto allmulti;
+ }
h = ether_crc32_be(enm->enm_addrlo,
ETHER_ADDR_LEN) >> 26;
@@ -1431,6 +1512,7 @@ rge_iff(struct rge_softc *sc)
ETHER_NEXT_MULTI(step, enm);
}
+ ETHER_UNLOCK(ec);
}
RGE_WRITE_4(sc, RGE_RXCFG, rxfilt);
@@ -1453,14 +1535,138 @@ rge_set_phy_power(struct rge_softc *sc,
break;
DELAY(1000);
}
- } else
+ } else {
rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN);
+ RGE_CLRBIT_1(sc, RGE_PMCH, 0x80);
+ RGE_CLRBIT_1(sc, RGE_PPSW, 0x40);
+ }
}
void
rge_phy_config(struct rge_softc *sc)
{
- uint16_t mcode_ver, val;
+ /* Read microcode version. */
+ rge_write_phy_ocp(sc, 0xa436, 0x801e);
+ sc->rge_mcodever = rge_read_phy_ocp(sc, 0xa438);
+
+ switch (sc->rge_type) {
+ case MAC_CFG2:
+ rge_phy_config_mac_cfg2(sc);
+ break;
+ case MAC_CFG3:
+ rge_phy_config_mac_cfg3(sc);
+ break;
+ case MAC_CFG4:
+ rge_phy_config_mac_cfg4(sc);
+ break;
+ case MAC_CFG5:
+ rge_phy_config_mac_cfg5(sc);
+ break;
+ default:
+ break; /* Can't happen. */
+ }
+
+ rge_write_phy(sc, 0x0a5b, 0x12,
+ rge_read_phy(sc, 0x0a5b, 0x12) & ~0x8000);
+
+ /* Disable EEE. */
+ RGE_MAC_CLRBIT(sc, 0xe040, 0x0003);
+ if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) {
+ RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006);
+ RGE_PHY_CLRBIT(sc, 0xa432, 0x0010);
+ }
+ RGE_PHY_CLRBIT(sc, 0xa5d0, 0x0006);
+ RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001);
+ RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010);
+ RGE_PHY_CLRBIT(sc, 0xa428, 0x0080);
+ RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200);
+
+ rge_patch_phy_mcu(sc, 1);
+ RGE_MAC_CLRBIT(sc, 0xe052, 0x0001);
+ RGE_PHY_CLRBIT(sc, 0xa442, 0x3000);
+ RGE_PHY_CLRBIT(sc, 0xa430, 0x8000);
+ rge_patch_phy_mcu(sc, 0);
+}
+
+void
+rge_phy_config_mac_cfg2(struct rge_softc *sc)
+{
+ uint16_t val;
+ int i;
+
+ for (i = 0; i < nitems(rtl8125_mac_cfg2_ephy); i++)
+ rge_write_ephy(sc, rtl8125_mac_cfg2_ephy[i].reg,
+ rtl8125_mac_cfg2_ephy[i].val);
+
+ rge_phy_config_mcu(sc, RGE_MAC_CFG2_MCODE_VER);
+
+ val = rge_read_phy_ocp(sc, 0xad40) & ~0x03ff;
+ rge_write_phy_ocp(sc, 0xad40, val | 0x0084);
+ RGE_PHY_SETBIT(sc, 0xad4e, 0x0010);
+ val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff;
+ rge_write_phy_ocp(sc, 0xad16, val | 0x0006);
+ val = rge_read_phy_ocp(sc, 0xad32) & ~0x03ff;
+ rge_write_phy_ocp(sc, 0xad32, val | 0x0006);
+ RGE_PHY_CLRBIT(sc, 0xac08, 0x1100);
+ val = rge_read_phy_ocp(sc, 0xac8a) & ~0xf000;
+ rge_write_phy_ocp(sc, 0xac8a, val | 0x7000);
+ RGE_PHY_SETBIT(sc, 0xad18, 0x0400);
+ RGE_PHY_SETBIT(sc, 0xad1a, 0x03ff);
+ RGE_PHY_SETBIT(sc, 0xad1c, 0x03ff);
+
+ rge_write_phy_ocp(sc, 0xa436, 0x80ea);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0xc400);
+ rge_write_phy_ocp(sc, 0xa436, 0x80eb);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0x0700;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x0300);
+ rge_write_phy_ocp(sc, 0xa436, 0x80f8);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x1c00);
+ rge_write_phy_ocp(sc, 0xa436, 0x80f1);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x3000);
+ rge_write_phy_ocp(sc, 0xa436, 0x80fe);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0xa500);
+ rge_write_phy_ocp(sc, 0xa436, 0x8102);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x5000);
+ rge_write_phy_ocp(sc, 0xa436, 0x8105);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x3300);
+ rge_write_phy_ocp(sc, 0xa436, 0x8100);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x7000);
+ rge_write_phy_ocp(sc, 0xa436, 0x8104);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0xf000);
+ rge_write_phy_ocp(sc, 0xa436, 0x8106);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x6500);
+ rge_write_phy_ocp(sc, 0xa436, 0x80dc);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0xed00);
+ rge_write_phy_ocp(sc, 0xa436, 0x80df);
+ RGE_PHY_SETBIT(sc, 0xa438, 0x0100);
+ rge_write_phy_ocp(sc, 0xa436, 0x80e1);
+ RGE_PHY_CLRBIT(sc, 0xa438, 0x0100);
+ val = rge_read_phy_ocp(sc, 0xbf06) & ~0x003f;
+ rge_write_phy_ocp(sc, 0xbf06, val | 0x0038);
+ rge_write_phy_ocp(sc, 0xa436, 0x819f);
+ rge_write_phy_ocp(sc, 0xa438, 0xd0b6);
+ rge_write_phy_ocp(sc, 0xbc34, 0x5555);
+ val = rge_read_phy_ocp(sc, 0xbf0a) & ~0x0e00;
+ rge_write_phy_ocp(sc, 0xbf0a, val | 0x0a00);
+ RGE_PHY_CLRBIT(sc, 0xa5c0, 0x0400);
+ RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
+}
+
+void
+rge_phy_config_mac_cfg3(struct rge_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ uint16_t val;
int i;
static const uint16_t mac_cfg3_a438_value[] =
{ 0x0043, 0x00a7, 0x00d6, 0x00ec, 0x00f6, 0x00fb, 0x00fd, 0x00ff,
@@ -1474,135 +1680,375 @@ rge_phy_config(struct rge_softc *sc)
0xc022, 0x175a, 0xc024, 0x19c0, 0xc026, 0x1c26, 0xc089, 0x6050,
0xc08a, 0x5f6e, 0xc08c, 0x6e6e, 0xc08e, 0x6e6e, 0xc090, 0x6e12 };
- /* Read microcode version. */
- rge_write_phy_ocp(sc, 0xa436, 0x801e);
- mcode_ver = rge_read_phy_ocp(sc, 0xa438);
+ for (i = 0; i < nitems(rtl8125_mac_cfg3_ephy); i++)
+ rge_write_ephy(sc, rtl8125_mac_cfg3_ephy[i].reg,
+ rtl8125_mac_cfg3_ephy[i].val);
+
+ val = rge_read_ephy(sc, 0x002a) & ~0x7000;
+ rge_write_ephy(sc, 0x002a, val | 0x3000);
+ RGE_EPHY_CLRBIT(sc, 0x0019, 0x0040);
+ RGE_EPHY_SETBIT(sc, 0x001b, 0x0e00);
+ RGE_EPHY_CLRBIT(sc, 0x001b, 0x7000);
+ rge_write_ephy(sc, 0x0002, 0x6042);
+ rge_write_ephy(sc, 0x0006, 0x0014);
+ val = rge_read_ephy(sc, 0x006a) & ~0x7000;
+ rge_write_ephy(sc, 0x006a, val | 0x3000);
+ RGE_EPHY_CLRBIT(sc, 0x0059, 0x0040);
+ RGE_EPHY_SETBIT(sc, 0x005b, 0x0e00);
+ RGE_EPHY_CLRBIT(sc, 0x005b, 0x7000);
+ rge_write_ephy(sc, 0x0042, 0x6042);
+ rge_write_ephy(sc, 0x0046, 0x0014);
+
+ rge_phy_config_mcu(sc, RGE_MAC_CFG3_MCODE_VER);
+
+ RGE_PHY_SETBIT(sc, 0xad4e, 0x0010);
+ val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff;
+ rge_write_phy_ocp(sc, 0xad16, val | 0x03ff);
+ val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f;
+ rge_write_phy_ocp(sc, 0xad32, val | 0x0006);
+ RGE_PHY_CLRBIT(sc, 0xac08, 0x1000);
+ RGE_PHY_CLRBIT(sc, 0xac08, 0x0100);
+ val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003;
+ rge_write_phy_ocp(sc, 0xacc0, val | 0x0002);
+ val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0;
+ rge_write_phy_ocp(sc, 0xad40, val | 0x0040);
+ val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007;
+ rge_write_phy_ocp(sc, 0xad40, val | 0x0004);
+ RGE_PHY_CLRBIT(sc, 0xac14, 0x0080);
+ RGE_PHY_CLRBIT(sc, 0xac80, 0x0300);
+ val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007;
+ rge_write_phy_ocp(sc, 0xac5e, val | 0x0002);
+ rge_write_phy_ocp(sc, 0xad4c, 0x00a8);
+ rge_write_phy_ocp(sc, 0xac5c, 0x01ff);
+ val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0;
+ rge_write_phy_ocp(sc, 0xac8a, val | 0x0030);
+ rge_write_phy_ocp(sc, 0xb87c, 0x8157);
+ val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
+ rge_write_phy_ocp(sc, 0xb87c, 0x8159);
+ val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
+ RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, ifp->if_mtu + ETHER_HDR_LEN +
+ 32);
+ rge_write_phy_ocp(sc, 0xb87c, 0x80a2);
+ rge_write_phy_ocp(sc, 0xb87e, 0x0153);
+ rge_write_phy_ocp(sc, 0xb87c, 0x809c);
+ rge_write_phy_ocp(sc, 0xb87e, 0x0153);
+
+ rge_write_phy_ocp(sc, 0xa436, 0x81b3);
+ for (i = 0; i < nitems(mac_cfg3_a438_value); i++)
+ rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]);
+ for (i = 0; i < 26; i++)
+ rge_write_phy_ocp(sc, 0xa438, 0);
+ rge_write_phy_ocp(sc, 0xa436, 0x8257);
+ rge_write_phy_ocp(sc, 0xa438, 0x020f);
+ rge_write_phy_ocp(sc, 0xa436, 0x80ea);
+ rge_write_phy_ocp(sc, 0xa438, 0x7843);
- if (sc->rge_type == MAC_CFG2) {
- for (i = 0; i < nitems(rtl8125_mac_cfg2_ephy); i++) {
- rge_write_ephy(sc, rtl8125_mac_cfg2_ephy[i].reg,
- rtl8125_mac_cfg2_ephy[i].val);
- }
+ rge_patch_phy_mcu(sc, 1);
+ RGE_PHY_CLRBIT(sc, 0xb896, 0x0001);
+ RGE_PHY_CLRBIT(sc, 0xb892, 0xff00);
+ for (i = 0; i < nitems(mac_cfg3_b88e_value); i += 2) {
+ rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]);
+ rge_write_phy_ocp(sc, 0xb890, mac_cfg3_b88e_value[i + 1]);
+ }
+ RGE_PHY_SETBIT(sc, 0xb896, 0x0001);
+ rge_patch_phy_mcu(sc, 0);
- if (mcode_ver != RGE_MAC_CFG2_MCODE_VER) {
- /* Disable PHY config. */
- RGE_CLRBIT_1(sc, 0xf2, 0x20);
- DELAY(1000);
+ RGE_PHY_SETBIT(sc, 0xd068, 0x2000);
+ rge_write_phy_ocp(sc, 0xa436, 0x81a2);
+ RGE_PHY_SETBIT(sc, 0xa438, 0x0100);
+ val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00);
+ RGE_PHY_CLRBIT(sc, 0xa454, 0x0001);
+ RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020);
+ RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010);
+ RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001);
+ RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
+}
+
+void
+rge_phy_config_mac_cfg4(struct rge_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ uint16_t val;
+ int i;
+ static const uint16_t mac_cfg4_b87c_value[] =
+ { 0x8013, 0x0700, 0x8fb9, 0x2801, 0x8fba, 0x0100, 0x8fbc, 0x1900,
+ 0x8fbe, 0xe100, 0x8fc0, 0x0800, 0x8fc2, 0xe500, 0x8fc4, 0x0f00,
+ 0x8fc6, 0xf100, 0x8fc8, 0x0400, 0x8fca, 0xf300, 0x8fcc, 0xfd00,
+ 0x8fce, 0xff00, 0x8fd0, 0xfb00, 0x8fd2, 0x0100, 0x8fd4, 0xf400,
+ 0x8fd6, 0xff00, 0x8fd8, 0xf600, 0x813d, 0x390e, 0x814f, 0x790e,
+ 0x80b0, 0x0f31 };
+
+ for (i = 0; i < nitems(rtl8125_mac_cfg4_ephy); i++)
+ rge_write_ephy(sc, rtl8125_mac_cfg4_ephy[i].reg,
+ rtl8125_mac_cfg4_ephy[i].val);
+
+ rge_write_phy_ocp(sc, 0xbf86, 0x9000);
+ RGE_PHY_SETBIT(sc, 0xc402, 0x0400);
+ RGE_PHY_CLRBIT(sc, 0xc402, 0x0400);
+ rge_write_phy_ocp(sc, 0xbd86, 0x1010);
+ rge_write_phy_ocp(sc, 0xbd88, 0x1010);
+ val = rge_read_phy_ocp(sc, 0xbd4e) & ~0x0c00;
+ rge_write_phy_ocp(sc, 0xbd4e, val | 0x0800);
+ val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00;
+ rge_write_phy_ocp(sc, 0xbf46, val | 0x0700);
+
+ rge_phy_config_mcu(sc, RGE_MAC_CFG4_MCODE_VER);
+
+ RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
+ RGE_PHY_SETBIT(sc, 0xbc08, 0x000c);
+ rge_write_phy_ocp(sc, 0xa436, 0x8fff);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x0400);
+ for (i = 0; i < 6; i++) {
+ rge_write_phy_ocp(sc, 0xb87c, 0x8560 + i * 2);
+ if (i < 3)
+ rge_write_phy_ocp(sc, 0xb87e, 0x19cc);
+ else
+ rge_write_phy_ocp(sc, 0xb87e, 0x147d);
+ }
+ rge_write_phy_ocp(sc, 0xb87c, 0x8ffe);
+ rge_write_phy_ocp(sc, 0xb87e, 0x0907);
+ val = rge_read_phy_ocp(sc, 0xacda) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xacda, val | 0xff00);
+ val = rge_read_phy_ocp(sc, 0xacde) & ~0xf000;
+ rge_write_phy_ocp(sc, 0xacde, val | 0xf000);
+ rge_write_phy_ocp(sc, 0xb87c, 0x80d6);
+ rge_write_phy_ocp(sc, 0xb87e, 0x2801);
+ rge_write_phy_ocp(sc, 0xb87c, 0x80F2);
+ rge_write_phy_ocp(sc, 0xb87e, 0x2801);
+ rge_write_phy_ocp(sc, 0xb87c, 0x80f4);
+ rge_write_phy_ocp(sc, 0xb87e, 0x6077);
+ rge_write_phy_ocp(sc, 0xb506, 0x01e7);
+ rge_write_phy_ocp(sc, 0xac8c, 0x0ffc);
+ rge_write_phy_ocp(sc, 0xac46, 0xb7b4);
+ rge_write_phy_ocp(sc, 0xac50, 0x0fbc);
+ rge_write_phy_ocp(sc, 0xac3c, 0x9240);
+ rge_write_phy_ocp(sc, 0xac4E, 0x0db4);
+ rge_write_phy_ocp(sc, 0xacc6, 0x0707);
+ rge_write_phy_ocp(sc, 0xacc8, 0xa0d3);
+ rge_write_phy_ocp(sc, 0xad08, 0x0007);
+ for (i = 0; i < nitems(mac_cfg4_b87c_value); i += 2) {
+ rge_write_phy_ocp(sc, 0xb87c, mac_cfg4_b87c_value[i]);
+ rge_write_phy_ocp(sc, 0xb87e, mac_cfg4_b87c_value[i + 1]);
+ }
+ RGE_PHY_SETBIT(sc, 0xbf4c, 0x0002);
+ RGE_PHY_SETBIT(sc, 0xbcca, 0x0300);
+ rge_write_phy_ocp(sc, 0xb87c, 0x8141);
+ rge_write_phy_ocp(sc, 0xb87e, 0x320e);
+ rge_write_phy_ocp(sc, 0xb87c, 0x8153);
+ rge_write_phy_ocp(sc, 0xb87e, 0x720e);
+ RGE_PHY_CLRBIT(sc, 0xa432, 0x0040);
+ rge_write_phy_ocp(sc, 0xb87c, 0x8529);
+ rge_write_phy_ocp(sc, 0xb87e, 0x050e);
+ RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, ifp->if_mtu + ETHER_HDR_LEN +
+ 32);
+ rge_write_phy_ocp(sc, 0xa436, 0x816c);
+ rge_write_phy_ocp(sc, 0xa438, 0xc4a0);
+ rge_write_phy_ocp(sc, 0xa436, 0x8170);
+ rge_write_phy_ocp(sc, 0xa438, 0xc4a0);
+ rge_write_phy_ocp(sc, 0xa436, 0x8174);
+ rge_write_phy_ocp(sc, 0xa438, 0x04a0);
+ rge_write_phy_ocp(sc, 0xa436, 0x8178);
+ rge_write_phy_ocp(sc, 0xa438, 0x04a0);
+ rge_write_phy_ocp(sc, 0xa436, 0x817c);
+ rge_write_phy_ocp(sc, 0xa438, 0x0719);
+ rge_write_phy_ocp(sc, 0xa436, 0x8ff4);
+ rge_write_phy_ocp(sc, 0xa438, 0x0400);
+ rge_write_phy_ocp(sc, 0xa436, 0x8ff1);
+ rge_write_phy_ocp(sc, 0xa438, 0x0404);
+ rge_write_phy_ocp(sc, 0xbf4a, 0x001b);
+ for (i = 0; i < 6; i++) {
+ rge_write_phy_ocp(sc, 0xb87c, 0x8033 + i * 4);
+ if (i == 2)
+ rge_write_phy_ocp(sc, 0xb87e, 0xfc32);
+ else
+ rge_write_phy_ocp(sc, 0xb87e, 0x7c13);
+ }
+ rge_write_phy_ocp(sc, 0xb87c, 0x8145);
+ rge_write_phy_ocp(sc, 0xb87e, 0x370e);
+ rge_write_phy_ocp(sc, 0xb87c, 0x8157);
+ rge_write_phy_ocp(sc, 0xb87e, 0x770e);
+ rge_write_phy_ocp(sc, 0xb87c, 0x8169);
+ rge_write_phy_ocp(sc, 0xb87e, 0x0d0a);
+ rge_write_phy_ocp(sc, 0xb87c, 0x817b);
+ rge_write_phy_ocp(sc, 0xb87e, 0x1d0a);
+ rge_write_phy_ocp(sc, 0xa436, 0x8217);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x5000);
+ rge_write_phy_ocp(sc, 0xa436, 0x821a);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x5000);
+ rge_write_phy_ocp(sc, 0xa436, 0x80da);
+ rge_write_phy_ocp(sc, 0xa438, 0x0403);
+ rge_write_phy_ocp(sc, 0xa436, 0x80dc);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
+ rge_write_phy_ocp(sc, 0xa436, 0x80b3);
+ rge_write_phy_ocp(sc, 0xa438, 0x0384);
+ rge_write_phy_ocp(sc, 0xa436, 0x80b7);
+ rge_write_phy_ocp(sc, 0xa438, 0x2007);
+ rge_write_phy_ocp(sc, 0xa436, 0x80ba);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x6c00);
+ rge_write_phy_ocp(sc, 0xa436, 0x80b5);
+ rge_write_phy_ocp(sc, 0xa438, 0xf009);
+ rge_write_phy_ocp(sc, 0xa436, 0x80bd);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x9f00);
+ rge_write_phy_ocp(sc, 0xa436, 0x80c7);
+ rge_write_phy_ocp(sc, 0xa438, 0xf083);
+ rge_write_phy_ocp(sc, 0xa436, 0x80dd);
+ rge_write_phy_ocp(sc, 0xa438, 0x03f0);
+ rge_write_phy_ocp(sc, 0xa436, 0x80df);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
+ rge_write_phy_ocp(sc, 0xa436, 0x80cb);
+ rge_write_phy_ocp(sc, 0xa438, 0x2007);
+ rge_write_phy_ocp(sc, 0xa436, 0x80ce);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x6c00);
+ rge_write_phy_ocp(sc, 0xa436, 0x80c9);
+ rge_write_phy_ocp(sc, 0xa438, 0x8009);
+ rge_write_phy_ocp(sc, 0xa436, 0x80d1);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0x8000);
+ rge_write_phy_ocp(sc, 0xa436, 0x80a3);
+ rge_write_phy_ocp(sc, 0xa438, 0x200a);
+ rge_write_phy_ocp(sc, 0xa436, 0x80a5);
+ rge_write_phy_ocp(sc, 0xa438, 0xf0ad);
+ rge_write_phy_ocp(sc, 0xa436, 0x809f);
+ rge_write_phy_ocp(sc, 0xa438, 0x6073);
+ rge_write_phy_ocp(sc, 0xa436, 0x80a1);
+ rge_write_phy_ocp(sc, 0xa438, 0x000b);
+ rge_write_phy_ocp(sc, 0xa436, 0x80a9);
+ val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xa438, val | 0xc000);
+ rge_patch_phy_mcu(sc, 1);
+ RGE_PHY_CLRBIT(sc, 0xb896, 0x0001);
+ RGE_PHY_CLRBIT(sc, 0xb892, 0xff00);
+ rge_write_phy_ocp(sc, 0xb88e, 0xc23e);
+ rge_write_phy_ocp(sc, 0xb890, 0x0000);
+ rge_write_phy_ocp(sc, 0xb88e, 0xc240);
+ rge_write_phy_ocp(sc, 0xb890, 0x0103);
+ rge_write_phy_ocp(sc, 0xb88e, 0xc242);
+ rge_write_phy_ocp(sc, 0xb890, 0x0507);
+ rge_write_phy_ocp(sc, 0xb88e, 0xc244);
+ rge_write_phy_ocp(sc, 0xb890, 0x090b);
+ rge_write_phy_ocp(sc, 0xb88e, 0xc246);
+ rge_write_phy_ocp(sc, 0xb890, 0x0c0e);
+ rge_write_phy_ocp(sc, 0xb88e, 0xc248);
+ rge_write_phy_ocp(sc, 0xb890, 0x1012);
+ rge_write_phy_ocp(sc, 0xb88e, 0xc24a);
+ rge_write_phy_ocp(sc, 0xb890, 0x1416);
+ RGE_PHY_SETBIT(sc, 0xb896, 0x0001);
+ rge_patch_phy_mcu(sc, 0);
+ RGE_PHY_SETBIT(sc, 0xa86a, 0x0001);
+ RGE_PHY_SETBIT(sc, 0xa6f0, 0x0001);
+ rge_write_phy_ocp(sc, 0xbfa0, 0xd70d);
+ rge_write_phy_ocp(sc, 0xbfa2, 0x4100);
+ rge_write_phy_ocp(sc, 0xbfa4, 0xe868);
+ rge_write_phy_ocp(sc, 0xbfa6, 0xdc59);
+ rge_write_phy_ocp(sc, 0xb54c, 0x3c18);
+ RGE_PHY_CLRBIT(sc, 0xbfa4, 0x0020);
+ rge_write_phy_ocp(sc, 0xa436, 0x817d);
+ RGE_PHY_SETBIT(sc, 0xa438, 0x1000);
+}
- rge_patch_phy_mcu(sc, 1);
+void
+rge_phy_config_mac_cfg5(struct rge_softc *sc)
+{
+ struct ifnet *ifp = &sc->sc_ec.ec_if;
+ uint16_t val;
+ int i;
+
+ for (i = 0; i < nitems(rtl8125_mac_cfg5_ephy); i++)
+ rge_write_ephy(sc, rtl8125_mac_cfg5_ephy[i].reg,
+ rtl8125_mac_cfg5_ephy[i].val);
+
+ val = rge_read_ephy(sc, 0x0022) & ~0x0030;
+ rge_write_ephy(sc, 0x0022, val | 0x0020);
+ val = rge_read_ephy(sc, 0x0062) & ~0x0030;
+ rge_write_ephy(sc, 0x0062, val | 0x0020);
+
+ rge_phy_config_mcu(sc, RGE_MAC_CFG5_MCODE_VER);
+
+ RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
+ val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0;
+ rge_write_phy_ocp(sc, 0xac46, val | 0x0090);
+ val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003;
+ rge_write_phy_ocp(sc, 0xad30, val | 0x0001);
+ RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, ifp->if_mtu + ETHER_HDR_LEN +
+ 32);
+ rge_write_phy_ocp(sc, 0xb87c, 0x80f5);
+ rge_write_phy_ocp(sc, 0xb87e, 0x760e);
+ rge_write_phy_ocp(sc, 0xb87c, 0x8107);
+ rge_write_phy_ocp(sc, 0xb87e, 0x360e);
+ rge_write_phy_ocp(sc, 0xb87c, 0x8551);
+ val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
+ rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
+ val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000;
+ rge_write_phy_ocp(sc, 0xbf00, val | 0xa000);
+ val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00;
+ rge_write_phy_ocp(sc, 0xbf46, val | 0x0300);
+ for (i = 0; i < 10; i++) {
+ rge_write_phy_ocp(sc, 0xa436, 0x8044 + i * 6);
+ rge_write_phy_ocp(sc, 0xa438, 0x2417);
+ }
+ RGE_PHY_SETBIT(sc, 0xa4ca, 0x0040);
+ val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000;
+ rge_write_phy_ocp(sc, 0xbf84, val | 0xa000);
+}
+
+void
+rge_phy_config_mcu(struct rge_softc *sc, uint16_t mcode_version)
+{
+ if (sc->rge_mcodever != mcode_version) {
+ int i;
+
+ rge_patch_phy_mcu(sc, 1);
+ if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) {
rge_write_phy_ocp(sc, 0xa436, 0x8024);
- rge_write_phy_ocp(sc, 0xa438, 0x8600);
+ if (sc->rge_type == MAC_CFG2)
+ rge_write_phy_ocp(sc, 0xa438, 0x8600);
+ else
+ rge_write_phy_ocp(sc, 0xa438, 0x8601);
rge_write_phy_ocp(sc, 0xa436, 0xb82e);
rge_write_phy_ocp(sc, 0xa438, 0x0001);
RGE_PHY_SETBIT(sc, 0xb820, 0x0080);
+ }
+
+ if (sc->rge_type == MAC_CFG2) {
for (i = 0; i < nitems(rtl8125_mac_cfg2_mcu); i++) {
rge_write_phy_ocp(sc,
rtl8125_mac_cfg2_mcu[i].reg,
rtl8125_mac_cfg2_mcu[i].val);
}
- RGE_PHY_CLRBIT(sc, 0xb820, 0x0080);
-
- rge_write_phy_ocp(sc, 0xa436, 0);
- rge_write_phy_ocp(sc, 0xa438, 0);
- RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001);
- rge_write_phy_ocp(sc, 0xa436, 0x8024);
- rge_write_phy_ocp(sc, 0xa438, 0);
-
- rge_patch_phy_mcu(sc, 0);
-
- /* Enable PHY config. */
- RGE_SETBIT_1(sc, 0xf2, 0x20);
-
- /* Write microcode version. */
- rge_write_phy_ocp(sc, 0xa436, 0x801e);
- rge_write_phy_ocp(sc, 0xa438, RGE_MAC_CFG2_MCODE_VER);
- }
-
- val = rge_read_phy_ocp(sc, 0xad40) & ~0x03ff;
- rge_write_phy_ocp(sc, 0xad40, val | 0x0084);
- RGE_PHY_SETBIT(sc, 0xad4e, 0x0010);
- val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff;
- rge_write_phy_ocp(sc, 0xad16, val | 0x0006);
- val = rge_read_phy_ocp(sc, 0xad32) & ~0x03ff;
- rge_write_phy_ocp(sc, 0xad32, val | 0x0006);
- RGE_PHY_CLRBIT(sc, 0xac08, 0x1100);
- val = rge_read_phy_ocp(sc, 0xac8a) & ~0xf000;
- rge_write_phy_ocp(sc, 0xac8a, val | 0x7000);
- RGE_PHY_SETBIT(sc, 0xad18, 0x0400);
- RGE_PHY_SETBIT(sc, 0xad1a, 0x03ff);
- RGE_PHY_SETBIT(sc, 0xad1c, 0x03ff);
-
- rge_write_phy_ocp(sc, 0xa436, 0x80ea);
- val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
- rge_write_phy_ocp(sc, 0xa438, val | 0xc400);
- rge_write_phy_ocp(sc, 0xa436, 0x80eb);
- val = rge_read_phy_ocp(sc, 0xa438) & ~0x0700;
- rge_write_phy_ocp(sc, 0xa438, val | 0x0300);
- rge_write_phy_ocp(sc, 0xa436, 0x80f8);
- val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
- rge_write_phy_ocp(sc, 0xa438, val | 0x1c00);
- rge_write_phy_ocp(sc, 0xa436, 0x80f1);
- val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
- rge_write_phy_ocp(sc, 0xa438, val | 0x3000);
- rge_write_phy_ocp(sc, 0xa436, 0x80fe);
- val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
- rge_write_phy_ocp(sc, 0xa438, val | 0xa500);
- rge_write_phy_ocp(sc, 0xa436, 0x8102);
- val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
- rge_write_phy_ocp(sc, 0xa438, val | 0x5000);
- rge_write_phy_ocp(sc, 0xa436, 0x8105);
- val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
- rge_write_phy_ocp(sc, 0xa438, val | 0x3300);
- rge_write_phy_ocp(sc, 0xa436, 0x8100);
- val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
- rge_write_phy_ocp(sc, 0xa438, val | 0x7000);
- rge_write_phy_ocp(sc, 0xa436, 0x8104);
- val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
- rge_write_phy_ocp(sc, 0xa438, val | 0xf000);
- rge_write_phy_ocp(sc, 0xa436, 0x8106);
- val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
- rge_write_phy_ocp(sc, 0xa438, val | 0x6500);
- rge_write_phy_ocp(sc, 0xa436, 0x80dc);
- val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
- rge_write_phy_ocp(sc, 0xa438, val | 0xed00);
- rge_write_phy_ocp(sc, 0xa436, 0x80df);
- RGE_PHY_SETBIT(sc, 0xa438, 0x0100);
- rge_write_phy_ocp(sc, 0xa436, 0x80e1);
- RGE_PHY_CLRBIT(sc, 0xa438, 0x0100);
- val = rge_read_phy_ocp(sc, 0xbf06) & ~0x003f;
- rge_write_phy_ocp(sc, 0xbf06, val | 0x0038);
- rge_write_phy_ocp(sc, 0xa436, 0x819f);
- rge_write_phy_ocp(sc, 0xa438, 0xd0b6);
- rge_write_phy_ocp(sc, 0xbc34, 0x5555);
- val = rge_read_phy_ocp(sc, 0xbf0a) & ~0x0e00;
- rge_write_phy_ocp(sc, 0xbf0a, val | 0x0a00);
- RGE_PHY_CLRBIT(sc, 0xa5c0, 0x0400);
- RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
- } else {
- for (i = 0; i < nitems(rtl8125_mac_cfg3_ephy); i++)
- rge_write_ephy(sc, rtl8125_mac_cfg3_ephy[i].reg,
- rtl8125_mac_cfg3_ephy[i].val);
-
- if (mcode_ver != RGE_MAC_CFG3_MCODE_VER) {
- /* Disable PHY config. */
- RGE_CLRBIT_1(sc, 0xf2, 0x20);
- DELAY(1000);
-
- rge_patch_phy_mcu(sc, 1);
-
- rge_write_phy_ocp(sc, 0xa436, 0x8024);
- rge_write_phy_ocp(sc, 0xa438, 0x8601);
- rge_write_phy_ocp(sc, 0xa436, 0xb82e);
- rge_write_phy_ocp(sc, 0xa438, 0x0001);
-
- RGE_PHY_SETBIT(sc, 0xb820, 0x0080);
+ } else if (sc->rge_type == MAC_CFG3) {
for (i = 0; i < nitems(rtl8125_mac_cfg3_mcu); i++) {
rge_write_phy_ocp(sc,
rtl8125_mac_cfg3_mcu[i].reg,
rtl8125_mac_cfg3_mcu[i].val);
}
+ } else if (sc->rge_type == MAC_CFG4) {
+ for (i = 0; i < nitems(rtl8125_mac_cfg4_mcu); i++) {
+ rge_write_phy_ocp(sc,
+ rtl8125_mac_cfg4_mcu[i].reg,
+ rtl8125_mac_cfg4_mcu[i].val);
+ }
+ } else if (sc->rge_type == MAC_CFG5) {
+ for (i = 0; i < nitems(rtl8125_mac_cfg5_mcu); i++) {
+ rge_write_phy_ocp(sc,
+ rtl8125_mac_cfg5_mcu[i].reg,
+ rtl8125_mac_cfg5_mcu[i].val);
+ }
+ }
+
+ if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) {
RGE_PHY_CLRBIT(sc, 0xb820, 0x0080);
rge_write_phy_ocp(sc, 0xa436, 0);
@@ -1610,91 +2056,14 @@ rge_phy_config(struct rge_softc *sc)
RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001);
rge_write_phy_ocp(sc, 0xa436, 0x8024);
rge_write_phy_ocp(sc, 0xa438, 0);
-
- rge_patch_phy_mcu(sc, 0);
-
- /* Enable PHY config. */
- RGE_SETBIT_1(sc, 0xf2, 0x20);
-
- /* Write microcode version. */
- rge_write_phy_ocp(sc, 0xa436, 0x801e);
- rge_write_phy_ocp(sc, 0xa438, RGE_MAC_CFG3_MCODE_VER);
- }
-
- RGE_PHY_SETBIT(sc, 0xad4e, 0x0010);
- val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff;
- rge_write_phy_ocp(sc, 0xad16, val | 0x03ff);
- val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f;
- rge_write_phy_ocp(sc, 0xad32, val | 0x0006);
- RGE_PHY_CLRBIT(sc, 0xac08, 0x1000);
- RGE_PHY_CLRBIT(sc, 0xac08, 0x0100);
- val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003;
- rge_write_phy_ocp(sc, 0xacc0, val | 0x0002);
- val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0;
- rge_write_phy_ocp(sc, 0xad40, val | 0x0040);
- val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007;
- rge_write_phy_ocp(sc, 0xad40, val | 0x0004);
- RGE_PHY_CLRBIT(sc, 0xac14, 0x0080);
- RGE_PHY_CLRBIT(sc, 0xac80, 0x0300);
- val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007;
- rge_write_phy_ocp(sc, 0xac5e, val | 0x0002);
- rge_write_phy_ocp(sc, 0xad4c, 0x00a8);
- rge_write_phy_ocp(sc, 0xac5c, 0x01ff);
- val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0;
- rge_write_phy_ocp(sc, 0xac8a, val | 0x0030);
- rge_write_phy_ocp(sc, 0xb87c, 0x80a2);
- rge_write_phy_ocp(sc, 0xb87e, 0x0153);
- rge_write_phy_ocp(sc, 0xb87c, 0x809c);
- rge_write_phy_ocp(sc, 0xb87e, 0x0153);
-
- rge_write_phy_ocp(sc, 0xa436, 0x81b3);
- for (i = 0; i < nitems(mac_cfg3_a438_value); i++)
- rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]);
- for (i = 0; i < 26; i++)
- rge_write_phy_ocp(sc, 0xa438, 0);
- rge_write_phy_ocp(sc, 0xa436, 0x8257);
- rge_write_phy_ocp(sc, 0xa438, 0x020f);
- rge_write_phy_ocp(sc, 0xa436, 0x80ea);
- rge_write_phy_ocp(sc, 0xa438, 0x7843);
-
- rge_patch_phy_mcu(sc, 1);
- RGE_PHY_CLRBIT(sc, 0xb896, 0x0001);
- RGE_PHY_CLRBIT(sc, 0xb892, 0xff00);
- for (i = 0; i < nitems(mac_cfg3_b88e_value); i += 2) {
- rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]);
- rge_write_phy_ocp(sc, 0xb890,
- mac_cfg3_b88e_value[i + 1]);
}
- RGE_PHY_SETBIT(sc, 0xb896, 0x0001);
+
rge_patch_phy_mcu(sc, 0);
- RGE_PHY_SETBIT(sc, 0xd068, 0x2000);
- rge_write_phy_ocp(sc, 0xa436, 0x81a2);
- RGE_PHY_SETBIT(sc, 0xa438, 0x0100);
- val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00;
- rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00);
- RGE_PHY_CLRBIT(sc, 0xa454, 0x0001);
- RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020);
- RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010);
- RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001);
- RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
+ /* Write microcode version. */
+ rge_write_phy_ocp(sc, 0xa436, 0x801e);
+ rge_write_phy_ocp(sc, 0xa438, mcode_version);
}
-
- /* Disable EEE. */
- RGE_MAC_CLRBIT(sc, 0xe040, 0x0003);
- RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006);
- RGE_PHY_CLRBIT(sc, 0xa432, 0x0010);
- RGE_PHY_CLRBIT(sc, 0xa5d0, 0x0006);
- RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001);
- RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010);
- RGE_PHY_CLRBIT(sc, 0xa428, 0x0080);
- RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200);
-
- rge_patch_phy_mcu(sc, 1);
- RGE_MAC_CLRBIT(sc, 0xe052, 0x0001);
- RGE_PHY_CLRBIT(sc, 0xa442, 0x3000);
- RGE_PHY_CLRBIT(sc, 0xa430, 0x8000);
- rge_patch_phy_mcu(sc, 0);
}
void
@@ -1739,9 +2108,15 @@ rge_hw_init(struct rge_softc *sc)
rge_write_mac_ocp(sc, 0xfc26, 0);
if (sc->rge_type == MAC_CFG3) {
- for (i = 0; i < nitems(rtl8125_def_bps); i++)
- rge_write_mac_ocp(sc, rtl8125_def_bps[i].reg,
- rtl8125_def_bps[i].val);
+ for (i = 0; i < nitems(rtl8125_mac_bps); i++) {
+ rge_write_mac_ocp(sc, rtl8125_mac_bps[i].reg,
+ rtl8125_mac_bps[i].val);
+ }
+ } else if (sc->rge_type == MAC_CFG5) {
+ for (i = 0; i < nitems(rtl8125b_mac_bps); i++) {
+ rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg,
+ rtl8125b_mac_bps[i].val);
+ }
}
/* Disable PHY power saving. */
@@ -1766,7 +2141,6 @@ rge_disable_phy_ocp_pwrsave(struct rge_s
void
rge_patch_phy_mcu(struct rge_softc *sc, int set)
{
- uint16_t val;
int i;
if (set)
@@ -1775,13 +2149,14 @@ rge_patch_phy_mcu(struct rge_softc *sc,
RGE_PHY_CLRBIT(sc, 0xb820, 0x0010);
for (i = 0; i < 1000; i++) {
- val = rge_read_phy_ocp(sc, 0xb800) & 0x0040;
- DELAY(100);
- if (val == 0x0040)
+ if ((rge_read_phy_ocp(sc, 0xb800) & 0x0040) == 0x0040)
break;
+ DELAY(100);
+ }
+ if (i == 1000) {
+ DPRINTF(("timeout waiting to patch phy mcu\n"));
+ return;
}
- if (i == 1000)
- aprint_error_dev(sc->sc_dev, "timeout waiting to patch phy mcu\n");
}
void
@@ -1818,16 +2193,22 @@ rge_config_imtype(struct rge_softc *sc,
}
void
+rge_disable_hw_im(struct rge_softc *sc)
+{
+ RGE_WRITE_2(sc, RGE_IM, 0);
+}
+
+void
rge_disable_sim_im(struct rge_softc *sc)
{
- RGE_WRITE_4(sc, RGE_TIMERINT, 0);
+ RGE_WRITE_4(sc, RGE_TIMERINT0, 0);
sc->rge_timerintr = 0;
}
void
rge_setup_sim_im(struct rge_softc *sc)
{
- RGE_WRITE_4(sc, RGE_TIMERINT, 0x2600);
+ RGE_WRITE_4(sc, RGE_TIMERINT0, 0x2600);
RGE_WRITE_4(sc, RGE_TIMERCNT, 1);
sc->rge_timerintr = 1;
}
@@ -1843,8 +2224,10 @@ rge_setup_intr(struct rge_softc *sc, int
switch (imtype) {
case RGE_IMTYPE_NONE:
rge_disable_sim_im(sc);
+ rge_disable_hw_im(sc);
break;
case RGE_IMTYPE_SIM:
+ rge_disable_hw_im(sc);
rge_setup_sim_im(sc);
break;
default:
@@ -1878,7 +2261,7 @@ rge_exit_oob(struct rge_softc *sc)
}
rge_write_mac_ocp(sc, 0xc0aa, 0x07d0);
- rge_write_mac_ocp(sc, 0xc0a6, 0x0150);
+ rge_write_mac_ocp(sc, 0xc0a6, 0x01b5);
rge_write_mac_ocp(sc, 0xc01e, 0x5555);
for (i = 0; i < 10; i++) {
@@ -1888,12 +2271,16 @@ rge_exit_oob(struct rge_softc *sc)
}
if (rge_read_mac_ocp(sc, 0xd42c) & 0x0100) {
+ printf("%s: rge_exit_oob(): rtl8125_is_ups_resume!!\n",
+ device_xname(sc->sc_dev));
for (i = 0; i < RGE_TIMEOUT; i++) {
if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 2)
break;
DELAY(1000);
}
RGE_MAC_CLRBIT(sc, 0xd408, 0x0100);
+ if (sc->rge_type == MAC_CFG4 || sc->rge_type == MAC_CFG5)
+ RGE_PHY_CLRBIT(sc, 0xa466, 0x0001);
RGE_PHY_CLRBIT(sc, 0xa468, 0x000a);
}
}
@@ -1904,7 +2291,7 @@ rge_write_csi(struct rge_softc *sc, uint
int i;
RGE_WRITE_4(sc, RGE_CSIDR, val);
- RGE_WRITE_4(sc, RGE_CSIAR, (1 << 16) | (reg & RGE_CSIAR_ADDR_MASK) |
+ RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |
(RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT) | RGE_CSIAR_BUSY);
for (i = 0; i < 10; i++) {
@@ -1921,7 +2308,7 @@ rge_read_csi(struct rge_softc *sc, uint3
{
int i;
- RGE_WRITE_4(sc, RGE_CSIAR, (1 << 16) | (reg & RGE_CSIAR_ADDR_MASK) |
+ RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |
(RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT));
for (i = 0; i < 10; i++) {
@@ -1976,6 +2363,27 @@ rge_write_ephy(struct rge_softc *sc, uin
DELAY(20);
}
+uint16_t
+rge_read_ephy(struct rge_softc *sc, uint16_t reg)
+{
+ uint32_t val;
+ int i;
+
+ val = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;
+ RGE_WRITE_4(sc, RGE_EPHYAR, val);
+
+ for (i = 0; i < 10; i++) {
+ DELAY(100);
+ val = RGE_READ_4(sc, RGE_EPHYAR);
+ if (val & RGE_EPHYAR_BUSY)
+ break;
+ }
+
+ DELAY(20);
+
+ return (val & RGE_EPHYAR_DATA_MASK);
+}
+
void
rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val)
{
@@ -1991,6 +2399,21 @@ rge_write_phy(struct rge_softc *sc, uint
rge_write_phy_ocp(sc, phyaddr, val);
}
+uint16_t
+rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg)
+{
+ uint16_t off, phyaddr;
+
+ phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8);
+ phyaddr <<= 4;
+
+ off = addr ? reg : 0x10 + (reg % 8);
+
+ phyaddr += (off - 16) << 1;
+
+ return (rge_read_phy_ocp(sc, phyaddr));
+}
+
void
rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
{
@@ -2051,7 +2474,7 @@ rge_tick(void *arg)
rge_link_state(sc);
splx(s);
- timeout_add_sec(&sc->sc_timeout, 1);
+ callout_schedule(&sc->sc_timeout, hz);
}
void
@@ -2063,8 +2486,7 @@ rge_link_state(struct rge_softc *sc)
if (rge_get_link_status(sc))
link = LINK_STATE_UP;
- if (ifp->if_link_state != link) {
- ifp->if_link_state = link;
- if_link_state_change(ifp, LINK_STATE_DOWN);
+ if (ifp->if_link_state != link) { /* XXX not safe to access */
+ if_link_state_change(ifp, link);
}
}
Index: src/sys/dev/pci/if_rgereg.h
diff -u src/sys/dev/pci/if_rgereg.h:1.4 src/sys/dev/pci/if_rgereg.h:1.5
--- src/sys/dev/pci/if_rgereg.h:1.4 Sat May 30 22:27:55 2020
+++ src/sys/dev/pci/if_rgereg.h Mon Mar 1 17:48:52 2021
@@ -1,8 +1,8 @@
-/* $NetBSD: if_rgereg.h,v 1.4 2020/05/30 22:27:55 sevan Exp $ */
-/* $OpenBSD: if_rgereg.h,v 1.1 2019/11/18 03:03:37 kevlo Exp $ */
+/* $NetBSD: if_rgereg.h,v 1.5 2021/03/01 17:48:52 jakllsch Exp $ */
+/* $OpenBSD: if_rgereg.h,v 1.6 2020/12/24 01:00:00 kevlo Exp $ */
/*
- * Copyright (c) 2019 Kevin Lo <[email protected]>
+ * Copyright (c) 2019, 2020 Kevin Lo <[email protected]>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -41,26 +41,32 @@
#define RGE_CFG4 0x0055
#define RGE_CFG5 0x0056
#define RGE_TDFNR 0x0057
-#define RGE_TIMERINT 0x0058
+#define RGE_TIMERINT0 0x0058
+#define RGE_TIMERINT1 0x005c
#define RGE_CSIDR 0x0064
#define RGE_CSIAR 0x0068
#define RGE_PHYSTAT 0x006c
#define RGE_PMCH 0x006f
#define RGE_EPHYAR 0x0080
+#define RGE_TIMERINT2 0x008c
#define RGE_TXSTART 0x0090
#define RGE_MACOCP 0x00b0
#define RGE_PHYOCP 0x00b8
+#define RGE_DLLPR 0x00d0
#define RGE_TWICMD 0x00d2
#define RGE_MCUCMD 0x00d3
#define RGE_RXMAXSIZE 0x00da
#define RGE_CPLUSCMD 0x00e0
+#define RGE_IM 0x00e2
#define RGE_RXDESC_ADDR_LO 0x00e4
#define RGE_RXDESC_ADDR_HI 0x00e8
#define RGE_PPSW 0x00f2
-#define RGE_IM(i) (0x0a00 + (i) * 4)
+#define RGE_TIMERINT3 0x00f4
+#define RGE_INTMITI(i) (0x0a00 + (i) * 4)
#define RGE_PHYBASE 0x0a40
#define RGE_ADDR0 0x19e0
#define RGE_ADDR1 0x19e4
+#define RGE_EEE_TXIDLE_TIMER 0x6048
/* Flags for register RGE_CMD */
#define RGE_CMD_RXBUF_EMPTY 0x01
@@ -83,8 +89,8 @@
#define RGE_INTRS \
(RGE_ISR_RX_OK | RGE_ISR_RX_ERR | RGE_ISR_TX_OK | \
- RGE_ISR_TX_ERR | RGE_ISR_RX_DESC_UNAVAIL | \
- RGE_ISR_RX_FIFO_OFLOW | RGE_ISR_SYSTEM_ERR)
+ RGE_ISR_TX_ERR | RGE_ISR_RX_DESC_UNAVAIL | RGE_ISR_LINKCHG | \
+ RGE_ISR_TX_DESC_UNAVAIL | RGE_ISR_PCS_TIMEOUT | RGE_ISR_SYSTEM_ERR)
#define RGE_INTRS_TIMER \
(RGE_ISR_RX_ERR | RGE_ISR_TX_ERR | RGE_ISR_PCS_TIMEOUT | \
@@ -106,16 +112,24 @@
#define RGE_EECMD_WRITECFG 0xc0
/* Flags for register RGE_CFG1 */
+#define RGE_CFG1_PM_EN 0x01
#define RGE_CFG1_SPEED_DOWN 0x10
/* Flags for register RGE_CFG2 */
+#define RGE_CFG2_PMSTS_EN 0x20
#define RGE_CFG2_CLKREQ_EN 0x80
/* Flags for register RGE_CFG3 */
#define RGE_CFG3_RDY_TO_L23 0x02
+#define RGE_CFG3_WOL_LINK 0x10
+#define RGE_CFG3_WOL_MAGIC 0x20
/* Flags for register RGE_CFG5 */
#define RGE_CFG5_PME_STS 0x01
+#define RGE_CFG5_WOL_LANWAKE 0x02
+#define RGE_CFG5_WOL_UCAST 0x10
+#define RGE_CFG5_WOL_MCAST 0x20
+#define RGE_CFG5_WOL_BCAST 0x40
/* Flags for register RGE_CSIAR */
#define RGE_CSIAR_BYTE_EN 0x0000000f
@@ -152,6 +166,10 @@
#define RGE_PHYOCP_BUSY 0x80000000
#define RGE_PHYOCP_ADDR_SHIFT 16
+/* Flags for register RGE_DLLPR. */
+#define RGE_DLLPR_PFM_EN 0x40
+#define RGE_DLLPR_TX_10M_PS_EN 0x80
+
/* Flags for register RGE_MCUCMD */
#define RGE_MCUCMD_RXFIFO_EMPTY 0x10
#define RGE_MCUCMD_TXFIFO_EMPTY 0x20
@@ -240,6 +258,7 @@ struct rge_list_data {
int rge_txq_considx;
struct rge_rxq rge_rxq[RGE_RX_LIST_CNT];
int rge_rxq_prodidx;
+ int rge_rxq_considx;
bus_dma_segment_t rge_tx_listseg;
int rge_tx_listnseg;
@@ -254,16 +273,24 @@ struct rge_list_data {
/* Microcode version */
#define RGE_MAC_CFG2_MCODE_VER 0x0b11
#define RGE_MAC_CFG3_MCODE_VER 0x0b33
+#define RGE_MAC_CFG4_MCODE_VER 0x0b17
+#define RGE_MAC_CFG5_MCODE_VER 0x0b36
enum rge_mac_type {
MAC_CFG_UNKNOWN = 1,
MAC_CFG2,
- MAC_CFG3
+ MAC_CFG3,
+ MAC_CFG4,
+ MAC_CFG5
};
#define RGE_TIMEOUT 100
+#if 0
#define RGE_JUMBO_FRAMELEN 9216
+#else
+#define RGE_JUMBO_FRAMELEN (MCLBYTES - ETHER_ALIGN)
+#endif
#define RGE_JUMBO_MTU \
(RGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - \
ETHER_VLAN_ENCAP_LEN)
@@ -283,7 +310,6 @@ struct rge_softc {
pcitag_t sc_tag;
bus_dma_segment_t sc_rx_seg;
bus_dmamap_t sc_rx_dmamap;
- uint8_t sc_enaddr[ETHER_ADDR_LEN];
struct ifmedia sc_media; /* media info */
enum rge_mac_type rge_type;
struct mbuf *rge_head;
@@ -295,6 +321,8 @@ struct rge_softc {
callout_t sc_timeout; /* tick timeout */
+ uint8_t sc_enaddr[ETHER_ADDR_LEN];
+ uint16_t rge_mcodever;
uint32_t rge_flags;
#define RGE_FLAG_MSI 0x00000001
@@ -302,7 +330,6 @@ struct rge_softc {
uint32_t rge_tx_ack;
uint32_t rge_rx_ack;
int rge_timerintr;
-
#define RGE_IMTYPE_NONE 0
#define RGE_IMTYPE_SIM 1
};
@@ -310,8 +337,6 @@ struct rge_softc {
/*
* Register space access macros.
*/
-#define RGE_WRITE_RAW_4(sc, reg, val) \
- bus_space_write_raw_region_4(sc->rge_btag, sc->rge_bhandle, reg, val, 4)
#define RGE_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->rge_btag, sc->rge_bhandle, reg, val)
#define RGE_WRITE_2(sc, reg, val) \
@@ -340,6 +365,12 @@ struct rge_softc {
#define RGE_CLRBIT_1(sc, reg, val) \
RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) & ~(val))
+#define RGE_EPHY_SETBIT(sc, reg, val) \
+ rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) | (val))
+
+#define RGE_EPHY_CLRBIT(sc, reg, val) \
+ rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) & ~(val))
+
#define RGE_PHY_SETBIT(sc, reg, val) \
rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) | (val))
@@ -352,155 +383,153 @@ struct rge_softc {
#define RGE_MAC_CLRBIT(sc, reg, val) \
rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) & ~(val))
-#define RTL8125_DEF_BPS \
- { 0xf800, 0xe008 }, \
- { 0xf802, 0xe01e }, \
- { 0xf804, 0xe02e }, \
- { 0xf806, 0xe054 }, \
- { 0xf808, 0xe057 }, \
- { 0xf80a, 0xe059 }, \
- { 0xf80c, 0xe05b }, \
- { 0xf80e, 0xe05d }, \
- { 0xf810, 0x9996 }, \
- { 0xf812, 0x49d1 }, \
- { 0xf814, 0xf005 }, \
- { 0xf816, 0x49d4 }, \
- { 0xf818, 0xf10a }, \
- { 0xf81a, 0x49d8 }, \
- { 0xf81c, 0xf108 }, \
- { 0xf81e, 0xc00f }, \
- { 0xf820, 0x7100 }, \
- { 0xf822, 0x209c }, \
- { 0xf824, 0x249c }, \
- { 0xf826, 0xc009 }, \
- { 0xf828, 0x9900 }, \
- { 0xf82a, 0xe004 }, \
- { 0xf82c, 0xc006 }, \
- { 0xf82e, 0x1900 }, \
- { 0xf830, 0x9900 }, \
- { 0xf832, 0xc602 }, \
- { 0xf834, 0xbe00 }, \
- { 0xf836, 0x5a48 }, \
- { 0xf838, 0xe0c2 }, \
- { 0xf83a, 0x0004 }, \
- { 0xf83c, 0xe10a }, \
- { 0xf83e, 0xc60f }, \
- { 0xf840, 0x73c4 }, \
- { 0xf842, 0x49b3 }, \
- { 0xf844, 0xf106 }, \
- { 0xf846, 0x73c2 }, \
- { 0xf848, 0xc608 }, \
- { 0xf84a, 0xb406 }, \
- { 0xf84c, 0xc609 }, \
- { 0xf84e, 0xff80 }, \
- { 0xf850, 0xc605 }, \
- { 0xf852, 0xb406 }, \
- { 0xf854, 0xc605 }, \
- { 0xf856, 0xff80 }, \
- { 0xf858, 0x0544 }, \
- { 0xf85a, 0x0568 }, \
- { 0xf85c, 0xe906 }, \
- { 0xf85e, 0xcde8 }, \
- { 0xf860, 0xc724 }, \
- { 0xf862, 0xc624 }, \
- { 0xf864, 0x9ee2 }, \
- { 0xf866, 0x1e01 }, \
- { 0xf868, 0x9ee0 }, \
- { 0xf86a, 0x76e0 }, \
- { 0xf86c, 0x49e0 }, \
- { 0xf86e, 0xf1fe }, \
- { 0xf870, 0x76e6 }, \
- { 0xf872, 0x486d }, \
- { 0xf874, 0x4868 }, \
- { 0xf876, 0x9ee4 }, \
- { 0xf878, 0x1e03 }, \
- { 0xf87a, 0x9ee0 }, \
- { 0xf87c, 0x76e0 }, \
- { 0xf87e, 0x49e0 }, \
- { 0xf880, 0xf1fe }, \
- { 0xf882, 0xc615 }, \
- { 0xf884, 0x9ee2 }, \
- { 0xf886, 0x1e01 }, \
- { 0xf888, 0x9ee0 }, \
- { 0xf88a, 0x76e0 }, \
- { 0xf88c, 0x49e0 }, \
- { 0xf88e, 0xf1fe }, \
- { 0xf890, 0x76e6 }, \
- { 0xf892, 0x486f }, \
- { 0xf894, 0x9ee4 }, \
- { 0xf896, 0x1e03 }, \
- { 0xf898, 0x9ee0 }, \
- { 0xf89a, 0x76e0 }, \
- { 0xf89c, 0x49e0 }, \
- { 0xf89e, 0xf1fe }, \
- { 0xf8a0, 0x7196 }, \
- { 0xf8a2, 0xc702 }, \
- { 0xf8a4, 0xbf00 }, \
- { 0xf8a6, 0x5a44 }, \
- { 0xf8a8, 0xeb0e }, \
- { 0xf8aa, 0x0070 }, \
- { 0xf8ac, 0x00c3 }, \
- { 0xf8ae, 0x1bc0 }, \
- { 0xf8b0, 0xc602 }, \
- { 0xf8b2, 0xbe00 }, \
- { 0xf8b4, 0x0e26 }, \
- { 0xf8b6, 0xc602 }, \
- { 0xf8b8, 0xbe00 }, \
- { 0xf8ba, 0x0eba }, \
- { 0xf8bc, 0xc602 }, \
- { 0xf8be, 0xbe00 }, \
- { 0xf8c0, 0x0000 }, \
- { 0xf8c2, 0xc602 }, \
- { 0xf8c4, 0xbe00 }, \
- { 0xf8c6, 0x0000 }, \
- { 0xf8c8, 0xc602 }, \
- { 0xf8ca, 0xbe00 }, \
- { 0xf8cc, 0x0000 }, \
- { 0xfc26, 0x8000 }, \
- { 0xfc2a, 0x0540 }, \
- { 0xfc2e, 0x0e24 }, \
- { 0xfc30, 0x0eb8 }, \
- { 0xfc48, 0x001a }
-
-#define RTL8125_MAC_CFG2_EPHY \
- { 0x0001, 0xa812 }, \
- { 0x0009, 0x520c }, \
- { 0x0004, 0xd000 }, \
- { 0x000d, 0xf702 }, \
- { 0x000a, 0x8653 }, \
- { 0x0006, 0x001e }, \
- { 0x0008, 0x3595 }, \
- { 0x0020, 0x9455 }, \
- { 0x0021, 0x99ff }, \
- { 0x0002, 0x6046 }, \
- { 0x0029, 0xfe00 }, \
- { 0x0023, 0xab62 }, \
- { 0x0041, 0xa80c }, \
- { 0x0049, 0x520c }, \
- { 0x0044, 0xd000 }, \
- { 0x004d, 0xf702 }, \
- { 0x004a, 0x8653 }, \
- { 0x0046, 0x001e }, \
- { 0x0048, 0x3595 }, \
- { 0x0060, 0x9455 }, \
- { 0x0061, 0x99ff }, \
- { 0x0042, 0x6046 }, \
- { 0x0069, 0xfe00 }, \
- { 0x0063, 0xab62 }
-
-#define RTL8125_MAC_CFG3_EPHY \
- { 0x0004, 0xd000 }, \
- { 0x000a, 0x8653 }, \
- { 0x0023, 0xab66 }, \
- { 0x0020, 0x9455 }, \
- { 0x0021, 0x99ff }, \
- { 0x0029, 0xfe04 }, \
- { 0x0044, 0xd000 }, \
- { 0x004a, 0x8653 }, \
- { 0x0063, 0xab66 }, \
- { 0x0060, 0x9455 }, \
- { 0x0061, 0x99ff }, \
- { 0x0069, 0xfe04 }
+static const struct {
+ uint16_t reg;
+ uint16_t val;
+} rtl8125_mac_bps[] = {
+ { 0xf800, 0xe008 }, { 0xf802, 0xe01e }, { 0xf804, 0xe02e },
+ { 0xf806, 0xe054 }, { 0xf808, 0xe057 }, { 0xf80a, 0xe059 },
+ { 0xf80c, 0xe0c2 }, { 0xf80e, 0xe0cb }, { 0xf810, 0x9996 },
+ { 0xf812, 0x49d1 }, { 0xf814, 0xf005 }, { 0xf816, 0x49d4 },
+ { 0xf818, 0xf10a }, { 0xf81a, 0x49d8 }, { 0xf81c, 0xf108 },
+ { 0xf81e, 0xc00f }, { 0xf820, 0x7100 }, { 0xf822, 0x209c },
+ { 0xf824, 0x249c }, { 0xf826, 0xc009 }, { 0xf828, 0x9900 },
+ { 0xf82a, 0xe004 }, { 0xf82c, 0xc006 }, { 0xf82e, 0x1900 },
+ { 0xf830, 0x9900 }, { 0xf832, 0xc602 }, { 0xf834, 0xbe00 },
+ { 0xf836, 0x5a48 }, { 0xf838, 0xe0c2 }, { 0xf83a, 0x0004 },
+ { 0xf83c, 0xe10a }, { 0xf83e, 0xc60f }, { 0xf840, 0x73c4 },
+ { 0xf842, 0x49b3 }, { 0xf844, 0xf106 }, { 0xf846, 0x73c2 },
+ { 0xf848, 0xc608 }, { 0xf84a, 0xb406 }, { 0xf84c, 0xc609 },
+ { 0xf84e, 0xff80 }, { 0xf850, 0xc605 }, { 0xf852, 0xb406 },
+ { 0xf854, 0xc605 }, { 0xf856, 0xff80 }, { 0xf858, 0x0544 },
+ { 0xf85a, 0x0568 }, { 0xf85c, 0xe906 }, { 0xf85e, 0xcde8 },
+ { 0xf860, 0xc724 }, { 0xf862, 0xc624 }, { 0xf864, 0x9ee2 },
+ { 0xf866, 0x1e01 }, { 0xf868, 0x9ee0 }, { 0xf86a, 0x76e0 },
+ { 0xf86c, 0x49e0 }, { 0xf86e, 0xf1fe }, { 0xf870, 0x76e6 },
+ { 0xf872, 0x486d }, { 0xf874, 0x4868 }, { 0xf876, 0x9ee4 },
+ { 0xf878, 0x1e03 }, { 0xf87a, 0x9ee0 }, { 0xf87c, 0x76e0 },
+ { 0xf87e, 0x49e0 }, { 0xf880, 0xf1fe }, { 0xf882, 0xc615 },
+ { 0xf884, 0x9ee2 }, { 0xf886, 0x1e01 }, { 0xf888, 0x9ee0 },
+ { 0xf88a, 0x76e0 }, { 0xf88c, 0x49e0 }, { 0xf88e, 0xf1fe },
+ { 0xf890, 0x76e6 }, { 0xf892, 0x486f }, { 0xf894, 0x9ee4 },
+ { 0xf896, 0x1e03 }, { 0xf898, 0x9ee0 }, { 0xf89a, 0x76e0 },
+ { 0xf89c, 0x49e0 }, { 0xf89e, 0xf1fe }, { 0xf8a0, 0x7196 },
+ { 0xf8a2, 0xc702 }, { 0xf8a4, 0xbf00 }, { 0xf8a6, 0x5a44 },
+ { 0xf8a8, 0xeb0e }, { 0xf8aa, 0x0070 }, { 0xf8ac, 0x00c3 },
+ { 0xf8ae, 0x1bc0 }, { 0xf8b0, 0xc602 }, { 0xf8b2, 0xbe00 },
+ { 0xf8b4, 0x0e26 }, { 0xf8b6, 0xc602 }, { 0xf8b8, 0xbe00 },
+ { 0xf8ba, 0x0eba }, { 0xf8bc, 0x1501 }, { 0xf8be, 0xf02a },
+ { 0xf8c0, 0x1500 }, { 0xf8c2, 0xf15d }, { 0xf8c4, 0xc661 },
+ { 0xf8c6, 0x75c8 }, { 0xf8c8, 0x49d5 }, { 0xf8ca, 0xf00a },
+ { 0xf8cc, 0x49d6 }, { 0xf8ce, 0xf008 }, { 0xf8d0, 0x49d7 },
+ { 0xf8d2, 0xf006 }, { 0xf8d4, 0x49d8 }, { 0xf8d6, 0xf004 },
+ { 0xf8d8, 0x75d2 }, { 0xf8da, 0x49d9 }, { 0xf8dc, 0xf150 },
+ { 0xf8de, 0xc553 }, { 0xf8e0, 0x77a0 }, { 0xf8e2, 0x75c8 },
+ { 0xf8e4, 0x4855 }, { 0xf8e6, 0x4856 }, { 0xf8e8, 0x4857 },
+ { 0xf8ea, 0x4858 }, { 0xf8ec, 0x48da }, { 0xf8ee, 0x48db },
+ { 0xf8f0, 0x49fe }, { 0xf8f2, 0xf002 }, { 0xf8f4, 0x485a },
+ { 0xf8f6, 0x49ff }, { 0xf8f8, 0xf002 }, { 0xf8fa, 0x485b },
+ { 0xf8fc, 0x9dc8 }, { 0xf8fe, 0x75d2 }, { 0xf900, 0x4859 },
+ { 0xf902, 0x9dd2 }, { 0xf904, 0xc643 }, { 0xf906, 0x75c0 },
+ { 0xf908, 0x49d4 }, { 0xf90a, 0xf033 }, { 0xf90c, 0x49d0 },
+ { 0xf90e, 0xf137 }, { 0xf910, 0xe030 }, { 0xf912, 0xc63a },
+ { 0xf914, 0x75c8 }, { 0xf916, 0x49d5 }, { 0xf918, 0xf00e },
+ { 0xf91a, 0x49d6 }, { 0xf91c, 0xf00c }, { 0xf91e, 0x49d7 },
+ { 0xf920, 0xf00a }, { 0xf922, 0x49d8 }, { 0xf924, 0xf008 },
+ { 0xf926, 0x75d2 }, { 0xf928, 0x49d9 }, { 0xf92a, 0xf005 },
+ { 0xf92c, 0xc62e }, { 0xf92e, 0x75c0 }, { 0xf930, 0x49d7 },
+ { 0xf932, 0xf125 }, { 0xf934, 0xc528 }, { 0xf936, 0x77a0 },
+ { 0xf938, 0xc627 }, { 0xf93a, 0x75c8 }, { 0xf93c, 0x4855 },
+ { 0xf93e, 0x4856 }, { 0xf940, 0x4857 }, { 0xf942, 0x4858 },
+ { 0xf944, 0x48da }, { 0xf946, 0x48db }, { 0xf948, 0x49fe },
+ { 0xf94a, 0xf002 }, { 0xf94c, 0x485a }, { 0xf94e, 0x49ff },
+ { 0xf950, 0xf002 }, { 0xf952, 0x485b }, { 0xf954, 0x9dc8 },
+ { 0xf956, 0x75d2 }, { 0xf958, 0x4859 }, { 0xf95a, 0x9dd2 },
+ { 0xf95c, 0xc616 }, { 0xf95e, 0x75c0 }, { 0xf960, 0x4857 },
+ { 0xf962, 0x9dc0 }, { 0xf964, 0xc613 }, { 0xf966, 0x75c0 },
+ { 0xf968, 0x49da }, { 0xf96a, 0xf003 }, { 0xf96c, 0x49d0 },
+ { 0xf96e, 0xf107 }, { 0xf970, 0xc60b }, { 0xf972, 0xc50e },
+ { 0xf974, 0x48d9 }, { 0xf976, 0x9dc0 }, { 0xf978, 0x4859 },
+ { 0xf97a, 0x9dc0 }, { 0xf97c, 0xc608 }, { 0xf97e, 0xc702 },
+ { 0xf980, 0xbf00 }, { 0xf982, 0x3ae0 }, { 0xf984, 0xe860 },
+ { 0xf986, 0xb400 }, { 0xf988, 0xb5d4 }, { 0xf98a, 0xe908 },
+ { 0xf98c, 0xe86c }, { 0xf98e, 0x1200 }, { 0xf990, 0xc409 },
+ { 0xf992, 0x6780 }, { 0xf994, 0x48f1 }, { 0xf996, 0x8f80 },
+ { 0xf998, 0xc404 }, { 0xf99a, 0xc602 }, { 0xf99c, 0xbe00 },
+ { 0xf99e, 0x10aa }, { 0xf9a0, 0xc010 }, { 0xf9a2, 0xea7c },
+ { 0xf9a4, 0xc602 }, { 0xf9a6, 0xbe00 }, { 0xf9a8, 0x0000 },
+ { 0xfc26, 0x8000 }, { 0xfc2a, 0x0540 }, { 0xfc2e, 0x0e24 },
+ { 0xfc30, 0x0eb8 }, { 0xfc32, 0x3a5c }, { 0xfc34, 0x10a8 },
+ { 0xfc48, 0x007a }
+}, rtl8125b_mac_bps[] = {
+ { 0xf800, 0xe008 }, { 0xf802, 0xe013 }, { 0xf804, 0xe01e },
+ { 0xf806, 0xe02f }, { 0xf808, 0xe035 }, { 0xf80a, 0xe04f },
+ { 0xf80c, 0xe053 }, { 0xf80e, 0xe055 }, { 0xf810, 0x740a },
+ { 0xf812, 0x4846 }, { 0xf814, 0x4847 }, { 0xf816, 0x9c0a },
+ { 0xf818, 0xc607 }, { 0xf81a, 0x74c0 }, { 0xf81c, 0x48c6 },
+ { 0xf81e, 0x9cc0 }, { 0xf820, 0xc602 }, { 0xf822, 0xbe00 },
+ { 0xf824, 0x13f0 }, { 0xf826, 0xe054 }, { 0xf828, 0x72ca },
+ { 0xf82a, 0x4826 }, { 0xf82c, 0x4827 }, { 0xf82e, 0x9aca },
+ { 0xf830, 0xc607 }, { 0xf832, 0x72c0 }, { 0xf834, 0x48a6 },
+ { 0xf836, 0x9ac0 }, { 0xf838, 0xc602 }, { 0xf83a, 0xbe00 },
+ { 0xf83c, 0x081c }, { 0xf83e, 0xe054 }, { 0xf840, 0xc60f },
+ { 0xf842, 0x74c4 }, { 0xf844, 0x49cc }, { 0xf846, 0xf109 },
+ { 0xf848, 0xc60c }, { 0xf84a, 0x74ca }, { 0xf84c, 0x48c7 },
+ { 0xf84e, 0x9cca }, { 0xf850, 0xc609 }, { 0xf852, 0x74c0 },
+ { 0xf854, 0x4846 }, { 0xf856, 0x9cc0 }, { 0xf858, 0xc602 },
+ { 0xf85a, 0xbe00 }, { 0xf85c, 0x2494 }, { 0xf85e, 0xe092 },
+ { 0xf860, 0xe0c0 }, { 0xf862, 0xe054 }, { 0xf864, 0x7420 },
+ { 0xf866, 0x48c0 }, { 0xf868, 0x9c20 }, { 0xf86a, 0x7444 },
+ { 0xf86c, 0xc602 }, { 0xf86e, 0xbe00 }, { 0xf870, 0x12dc },
+ { 0xf872, 0x733a }, { 0xf874, 0x21b5 }, { 0xf876, 0x25bc },
+ { 0xf878, 0x1304 }, { 0xf87a, 0xf111 }, { 0xf87c, 0x1b12 },
+ { 0xf87e, 0x1d2a }, { 0xf880, 0x3168 }, { 0xf882, 0x3ada },
+ { 0xf884, 0x31ab }, { 0xf886, 0x1a00 }, { 0xf888, 0x9ac0 },
+ { 0xf88a, 0x1300 }, { 0xf88c, 0xf1fb }, { 0xf88e, 0x7620 },
+ { 0xf890, 0x236e }, { 0xf892, 0x276f }, { 0xf894, 0x1a3c },
+ { 0xf896, 0x22a1 }, { 0xf898, 0x41b5 }, { 0xf89a, 0x9ee2 },
+ { 0xf89c, 0x76e4 }, { 0xf89e, 0x486f }, { 0xf8a0, 0x9ee4 },
+ { 0xf8a2, 0xc602 }, { 0xf8a4, 0xbe00 }, { 0xf8a6, 0x4a26 },
+ { 0xf8a8, 0x733a }, { 0xf8aa, 0x49bb }, { 0xf8ac, 0xc602 },
+ { 0xf8ae, 0xbe00 }, { 0xf8b0, 0x47a2 }, { 0xf8b2, 0xc602 },
+ { 0xf8b4, 0xbe00 }, { 0xf8b6, 0x0000 }, { 0xf8b8, 0xc602 },
+ { 0xf8ba, 0xbe00 }, { 0xf8bc, 0x0000 }, { 0xfc26, 0x8000 },
+ { 0xfc28, 0x13e6 }, { 0xfc2a, 0x0812 }, { 0xfc2c, 0x248c },
+ { 0xfc2e, 0x12da }, { 0xfc30, 0x4a20 }, { 0xfc32, 0x47a0 },
+ { 0xfc48, 0x003f }
+};
+
+static const struct {
+ uint16_t reg;
+ uint16_t val;
+} rtl8125_mac_cfg2_ephy[] = {
+ { 0x0001, 0xa812 }, { 0x0009, 0x520c }, { 0x0004, 0xd000 },
+ { 0x000d, 0xf702 }, { 0x000a, 0x8653 }, { 0x0006, 0x001e },
+ { 0x0008, 0x3595 }, { 0x0020, 0x9455 }, { 0x0021, 0x99ff },
+ { 0x0002, 0x6046 }, { 0x0029, 0xfe00 }, { 0x0023, 0xab62 },
+ { 0x0041, 0xa80c }, { 0x0049, 0x520c }, { 0x0044, 0xd000 },
+ { 0x004d, 0xf702 }, { 0x004a, 0x8653 }, { 0x0046, 0x001e },
+ { 0x0048, 0x3595 }, { 0x0060, 0x9455 }, { 0x0061, 0x99ff },
+ { 0x0042, 0x6046 }, { 0x0069, 0xfe00 }, { 0x0063, 0xab62 }
+}, rtl8125_mac_cfg3_ephy[] = {
+ { 0x0004, 0xd000 }, { 0x000a, 0x8653 }, { 0x0023, 0xab66 },
+ { 0x0020, 0x9455 }, { 0x0021, 0x99ff }, { 0x0029, 0xfe04 },
+ { 0x0044, 0xd000 }, { 0x004a, 0x8653 }, { 0x0063, 0xab66 },
+ { 0x0060, 0x9455 }, { 0x0061, 0x99ff }, { 0x0069, 0xfe04 }
+}, rtl8125_mac_cfg4_ephy[] = {
+ { 0x0006, 0x001f }, { 0x000a, 0xb66b }, { 0x0001, 0xa852 },
+ { 0x0024, 0x0008 }, { 0x002f, 0x6052 }, { 0x000d, 0xf716 },
+ { 0x0020, 0xd477 }, { 0x0021, 0x4477 }, { 0x0022, 0x0013 },
+ { 0x0023, 0xbb66 }, { 0x000b, 0xa909 }, { 0x0029, 0xff04 },
+ { 0x001b, 0x1ea0 }, { 0x0046, 0x001f }, { 0x004a, 0xb66b },
+ { 0x0041, 0xa84a }, { 0x0064, 0x000c }, { 0x006f, 0x604a },
+ { 0x004d, 0xf716 }, { 0x0060, 0xd477 }, { 0x0061, 0x4477 },
+ { 0x0062, 0x0013 }, { 0x0063, 0xbb66 }, { 0x004b, 0xa909 },
+ { 0x0069, 0xff04 }, { 0x005b, 0x1ea0 }
+}, rtl8125_mac_cfg5_ephy[] = {
+ { 0x000b, 0xa908 }, { 0x001e, 0x20eb }, { 0x004b, 0xa908 },
+ { 0x005e, 0x20eb }
+};
#define RTL8125_MAC_CFG2_MCU \
{ 0xa436, 0xa016 }, \
@@ -1863,3 +1892,3082 @@ struct rge_softc {
{ 0xa438, 0xffff }, \
{ 0xa436, 0xb878 }, \
{ 0xa438, 0x0001 }
+
+#define RTL8125_MAC_CFG4_MCU \
+ { 0xa436, 0x8024 }, \
+ { 0xa438, 0x3700 }, \
+ { 0xa436, 0xb82e }, \
+ { 0xa438, 0x0001 }, \
+ { 0xb820, 0x0090 }, \
+ { 0xa436, 0xa016 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa436, 0xa012 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa436, 0xa014 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8010 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8025 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x803a }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8044 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8083 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x808d }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x808d }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x808d }, \
+ { 0xa438, 0xd712 }, \
+ { 0xa438, 0x4077 }, \
+ { 0xa438, 0xd71e }, \
+ { 0xa438, 0x4159 }, \
+ { 0xa438, 0xd71e }, \
+ { 0xa438, 0x6099 }, \
+ { 0xa438, 0x7f44 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x1a14 }, \
+ { 0xa438, 0x9040 }, \
+ { 0xa438, 0x9201 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x1b1a }, \
+ { 0xa438, 0xd71e }, \
+ { 0xa438, 0x2425 }, \
+ { 0xa438, 0x1a14 }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x3ce5 }, \
+ { 0xa438, 0x1afb }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x1b00 }, \
+ { 0xa438, 0xd712 }, \
+ { 0xa438, 0x4077 }, \
+ { 0xa438, 0xd71e }, \
+ { 0xa438, 0x4159 }, \
+ { 0xa438, 0xd71e }, \
+ { 0xa438, 0x60b9 }, \
+ { 0xa438, 0x2421 }, \
+ { 0xa438, 0x1c17 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x1a14 }, \
+ { 0xa438, 0x9040 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x1c2c }, \
+ { 0xa438, 0xd71e }, \
+ { 0xa438, 0x2425 }, \
+ { 0xa438, 0x1a14 }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x3ce5 }, \
+ { 0xa438, 0x1c0f }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x1c13 }, \
+ { 0xa438, 0xd702 }, \
+ { 0xa438, 0xd501 }, \
+ { 0xa438, 0x6072 }, \
+ { 0xa438, 0x8401 }, \
+ { 0xa438, 0xf002 }, \
+ { 0xa438, 0xa401 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x146e }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x0b77 }, \
+ { 0xa438, 0xd703 }, \
+ { 0xa438, 0x665d }, \
+ { 0xa438, 0x653e }, \
+ { 0xa438, 0x641f }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x62c4 }, \
+ { 0xa438, 0x6185 }, \
+ { 0xa438, 0x6066 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x165a }, \
+ { 0xa438, 0xc101 }, \
+ { 0xa438, 0xcb00 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x1945 }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x7fa6 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x807d }, \
+ { 0xa438, 0xc102 }, \
+ { 0xa438, 0xcb00 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x1945 }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x2569 }, \
+ { 0xa438, 0x8058 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x807d }, \
+ { 0xa438, 0xc104 }, \
+ { 0xa438, 0xcb00 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x1945 }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x7fa4 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x807d }, \
+ { 0xa438, 0xc120 }, \
+ { 0xa438, 0xcb00 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x1945 }, \
+ { 0xa438, 0xd703 }, \
+ { 0xa438, 0x7fbf }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x807d }, \
+ { 0xa438, 0xc140 }, \
+ { 0xa438, 0xcb00 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x1945 }, \
+ { 0xa438, 0xd703 }, \
+ { 0xa438, 0x7fbe }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x807d }, \
+ { 0xa438, 0xc180 }, \
+ { 0xa438, 0xcb00 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x1945 }, \
+ { 0xa438, 0xd703 }, \
+ { 0xa438, 0x7fbd }, \
+ { 0xa438, 0xc100 }, \
+ { 0xa438, 0xcb00 }, \
+ { 0xa438, 0xd708 }, \
+ { 0xa438, 0x6018 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x165a }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x14f6 }, \
+ { 0xa438, 0xd014 }, \
+ { 0xa438, 0xd1e3 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x1356 }, \
+ { 0xa438, 0xd705 }, \
+ { 0xa438, 0x5fbe }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x1559 }, \
+ { 0xa436, 0xa026 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa024 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa022 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa020 }, \
+ { 0xa438, 0x1557 }, \
+ { 0xa436, 0xa006 }, \
+ { 0xa438, 0x1677 }, \
+ { 0xa436, 0xa004 }, \
+ { 0xa438, 0x0b75 }, \
+ { 0xa436, 0xa002 }, \
+ { 0xa438, 0x1c17 }, \
+ { 0xa436, 0xa000 }, \
+ { 0xa438, 0x1b04 }, \
+ { 0xa436, 0xa008 }, \
+ { 0xa438, 0x1f00 }, \
+ { 0xa436, 0xa016 }, \
+ { 0xa438, 0x0020 }, \
+ { 0xa436, 0xa012 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa436, 0xa014 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8010 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x817f }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x82ab }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x83f8 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8444 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8454 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8459 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8465 }, \
+ { 0xa438, 0xcb11 }, \
+ { 0xa438, 0xa50c }, \
+ { 0xa438, 0x8310 }, \
+ { 0xa438, 0xd701 }, \
+ { 0xa438, 0x4076 }, \
+ { 0xa438, 0x0c03 }, \
+ { 0xa438, 0x0903 }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x6083 }, \
+ { 0xa438, 0x0c1f }, \
+ { 0xa438, 0x0d00 }, \
+ { 0xa438, 0xf003 }, \
+ { 0xa438, 0x0c1f }, \
+ { 0xa438, 0x0d00 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a7d }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a4d }, \
+ { 0xa438, 0xcb12 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x5f84 }, \
+ { 0xa438, 0xd102 }, \
+ { 0xa438, 0xd040 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5fb4 }, \
+ { 0xa438, 0xd701 }, \
+ { 0xa438, 0x60f3 }, \
+ { 0xa438, 0xd413 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a37 }, \
+ { 0xa438, 0xd410 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a37 }, \
+ { 0xa438, 0xcb13 }, \
+ { 0xa438, 0xa108 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a42 }, \
+ { 0xa438, 0x8108 }, \
+ { 0xa438, 0xa00a }, \
+ { 0xa438, 0xa910 }, \
+ { 0xa438, 0xa780 }, \
+ { 0xa438, 0xd14a }, \
+ { 0xa438, 0xd048 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd701 }, \
+ { 0xa438, 0x6255 }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5f74 }, \
+ { 0xa438, 0x6326 }, \
+ { 0xa438, 0xd702 }, \
+ { 0xa438, 0x5f07 }, \
+ { 0xa438, 0x800a }, \
+ { 0xa438, 0xa004 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a42 }, \
+ { 0xa438, 0x8004 }, \
+ { 0xa438, 0xa001 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a42 }, \
+ { 0xa438, 0x8001 }, \
+ { 0xa438, 0x0c03 }, \
+ { 0xa438, 0x0902 }, \
+ { 0xa438, 0xffe2 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x5fab }, \
+ { 0xa438, 0xba08 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x7f8b }, \
+ { 0xa438, 0x9a08 }, \
+ { 0xa438, 0x800a }, \
+ { 0xa438, 0xd702 }, \
+ { 0xa438, 0x6535 }, \
+ { 0xa438, 0xd40d }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a37 }, \
+ { 0xa438, 0xcb14 }, \
+ { 0xa438, 0xa004 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a42 }, \
+ { 0xa438, 0x8004 }, \
+ { 0xa438, 0xa001 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a42 }, \
+ { 0xa438, 0x8001 }, \
+ { 0xa438, 0xa00a }, \
+ { 0xa438, 0xa780 }, \
+ { 0xa438, 0xd14a }, \
+ { 0xa438, 0xd048 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5fb4 }, \
+ { 0xa438, 0x6206 }, \
+ { 0xa438, 0xd702 }, \
+ { 0xa438, 0x5f47 }, \
+ { 0xa438, 0x800a }, \
+ { 0xa438, 0xa004 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a42 }, \
+ { 0xa438, 0x8004 }, \
+ { 0xa438, 0xa001 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a42 }, \
+ { 0xa438, 0x8001 }, \
+ { 0xa438, 0x0c03 }, \
+ { 0xa438, 0x0902 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8064 }, \
+ { 0xa438, 0x800a }, \
+ { 0xa438, 0xd40e }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a37 }, \
+ { 0xa438, 0xb920 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x5fac }, \
+ { 0xa438, 0x9920 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x7f8c }, \
+ { 0xa438, 0xd701 }, \
+ { 0xa438, 0x6073 }, \
+ { 0xa438, 0xd701 }, \
+ { 0xa438, 0x4216 }, \
+ { 0xa438, 0xa004 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a42 }, \
+ { 0xa438, 0x8004 }, \
+ { 0xa438, 0xa001 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a42 }, \
+ { 0xa438, 0x8001 }, \
+ { 0xa438, 0xd120 }, \
+ { 0xa438, 0xd040 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5fb4 }, \
+ { 0xa438, 0x8504 }, \
+ { 0xa438, 0xcb21 }, \
+ { 0xa438, 0xa301 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5f9f }, \
+ { 0xa438, 0x8301 }, \
+ { 0xa438, 0xd704 }, \
+ { 0xa438, 0x40e0 }, \
+ { 0xa438, 0xd196 }, \
+ { 0xa438, 0xd04d }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5fb4 }, \
+ { 0xa438, 0xcb22 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a6d }, \
+ { 0xa438, 0x0c03 }, \
+ { 0xa438, 0x1502 }, \
+ { 0xa438, 0xa640 }, \
+ { 0xa438, 0x9503 }, \
+ { 0xa438, 0x8910 }, \
+ { 0xa438, 0x8720 }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x6083 }, \
+ { 0xa438, 0x0c1f }, \
+ { 0xa438, 0x0d01 }, \
+ { 0xa438, 0xf003 }, \
+ { 0xa438, 0x0c1f }, \
+ { 0xa438, 0x0d01 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a7d }, \
+ { 0xa438, 0x0c1f }, \
+ { 0xa438, 0x0f14 }, \
+ { 0xa438, 0xcb23 }, \
+ { 0xa438, 0x8fc0 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a25 }, \
+ { 0xa438, 0xaf40 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a25 }, \
+ { 0xa438, 0x0cc0 }, \
+ { 0xa438, 0x0f80 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a25 }, \
+ { 0xa438, 0xafc0 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a25 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd701 }, \
+ { 0xa438, 0x5dee }, \
+ { 0xa438, 0xcb24 }, \
+ { 0xa438, 0x8f1f }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd701 }, \
+ { 0xa438, 0x7f6e }, \
+ { 0xa438, 0xa111 }, \
+ { 0xa438, 0xa215 }, \
+ { 0xa438, 0xa401 }, \
+ { 0xa438, 0x8404 }, \
+ { 0xa438, 0xa720 }, \
+ { 0xa438, 0xcb25 }, \
+ { 0xa438, 0x0c03 }, \
+ { 0xa438, 0x1502 }, \
+ { 0xa438, 0x8640 }, \
+ { 0xa438, 0x9503 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0b43 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0b86 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xb920 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x5fac }, \
+ { 0xa438, 0x9920 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x7f8c }, \
+ { 0xa438, 0xcb26 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x5f82 }, \
+ { 0xa438, 0x8111 }, \
+ { 0xa438, 0x8205 }, \
+ { 0xa438, 0x8404 }, \
+ { 0xa438, 0xcb27 }, \
+ { 0xa438, 0xd404 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a37 }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x6083 }, \
+ { 0xa438, 0x0c1f }, \
+ { 0xa438, 0x0d02 }, \
+ { 0xa438, 0xf003 }, \
+ { 0xa438, 0x0c1f }, \
+ { 0xa438, 0x0d02 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a7d }, \
+ { 0xa438, 0xa710 }, \
+ { 0xa438, 0xa104 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a42 }, \
+ { 0xa438, 0x8104 }, \
+ { 0xa438, 0xa001 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a42 }, \
+ { 0xa438, 0x8001 }, \
+ { 0xa438, 0xa120 }, \
+ { 0xa438, 0xaa0f }, \
+ { 0xa438, 0x8110 }, \
+ { 0xa438, 0xa284 }, \
+ { 0xa438, 0xa404 }, \
+ { 0xa438, 0xa00a }, \
+ { 0xa438, 0xd193 }, \
+ { 0xa438, 0xd046 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5fb4 }, \
+ { 0xa438, 0xcb28 }, \
+ { 0xa438, 0xa110 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5fa8 }, \
+ { 0xa438, 0x8110 }, \
+ { 0xa438, 0x8284 }, \
+ { 0xa438, 0xa404 }, \
+ { 0xa438, 0x800a }, \
+ { 0xa438, 0x8710 }, \
+ { 0xa438, 0xb804 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x7f82 }, \
+ { 0xa438, 0x9804 }, \
+ { 0xa438, 0xcb29 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x5f85 }, \
+ { 0xa438, 0xa710 }, \
+ { 0xa438, 0xb820 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x7f65 }, \
+ { 0xa438, 0x9820 }, \
+ { 0xa438, 0xcb2a }, \
+ { 0xa438, 0xa190 }, \
+ { 0xa438, 0xa284 }, \
+ { 0xa438, 0xa404 }, \
+ { 0xa438, 0xa00a }, \
+ { 0xa438, 0xd13d }, \
+ { 0xa438, 0xd04a }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x3444 }, \
+ { 0xa438, 0x8149 }, \
+ { 0xa438, 0xa220 }, \
+ { 0xa438, 0xd1a0 }, \
+ { 0xa438, 0xd040 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x3444 }, \
+ { 0xa438, 0x8151 }, \
+ { 0xa438, 0xd702 }, \
+ { 0xa438, 0x5f51 }, \
+ { 0xa438, 0xcb2f }, \
+ { 0xa438, 0xa302 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd708 }, \
+ { 0xa438, 0x5f63 }, \
+ { 0xa438, 0xd411 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a37 }, \
+ { 0xa438, 0x8302 }, \
+ { 0xa438, 0xd409 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a37 }, \
+ { 0xa438, 0xb920 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x5fac }, \
+ { 0xa438, 0x9920 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x7f8c }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x5fa3 }, \
+ { 0xa438, 0x8190 }, \
+ { 0xa438, 0x82a4 }, \
+ { 0xa438, 0x8404 }, \
+ { 0xa438, 0x800a }, \
+ { 0xa438, 0xb808 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd71f }, \
+ { 0xa438, 0x7fa3 }, \
+ { 0xa438, 0x9808 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x0433 }, \
+ { 0xa438, 0xcb15 }, \
+ { 0xa438, 0xa508 }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x6083 }, \
+ { 0xa438, 0x0c1f }, \
+ { 0xa438, 0x0d01 }, \
+ { 0xa438, 0xf003 }, \
+ { 0xa438, 0x0c1f }, \
+ { 0xa438, 0x0d01 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a7d }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a4d }, \
+ { 0xa438, 0xa301 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5f9f }, \
+ { 0xa438, 0x8301 }, \
+ { 0xa438, 0xd704 }, \
+ { 0xa438, 0x40e0 }, \
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+ { 0xa438, 0xcc55 }, \
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+ { 0xa438, 0xd702 }, \
+ { 0xa438, 0x5f71 }, \
+ { 0xa438, 0xcb38 }, \
+ { 0xa438, 0x8224 }, \
+ { 0xa438, 0xa288 }, \
+ { 0xa438, 0x8180 }, \
+ { 0xa438, 0xa110 }, \
+ { 0xa438, 0xa404 }, \
+ { 0xa438, 0x800a }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x6041 }, \
+ { 0xa438, 0x8402 }, \
+ { 0xa438, 0xd415 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a37 }, \
+ { 0xa438, 0xd13d }, \
+ { 0xa438, 0xd04a }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5fb4 }, \
+ { 0xa438, 0xcb39 }, \
+ { 0xa438, 0xa00a }, \
+ { 0xa438, 0xa190 }, \
+ { 0xa438, 0xa2a0 }, \
+ { 0xa438, 0xa404 }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x6041 }, \
+ { 0xa438, 0xa402 }, \
+ { 0xa438, 0xd17a }, \
+ { 0xa438, 0xd047 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5fb4 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x0560 }, \
+ { 0xa438, 0xa111 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0xd3f5 }, \
+ { 0xa438, 0xd219 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0c31 }, \
+ { 0xa438, 0xd708 }, \
+ { 0xa438, 0x5fa5 }, \
+ { 0xa438, 0xa215 }, \
+ { 0xa438, 0xd30e }, \
+ { 0xa438, 0xd21a }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0c31 }, \
+ { 0xa438, 0xd708 }, \
+ { 0xa438, 0x63e9 }, \
+ { 0xa438, 0xd708 }, \
+ { 0xa438, 0x5f65 }, \
+ { 0xa438, 0xd708 }, \
+ { 0xa438, 0x7f36 }, \
+ { 0xa438, 0xa004 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0c35 }, \
+ { 0xa438, 0x8004 }, \
+ { 0xa438, 0xa001 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0c35 }, \
+ { 0xa438, 0x8001 }, \
+ { 0xa438, 0xd708 }, \
+ { 0xa438, 0x4098 }, \
+ { 0xa438, 0xd102 }, \
+ { 0xa438, 0x9401 }, \
+ { 0xa438, 0xf003 }, \
+ { 0xa438, 0xd103 }, \
+ { 0xa438, 0xb401 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0c27 }, \
+ { 0xa438, 0xa108 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0c35 }, \
+ { 0xa438, 0x8108 }, \
+ { 0xa438, 0x8110 }, \
+ { 0xa438, 0x8294 }, \
+ { 0xa438, 0xa202 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x0bdb }, \
+ { 0xa438, 0xd39c }, \
+ { 0xa438, 0xd210 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0c31 }, \
+ { 0xa438, 0xd708 }, \
+ { 0xa438, 0x5fa5 }, \
+ { 0xa438, 0xd39c }, \
+ { 0xa438, 0xd210 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0c31 }, \
+ { 0xa438, 0xd708 }, \
+ { 0xa438, 0x5fa5 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0c31 }, \
+ { 0xa438, 0xd708 }, \
+ { 0xa438, 0x29b5 }, \
+ { 0xa438, 0x840e }, \
+ { 0xa438, 0xd708 }, \
+ { 0xa438, 0x5f4a }, \
+ { 0xa438, 0x0c1f }, \
+ { 0xa438, 0x1014 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0c31 }, \
+ { 0xa438, 0xd709 }, \
+ { 0xa438, 0x7fa4 }, \
+ { 0xa438, 0x901f }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x0c23 }, \
+ { 0xa438, 0xcb43 }, \
+ { 0xa438, 0xa508 }, \
+ { 0xa438, 0xd701 }, \
+ { 0xa438, 0x3699 }, \
+ { 0xa438, 0x844a }, \
+ { 0xa438, 0xa504 }, \
+ { 0xa438, 0xa190 }, \
+ { 0xa438, 0xa2a0 }, \
+ { 0xa438, 0xa404 }, \
+ { 0xa438, 0xa00a }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x2109 }, \
+ { 0xa438, 0x05ea }, \
+ { 0xa438, 0xa402 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x05ea }, \
+ { 0xa438, 0xcb90 }, \
+ { 0xa438, 0x0cf0 }, \
+ { 0xa438, 0x0ca0 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x06db }, \
+ { 0xa438, 0xd1ff }, \
+ { 0xa438, 0xd052 }, \
+ { 0xa438, 0xa508 }, \
+ { 0xa438, 0x8718 }, \
+ { 0xa438, 0xa00a }, \
+ { 0xa438, 0xa190 }, \
+ { 0xa438, 0xa2a0 }, \
+ { 0xa438, 0xa404 }, \
+ { 0xa438, 0x0cf0 }, \
+ { 0xa438, 0x0c50 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x09ef }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a5e }, \
+ { 0xa438, 0xd704 }, \
+ { 0xa438, 0x2e70 }, \
+ { 0xa438, 0x06da }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5f55 }, \
+ { 0xa438, 0xa90c }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x0645 }, \
+ { 0xa436, 0xa10e }, \
+ { 0xa438, 0x0644 }, \
+ { 0xa436, 0xa10c }, \
+ { 0xa438, 0x09e9 }, \
+ { 0xa436, 0xa10a }, \
+ { 0xa438, 0x06da }, \
+ { 0xa436, 0xa108 }, \
+ { 0xa438, 0x05e1 }, \
+ { 0xa436, 0xa106 }, \
+ { 0xa438, 0x0be4 }, \
+ { 0xa436, 0xa104 }, \
+ { 0xa438, 0x0435 }, \
+ { 0xa436, 0xa102 }, \
+ { 0xa438, 0x0141 }, \
+ { 0xa436, 0xa100 }, \
+ { 0xa438, 0x026d }, \
+ { 0xa436, 0xa110 }, \
+ { 0xa438, 0x00ff }, \
+ { 0xa436, 0xb87c }, \
+ { 0xa438, 0x85fe }, \
+ { 0xa436, 0xb87e }, \
+ { 0xa438, 0xaf86 }, \
+ { 0xa438, 0x16af }, \
+ { 0xa438, 0x8699 }, \
+ { 0xa438, 0xaf86 }, \
+ { 0xa438, 0xe5af }, \
+ { 0xa438, 0x86f9 }, \
+ { 0xa438, 0xaf87 }, \
+ { 0xa438, 0x7aaf }, \
+ { 0xa438, 0x883a }, \
+ { 0xa438, 0xaf88 }, \
+ { 0xa438, 0x58af }, \
+ { 0xa438, 0x8b6c }, \
+ { 0xa438, 0xd48b }, \
+ { 0xa438, 0x7c02 }, \
+ { 0xa438, 0x8644 }, \
+ { 0xa438, 0x2c00 }, \
+ { 0xa438, 0x503c }, \
+ { 0xa438, 0xffd6 }, \
+ { 0xa438, 0xac27 }, \
+ { 0xa438, 0x18e1 }, \
+ { 0xa438, 0x82fe }, \
+ { 0xa438, 0xad28 }, \
+ { 0xa438, 0x0cd4 }, \
+ { 0xa438, 0x8b84 }, \
+ { 0xa438, 0x0286 }, \
+ { 0xa438, 0x442c }, \
+ { 0xa438, 0x003c }, \
+ { 0xa438, 0xac27 }, \
+ { 0xa438, 0x06ee }, \
+ { 0xa438, 0x8299 }, \
+ { 0xa438, 0x01ae }, \
+ { 0xa438, 0x04ee }, \
+ { 0xa438, 0x8299 }, \
+ { 0xa438, 0x00af }, \
+ { 0xa438, 0x23dc }, \
+ { 0xa438, 0xf9fa }, \
+ { 0xa438, 0xcefa }, \
+ { 0xa438, 0xfbef }, \
+ { 0xa438, 0x79fb }, \
+ { 0xa438, 0xc4bf }, \
+ { 0xa438, 0x8b76 }, \
+ { 0xa438, 0x026c }, \
+ { 0xa438, 0x6dac }, \
+ { 0xa438, 0x2804 }, \
+ { 0xa438, 0xd203 }, \
+ { 0xa438, 0xae02 }, \
+ { 0xa438, 0xd201 }, \
+ { 0xa438, 0xbdd8 }, \
+ { 0xa438, 0x19d9 }, \
+ { 0xa438, 0xef94 }, \
+ { 0xa438, 0x026c }, \
+ { 0xa438, 0x6d78 }, \
+ { 0xa438, 0x03ef }, \
+ { 0xa438, 0x648a }, \
+ { 0xa438, 0x0002 }, \
+ { 0xa438, 0xbdd8 }, \
+ { 0xa438, 0x19d9 }, \
+ { 0xa438, 0xef94 }, \
+ { 0xa438, 0x026c }, \
+ { 0xa438, 0x6d78 }, \
+ { 0xa438, 0x03ef }, \
+ { 0xa438, 0x7402 }, \
+ { 0xa438, 0x72cd }, \
+ { 0xa438, 0xac50 }, \
+ { 0xa438, 0x02ef }, \
+ { 0xa438, 0x643a }, \
+ { 0xa438, 0x019f }, \
+ { 0xa438, 0xe4ef }, \
+ { 0xa438, 0x4678 }, \
+ { 0xa438, 0x03ac }, \
+ { 0xa438, 0x2002 }, \
+ { 0xa438, 0xae02 }, \
+ { 0xa438, 0xd0ff }, \
+ { 0xa438, 0xffef }, \
+ { 0xa438, 0x97ff }, \
+ { 0xa438, 0xfec6 }, \
+ { 0xa438, 0xfefd }, \
+ { 0xa438, 0x041f }, \
+ { 0xa438, 0x771f }, \
+ { 0xa438, 0x221c }, \
+ { 0xa438, 0x450d }, \
+ { 0xa438, 0x481f }, \
+ { 0xa438, 0x00ac }, \
+ { 0xa438, 0x7f04 }, \
+ { 0xa438, 0x1a94 }, \
+ { 0xa438, 0xae08 }, \
+ { 0xa438, 0x1a94 }, \
+ { 0xa438, 0xac7f }, \
+ { 0xa438, 0x03d7 }, \
+ { 0xa438, 0x0100 }, \
+ { 0xa438, 0xef46 }, \
+ { 0xa438, 0x0d48 }, \
+ { 0xa438, 0x1f00 }, \
+ { 0xa438, 0x1c45 }, \
+ { 0xa438, 0xef69 }, \
+ { 0xa438, 0xef57 }, \
+ { 0xa438, 0xef74 }, \
+ { 0xa438, 0x0272 }, \
+ { 0xa438, 0xe8a7 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa438, 0x0d1a }, \
+ { 0xa438, 0x941b }, \
+ { 0xa438, 0x979e }, \
+ { 0xa438, 0x072d }, \
+ { 0xa438, 0x0100 }, \
+ { 0xa438, 0x1a64 }, \
+ { 0xa438, 0xef76 }, \
+ { 0xa438, 0xef97 }, \
+ { 0xa438, 0x0d98 }, \
+ { 0xa438, 0xd400 }, \
+ { 0xa438, 0xff1d }, \
+ { 0xa438, 0x941a }, \
+ { 0xa438, 0x89cf }, \
+ { 0xa438, 0x1a75 }, \
+ { 0xa438, 0xaf74 }, \
+ { 0xa438, 0xf9bf }, \
+ { 0xa438, 0x8b79 }, \
+ { 0xa438, 0x026c }, \
+ { 0xa438, 0x6da1 }, \
+ { 0xa438, 0x0005 }, \
+ { 0xa438, 0xe180 }, \
+ { 0xa438, 0xa0ae }, \
+ { 0xa438, 0x03e1 }, \
+ { 0xa438, 0x80a1 }, \
+ { 0xa438, 0xaf26 }, \
+ { 0xa438, 0x9aac }, \
+ { 0xa438, 0x284d }, \
+ { 0xa438, 0xe08f }, \
+ { 0xa438, 0xffef }, \
+ { 0xa438, 0x10c0 }, \
+ { 0xa438, 0xe08f }, \
+ { 0xa438, 0xfe10 }, \
+ { 0xa438, 0x1b08 }, \
+ { 0xa438, 0xa000 }, \
+ { 0xa438, 0x04c8 }, \
+ { 0xa438, 0xaf40 }, \
+ { 0xa438, 0x67c8 }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x8c02 }, \
+ { 0xa438, 0x6c4e }, \
+ { 0xa438, 0xc4bf }, \
+ { 0xa438, 0x8b8f }, \
+ { 0xa438, 0x026c }, \
+ { 0xa438, 0x6def }, \
+ { 0xa438, 0x74e0 }, \
+ { 0xa438, 0x830c }, \
+ { 0xa438, 0xad20 }, \
+ { 0xa438, 0x0302 }, \
+ { 0xa438, 0x74ac }, \
+ { 0xa438, 0xccef }, \
+ { 0xa438, 0x971b }, \
+ { 0xa438, 0x76ad }, \
+ { 0xa438, 0x5f02 }, \
+ { 0xa438, 0xae13 }, \
+ { 0xa438, 0xef69 }, \
+ { 0xa438, 0xef30 }, \
+ { 0xa438, 0x1b32 }, \
+ { 0xa438, 0xc4ef }, \
+ { 0xa438, 0x46e4 }, \
+ { 0xa438, 0x8ffb }, \
+ { 0xa438, 0xe58f }, \
+ { 0xa438, 0xfce7 }, \
+ { 0xa438, 0x8ffd }, \
+ { 0xa438, 0xcc10 }, \
+ { 0xa438, 0x11ae }, \
+ { 0xa438, 0xb8d1 }, \
+ { 0xa438, 0x00a1 }, \
+ { 0xa438, 0x1f03 }, \
+ { 0xa438, 0xaf40 }, \
+ { 0xa438, 0x4fbf }, \
+ { 0xa438, 0x8b8c }, \
+ { 0xa438, 0x026c }, \
+ { 0xa438, 0x4ec4 }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x8f02 }, \
+ { 0xa438, 0x6c6d }, \
+ { 0xa438, 0xef74 }, \
+ { 0xa438, 0xe083 }, \
+ { 0xa438, 0x0cad }, \
+ { 0xa438, 0x2003 }, \
+ { 0xa438, 0x0274 }, \
+ { 0xa438, 0xaccc }, \
+ { 0xa438, 0xef97 }, \
+ { 0xa438, 0x1b76 }, \
+ { 0xa438, 0xad5f }, \
+ { 0xa438, 0x02ae }, \
+ { 0xa438, 0x04ef }, \
+ { 0xa438, 0x69ef }, \
+ { 0xa438, 0x3111 }, \
+ { 0xa438, 0xaed1 }, \
+ { 0xa438, 0x0287 }, \
+ { 0xa438, 0x80af }, \
+ { 0xa438, 0x2293 }, \
+ { 0xa438, 0xf8f9 }, \
+ { 0xa438, 0xfafb }, \
+ { 0xa438, 0xef59 }, \
+ { 0xa438, 0xe080 }, \
+ { 0xa438, 0x13ad }, \
+ { 0xa438, 0x252f }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x2802 }, \
+ { 0xa438, 0x6c6d }, \
+ { 0xa438, 0xef64 }, \
+ { 0xa438, 0x1f44 }, \
+ { 0xa438, 0xe18f }, \
+ { 0xa438, 0xb91b }, \
+ { 0xa438, 0x64ad }, \
+ { 0xa438, 0x4f1d }, \
+ { 0xa438, 0xd688 }, \
+ { 0xa438, 0x2bd7 }, \
+ { 0xa438, 0x882e }, \
+ { 0xa438, 0x0274 }, \
+ { 0xa438, 0x73ad }, \
+ { 0xa438, 0x5008 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x3102 }, \
+ { 0xa438, 0x737c }, \
+ { 0xa438, 0xae03 }, \
+ { 0xa438, 0x0287 }, \
+ { 0xa438, 0xd0bf }, \
+ { 0xa438, 0x882b }, \
+ { 0xa438, 0x0273 }, \
+ { 0xa438, 0x73e0 }, \
+ { 0xa438, 0x824c }, \
+ { 0xa438, 0xf621 }, \
+ { 0xa438, 0xe482 }, \
+ { 0xa438, 0x4cbf }, \
+ { 0xa438, 0x8834 }, \
+ { 0xa438, 0x0273 }, \
+ { 0xa438, 0x7cef }, \
+ { 0xa438, 0x95ff }, \
+ { 0xa438, 0xfefd }, \
+ { 0xa438, 0xfc04 }, \
+ { 0xa438, 0xf8f9 }, \
+ { 0xa438, 0xfafb }, \
+ { 0xa438, 0xef79 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x1f02 }, \
+ { 0xa438, 0x737c }, \
+ { 0xa438, 0x1f22 }, \
+ { 0xa438, 0xac32 }, \
+ { 0xa438, 0x31ef }, \
+ { 0xa438, 0x12bf }, \
+ { 0xa438, 0x8822 }, \
+ { 0xa438, 0x026c }, \
+ { 0xa438, 0x4ed6 }, \
+ { 0xa438, 0x8fba }, \
+ { 0xa438, 0x1f33 }, \
+ { 0xa438, 0xac3c }, \
+ { 0xa438, 0x1eef }, \
+ { 0xa438, 0x13bf }, \
+ { 0xa438, 0x8837 }, \
+ { 0xa438, 0x026c }, \
+ { 0xa438, 0x4eef }, \
+ { 0xa438, 0x96d8 }, \
+ { 0xa438, 0x19d9 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x2502 }, \
+ { 0xa438, 0x6c4e }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x2502 }, \
+ { 0xa438, 0x6c4e }, \
+ { 0xa438, 0x1616 }, \
+ { 0xa438, 0x13ae }, \
+ { 0xa438, 0xdf12 }, \
+ { 0xa438, 0xaecc }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x1f02 }, \
+ { 0xa438, 0x7373 }, \
+ { 0xa438, 0xef97 }, \
+ { 0xa438, 0xfffe }, \
+ { 0xa438, 0xfdfc }, \
+ { 0xa438, 0x0466 }, \
+ { 0xa438, 0xac88 }, \
+ { 0xa438, 0x54ac }, \
+ { 0xa438, 0x88f0 }, \
+ { 0xa438, 0xac8a }, \
+ { 0xa438, 0x92ac }, \
+ { 0xa438, 0xbadd }, \
+ { 0xa438, 0xac6c }, \
+ { 0xa438, 0xeeac }, \
+ { 0xa438, 0x6cff }, \
+ { 0xa438, 0xad02 }, \
+ { 0xa438, 0x99ac }, \
+ { 0xa438, 0x0030 }, \
+ { 0xa438, 0xac88 }, \
+ { 0xa438, 0xd4c3 }, \
+ { 0xa438, 0x5000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x00b4 }, \
+ { 0xa438, 0xecee }, \
+ { 0xa438, 0x8298 }, \
+ { 0xa438, 0x00af }, \
+ { 0xa438, 0x1412 }, \
+ { 0xa438, 0xf8bf }, \
+ { 0xa438, 0x8b5d }, \
+ { 0xa438, 0x026c }, \
+ { 0xa438, 0x6d58 }, \
+ { 0xa438, 0x03e1 }, \
+ { 0xa438, 0x8fb8 }, \
+ { 0xa438, 0x2901 }, \
+ { 0xa438, 0xe58f }, \
+ { 0xa438, 0xb8a0 }, \
+ { 0xa438, 0x0049 }, \
+ { 0xa438, 0xef47 }, \
+ { 0xa438, 0xe483 }, \
+ { 0xa438, 0x02e5 }, \
+ { 0xa438, 0x8303 }, \
+ { 0xa438, 0xbfc2 }, \
+ { 0xa438, 0x5f1a }, \
+ { 0xa438, 0x95f7 }, \
+ { 0xa438, 0x05ee }, \
+ { 0xa438, 0xffd2 }, \
+ { 0xa438, 0x00d8 }, \
+ { 0xa438, 0xf605 }, \
+ { 0xa438, 0x1f11 }, \
+ { 0xa438, 0xef60 }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x3002 }, \
+ { 0xa438, 0x6c4e }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x3302 }, \
+ { 0xa438, 0x6c6d }, \
+ { 0xa438, 0xf728 }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x3302 }, \
+ { 0xa438, 0x6c4e }, \
+ { 0xa438, 0xf628 }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x3302 }, \
+ { 0xa438, 0x6c4e }, \
+ { 0xa438, 0x0c64 }, \
+ { 0xa438, 0xef46 }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x6002 }, \
+ { 0xa438, 0x6c4e }, \
+ { 0xa438, 0x0289 }, \
+ { 0xa438, 0x9902 }, \
+ { 0xa438, 0x3920 }, \
+ { 0xa438, 0xaf89 }, \
+ { 0xa438, 0x96a0 }, \
+ { 0xa438, 0x0149 }, \
+ { 0xa438, 0xef47 }, \
+ { 0xa438, 0xe483 }, \
+ { 0xa438, 0x04e5 }, \
+ { 0xa438, 0x8305 }, \
+ { 0xa438, 0xbfc2 }, \
+ { 0xa438, 0x5f1a }, \
+ { 0xa438, 0x95f7 }, \
+ { 0xa438, 0x05ee }, \
+ { 0xa438, 0xffd2 }, \
+ { 0xa438, 0x00d8 }, \
+ { 0xa438, 0xf605 }, \
+ { 0xa438, 0x1f11 }, \
+ { 0xa438, 0xef60 }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x3002 }, \
+ { 0xa438, 0x6c4e }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x3302 }, \
+ { 0xa438, 0x6c6d }, \
+ { 0xa438, 0xf729 }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x3302 }, \
+ { 0xa438, 0x6c4e }, \
+ { 0xa438, 0xf629 }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x3302 }, \
+ { 0xa438, 0x6c4e }, \
+ { 0xa438, 0x0c64 }, \
+ { 0xa438, 0xef46 }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x6302 }, \
+ { 0xa438, 0x6c4e }, \
+ { 0xa438, 0x0289 }, \
+ { 0xa438, 0x9902 }, \
+ { 0xa438, 0x3920 }, \
+ { 0xa438, 0xaf89 }, \
+ { 0xa438, 0x96a0 }, \
+ { 0xa438, 0x0249 }, \
+ { 0xa438, 0xef47 }, \
+ { 0xa438, 0xe483 }, \
+ { 0xa438, 0x06e5 }, \
+ { 0xa438, 0x8307 }, \
+ { 0xa438, 0xbfc2 }, \
+ { 0xa438, 0x5f1a }, \
+ { 0xa438, 0x95f7 }, \
+ { 0xa438, 0x05ee }, \
+ { 0xa438, 0xffd2 }, \
+ { 0xa438, 0x00d8 }, \
+ { 0xa438, 0xf605 }, \
+ { 0xa438, 0x1f11 }, \
+ { 0xa438, 0xef60 }, \
+ { 0xa438, 0xbf8b }, \
+ { 0xa438, 0x3002 }, \
+ { 0xa438, 0x6c4e }, \
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+ { 0xa438, 0xf3bf }, \
+ { 0xa438, 0x867b }, \
+ { 0xa438, 0x024f }, \
+ { 0xa438, 0x48ae }, \
+ { 0xa438, 0x29a1 }, \
+ { 0xa438, 0x070b }, \
+ { 0xa438, 0xae24 }, \
+ { 0xa438, 0xbf86 }, \
+ { 0xa438, 0x8102 }, \
+ { 0xa438, 0x4f67 }, \
+ { 0xa438, 0xad28 }, \
+ { 0xa438, 0x1be1 }, \
+ { 0xa438, 0x8ff4 }, \
+ { 0xa438, 0xbf86 }, \
+ { 0xa438, 0x7502 }, \
+ { 0xa438, 0x4f48 }, \
+ { 0xa438, 0xe18f }, \
+ { 0xa438, 0xf5bf }, \
+ { 0xa438, 0x8678 }, \
+ { 0xa438, 0x024f }, \
+ { 0xa438, 0x48e1 }, \
+ { 0xa438, 0x8ff6 }, \
+ { 0xa438, 0xbf86 }, \
+ { 0xa438, 0x7b02 }, \
+ { 0xa438, 0x4f48 }, \
+ { 0xa438, 0xaf09 }, \
+ { 0xa438, 0x8420 }, \
+ { 0xa438, 0xbc32 }, \
+ { 0xa438, 0x20bc }, \
+ { 0xa438, 0x3e76 }, \
+ { 0xa438, 0xbc08 }, \
+ { 0xa438, 0xfda6 }, \
+ { 0xa438, 0x1a00 }, \
+ { 0xa438, 0xb64e }, \
+ { 0xa438, 0xd101 }, \
+ { 0xa438, 0xbf85 }, \
+ { 0xa438, 0xa402 }, \
+ { 0xa438, 0x4f48 }, \
+ { 0xa438, 0xbf85 }, \
+ { 0xa438, 0xa702 }, \
+ { 0xa438, 0x54c0 }, \
+ { 0xa438, 0xd10f }, \
+ { 0xa438, 0xbf85 }, \
+ { 0xa438, 0xaa02 }, \
+ { 0xa438, 0x4f48 }, \
+ { 0xa438, 0x024d }, \
+ { 0xa438, 0x6abf }, \
+ { 0xa438, 0x85ad }, \
+ { 0xa438, 0x024f }, \
+ { 0xa438, 0x67bf }, \
+ { 0xa438, 0x8ff7 }, \
+ { 0xa438, 0xddbf }, \
+ { 0xa438, 0x85b0 }, \
+ { 0xa438, 0x024f }, \
+ { 0xa438, 0x67bf }, \
+ { 0xa438, 0x8ff8 }, \
+ { 0xa438, 0xddbf }, \
+ { 0xa438, 0x85b3 }, \
+ { 0xa438, 0x024f }, \
+ { 0xa438, 0x67bf }, \
+ { 0xa438, 0x8ff9 }, \
+ { 0xa438, 0xddbf }, \
+ { 0xa438, 0x85b6 }, \
+ { 0xa438, 0x024f }, \
+ { 0xa438, 0x67bf }, \
+ { 0xa438, 0x8ffa }, \
+ { 0xa438, 0xddd1 }, \
+ { 0xa438, 0x00bf }, \
+ { 0xa438, 0x85aa }, \
+ { 0xa438, 0x024f }, \
+ { 0xa438, 0x4802 }, \
+ { 0xa438, 0x4d6a }, \
+ { 0xa438, 0xbf85 }, \
+ { 0xa438, 0xad02 }, \
+ { 0xa438, 0x4f67 }, \
+ { 0xa438, 0xbf8f }, \
+ { 0xa438, 0xfbdd }, \
+ { 0xa438, 0xbf85 }, \
+ { 0xa438, 0xb002 }, \
+ { 0xa438, 0x4f67 }, \
+ { 0xa438, 0xbf8f }, \
+ { 0xa438, 0xfcdd }, \
+ { 0xa438, 0xbf85 }, \
+ { 0xa438, 0xb302 }, \
+ { 0xa438, 0x4f67 }, \
+ { 0xa438, 0xbf8f }, \
+ { 0xa438, 0xfddd }, \
+ { 0xa438, 0xbf85 }, \
+ { 0xa438, 0xb602 }, \
+ { 0xa438, 0x4f67 }, \
+ { 0xa438, 0xbf8f }, \
+ { 0xa438, 0xfedd }, \
+ { 0xa438, 0xbf85 }, \
+ { 0xa438, 0xa702 }, \
+ { 0xa438, 0x54b7 }, \
+ { 0xa438, 0xaf00 }, \
+ { 0xa438, 0x8800 }, \
+ { 0xa436, 0xb818 }, \
+ { 0xa438, 0x38b8 }, \
+ { 0xa436, 0xb81a }, \
+ { 0xa438, 0x0444 }, \
+ { 0xa436, 0xb81c }, \
+ { 0xa438, 0x40ee }, \
+ { 0xa436, 0xb81e }, \
+ { 0xa438, 0x3c1a }, \
+ { 0xa436, 0xb850 }, \
+ { 0xa438, 0x0981 }, \
+ { 0xa436, 0xb852 }, \
+ { 0xa438, 0x0085 }, \
+ { 0xa436, 0xb878 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xb884 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xb832 }, \
+ { 0xa438, 0x003f }, \
+ { 0xa436, 0x0000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa436, 0xb82e }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa436, 0x8024 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xb820, 0x0000 }, \
+ { 0xa436, 0x801e }, \
+ { 0xa438, 0x0021 }
+
+#define RTL8125_MAC_CFG5_MCU \
+ { 0xa436, 0x8024 }, \
+ { 0xa438, 0x3701 }, \
+ { 0xa436, 0xb82e }, \
+ { 0xa438, 0x0001 }, \
+ { 0xb820, 0x0090 }, \
+ { 0xa436, 0xa016 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa436, 0xa012 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa436, 0xa014 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8010 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x801a }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8024 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x802f }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8051 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8057 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8063 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8068 }, \
+ { 0xa438, 0xd093 }, \
+ { 0xa438, 0xd1c4 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x135c }, \
+ { 0xa438, 0xd704 }, \
+ { 0xa438, 0x5fbc }, \
+ { 0xa438, 0xd504 }, \
+ { 0xa438, 0xc9f1 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x0fc9 }, \
+ { 0xa438, 0xbb50 }, \
+ { 0xa438, 0xd505 }, \
+ { 0xa438, 0xa202 }, \
+ { 0xa438, 0xd504 }, \
+ { 0xa438, 0x8c0f }, \
+ { 0xa438, 0xd500 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x1519 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x1548 }, \
+ { 0xa438, 0x2f70 }, \
+ { 0xa438, 0x802a }, \
+ { 0xa438, 0x2f73 }, \
+ { 0xa438, 0x156a }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x155c }, \
+ { 0xa438, 0xd505 }, \
+ { 0xa438, 0xa202 }, \
+ { 0xa438, 0xd500 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x1551 }, \
+ { 0xa438, 0xc0c1 }, \
+ { 0xa438, 0xc0c0 }, \
+ { 0xa438, 0xd05a }, \
+ { 0xa438, 0xd1ba }, \
+ { 0xa438, 0xd701 }, \
+ { 0xa438, 0x2529 }, \
+ { 0xa438, 0x022a }, \
+ { 0xa438, 0xd0a7 }, \
+ { 0xa438, 0xd1b9 }, \
+ { 0xa438, 0xa208 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x080e }, \
+ { 0xa438, 0xd701 }, \
+ { 0xa438, 0x408b }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a65 }, \
+ { 0xa438, 0xf003 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0a6b }, \
+ { 0xa438, 0xd701 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0920 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0915 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0909 }, \
+ { 0xa438, 0x228f }, \
+ { 0xa438, 0x8038 }, \
+ { 0xa438, 0x9801 }, \
+ { 0xa438, 0xd71e }, \
+ { 0xa438, 0x5d61 }, \
+ { 0xa438, 0xd701 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x022a }, \
+ { 0xa438, 0x2005 }, \
+ { 0xa438, 0x091a }, \
+ { 0xa438, 0x3bd9 }, \
+ { 0xa438, 0x0919 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x0916 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x14c5 }, \
+ { 0xa438, 0xd703 }, \
+ { 0xa438, 0x3181 }, \
+ { 0xa438, 0x8061 }, \
+ { 0xa438, 0x60ad }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x135c }, \
+ { 0xa438, 0xd703 }, \
+ { 0xa438, 0x5fba }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x0cc7 }, \
+ { 0xa438, 0xd096 }, \
+ { 0xa438, 0xd1a9 }, \
+ { 0xa438, 0xd503 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x0c94 }, \
+ { 0xa436, 0xa026 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa024 }, \
+ { 0xa438, 0x0c93 }, \
+ { 0xa436, 0xa022 }, \
+ { 0xa438, 0x0cc5 }, \
+ { 0xa436, 0xa020 }, \
+ { 0xa438, 0x0915 }, \
+ { 0xa436, 0xa006 }, \
+ { 0xa438, 0x020a }, \
+ { 0xa436, 0xa004 }, \
+ { 0xa438, 0x155b }, \
+ { 0xa436, 0xa002 }, \
+ { 0xa438, 0x1542 }, \
+ { 0xa436, 0xa000 }, \
+ { 0xa438, 0x0fc7 }, \
+ { 0xa436, 0xa008 }, \
+ { 0xa438, 0x7f00 }, \
+ { 0xa436, 0xa016 }, \
+ { 0xa438, 0x0010 }, \
+ { 0xa436, 0xa012 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa436, 0xa014 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8010 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x801d }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x802c }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x802c }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x802c }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x802c }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x802c }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x802c }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x6090 }, \
+ { 0xa438, 0x60d1 }, \
+ { 0xa438, 0xc95c }, \
+ { 0xa438, 0xf007 }, \
+ { 0xa438, 0x60b1 }, \
+ { 0xa438, 0xc95a }, \
+ { 0xa438, 0xf004 }, \
+ { 0xa438, 0xc956 }, \
+ { 0xa438, 0xf002 }, \
+ { 0xa438, 0xc94e }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x00cd }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x6090 }, \
+ { 0xa438, 0x60d1 }, \
+ { 0xa438, 0xc95c }, \
+ { 0xa438, 0xf007 }, \
+ { 0xa438, 0x60b1 }, \
+ { 0xa438, 0xc95a }, \
+ { 0xa438, 0xf004 }, \
+ { 0xa438, 0xc956 }, \
+ { 0xa438, 0xf002 }, \
+ { 0xa438, 0xc94e }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x022a }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x0132 }, \
+ { 0xa436, 0xa08e }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa08c }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa08a }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa088 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa086 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa084 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa082 }, \
+ { 0xa438, 0x012f }, \
+ { 0xa436, 0xa080 }, \
+ { 0xa438, 0x00cc }, \
+ { 0xa436, 0xa090 }, \
+ { 0xa438, 0x0103 }, \
+ { 0xa436, 0xa016 }, \
+ { 0xa438, 0x0020 }, \
+ { 0xa436, 0xa012 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa436, 0xa014 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8010 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8020 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x802a }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x8035 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x803c }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x803c }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x803c }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x803c }, \
+ { 0xa438, 0xd107 }, \
+ { 0xa438, 0xd042 }, \
+ { 0xa438, 0xa404 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x09df }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5fb4 }, \
+ { 0xa438, 0x8280 }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x6065 }, \
+ { 0xa438, 0xd125 }, \
+ { 0xa438, 0xf002 }, \
+ { 0xa438, 0xd12b }, \
+ { 0xa438, 0xd040 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x077f }, \
+ { 0xa438, 0x0cf0 }, \
+ { 0xa438, 0x0c50 }, \
+ { 0xa438, 0xd104 }, \
+ { 0xa438, 0xd040 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0aa8 }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5fb4 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x0a2e }, \
+ { 0xa438, 0xcb9b }, \
+ { 0xa438, 0xd110 }, \
+ { 0xa438, 0xd040 }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x0b7b }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x09df }, \
+ { 0xa438, 0xd700 }, \
+ { 0xa438, 0x5fb4 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x081b }, \
+ { 0xa438, 0x1000 }, \
+ { 0xa438, 0x09df }, \
+ { 0xa438, 0xd704 }, \
+ { 0xa438, 0x7fb8 }, \
+ { 0xa438, 0xa718 }, \
+ { 0xa438, 0x1800 }, \
+ { 0xa438, 0x074e }, \
+ { 0xa436, 0xa10e }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa10c }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa10a }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa108 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xa106 }, \
+ { 0xa438, 0x074d }, \
+ { 0xa436, 0xa104 }, \
+ { 0xa438, 0x0818 }, \
+ { 0xa436, 0xa102 }, \
+ { 0xa438, 0x0a2c }, \
+ { 0xa436, 0xa100 }, \
+ { 0xa438, 0x077e }, \
+ { 0xa436, 0xa110 }, \
+ { 0xa438, 0x000f }, \
+ { 0xa436, 0xb87c }, \
+ { 0xa438, 0x8625 }, \
+ { 0xa436, 0xb87e }, \
+ { 0xa438, 0xaf86 }, \
+ { 0xa438, 0x3daf }, \
+ { 0xa438, 0x8689 }, \
+ { 0xa438, 0xaf88 }, \
+ { 0xa438, 0x69af }, \
+ { 0xa438, 0x8887 }, \
+ { 0xa438, 0xaf88 }, \
+ { 0xa438, 0x9caf }, \
+ { 0xa438, 0x889c }, \
+ { 0xa438, 0xaf88 }, \
+ { 0xa438, 0x9caf }, \
+ { 0xa438, 0x889c }, \
+ { 0xa438, 0xbf86 }, \
+ { 0xa438, 0x49d7 }, \
+ { 0xa438, 0x0040 }, \
+ { 0xa438, 0x0277 }, \
+ { 0xa438, 0x7daf }, \
+ { 0xa438, 0x2727 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x7205 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x7208 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x71f3 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x71f6 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x7229 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x722c }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x7217 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x721a }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x721d }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x7211 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x7220 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x7214 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x722f }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x7223 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x7232 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa438, 0x7226 }, \
+ { 0xa438, 0xf8f9 }, \
+ { 0xa438, 0xfae0 }, \
+ { 0xa438, 0x85b3 }, \
+ { 0xa438, 0x3802 }, \
+ { 0xa438, 0xad27 }, \
+ { 0xa438, 0x02ae }, \
+ { 0xa438, 0x03af }, \
+ { 0xa438, 0x8830 }, \
+ { 0xa438, 0x1f66 }, \
+ { 0xa438, 0xef65 }, \
+ { 0xa438, 0xbfc2 }, \
+ { 0xa438, 0x1f1a }, \
+ { 0xa438, 0x96f7 }, \
+ { 0xa438, 0x05ee }, \
+ { 0xa438, 0xffd2 }, \
+ { 0xa438, 0x00da }, \
+ { 0xa438, 0xf605 }, \
+ { 0xa438, 0xbfc2 }, \
+ { 0xa438, 0x2f1a }, \
+ { 0xa438, 0x96f7 }, \
+ { 0xa438, 0x05ee }, \
+ { 0xa438, 0xffd2 }, \
+ { 0xa438, 0x00db }, \
+ { 0xa438, 0xf605 }, \
+ { 0xa438, 0xef02 }, \
+ { 0xa438, 0x1f11 }, \
+ { 0xa438, 0x0d42 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x4202 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xef02 }, \
+ { 0xa438, 0x1b03 }, \
+ { 0xa438, 0x1f11 }, \
+ { 0xa438, 0x0d42 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x4502 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xef02 }, \
+ { 0xa438, 0x1a03 }, \
+ { 0xa438, 0x1f11 }, \
+ { 0xa438, 0x0d42 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x4802 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xbfc2 }, \
+ { 0xa438, 0x3f1a }, \
+ { 0xa438, 0x96f7 }, \
+ { 0xa438, 0x05ee }, \
+ { 0xa438, 0xffd2 }, \
+ { 0xa438, 0x00da }, \
+ { 0xa438, 0xf605 }, \
+ { 0xa438, 0xbfc2 }, \
+ { 0xa438, 0x4f1a }, \
+ { 0xa438, 0x96f7 }, \
+ { 0xa438, 0x05ee }, \
+ { 0xa438, 0xffd2 }, \
+ { 0xa438, 0x00db }, \
+ { 0xa438, 0xf605 }, \
+ { 0xa438, 0xef02 }, \
+ { 0xa438, 0x1f11 }, \
+ { 0xa438, 0x0d42 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x4b02 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xef02 }, \
+ { 0xa438, 0x1b03 }, \
+ { 0xa438, 0x1f11 }, \
+ { 0xa438, 0x0d42 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x4e02 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xef02 }, \
+ { 0xa438, 0x1a03 }, \
+ { 0xa438, 0x1f11 }, \
+ { 0xa438, 0x0d42 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x5102 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xef56 }, \
+ { 0xa438, 0xd020 }, \
+ { 0xa438, 0x1f11 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x5402 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x5702 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x5a02 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xe185 }, \
+ { 0xa438, 0xa0ef }, \
+ { 0xa438, 0x0348 }, \
+ { 0xa438, 0x0a28 }, \
+ { 0xa438, 0x05ef }, \
+ { 0xa438, 0x201b }, \
+ { 0xa438, 0x01ad }, \
+ { 0xa438, 0x2735 }, \
+ { 0xa438, 0x1f44 }, \
+ { 0xa438, 0xe085 }, \
+ { 0xa438, 0x88e1 }, \
+ { 0xa438, 0x8589 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x5d02 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xe085 }, \
+ { 0xa438, 0x8ee1 }, \
+ { 0xa438, 0x858f }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x6002 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xe085 }, \
+ { 0xa438, 0x94e1 }, \
+ { 0xa438, 0x8595 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x6302 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xe085 }, \
+ { 0xa438, 0x9ae1 }, \
+ { 0xa438, 0x859b }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x6602 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xaf88 }, \
+ { 0xa438, 0x3cbf }, \
+ { 0xa438, 0x883f }, \
+ { 0xa438, 0x026e }, \
+ { 0xa438, 0x9cad }, \
+ { 0xa438, 0x2835 }, \
+ { 0xa438, 0x1f44 }, \
+ { 0xa438, 0xe08f }, \
+ { 0xa438, 0xf8e1 }, \
+ { 0xa438, 0x8ff9 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x5d02 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xe08f }, \
+ { 0xa438, 0xfae1 }, \
+ { 0xa438, 0x8ffb }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x6002 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xe08f }, \
+ { 0xa438, 0xfce1 }, \
+ { 0xa438, 0x8ffd }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x6302 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xe08f }, \
+ { 0xa438, 0xfee1 }, \
+ { 0xa438, 0x8fff }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x6602 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xaf88 }, \
+ { 0xa438, 0x3ce1 }, \
+ { 0xa438, 0x85a1 }, \
+ { 0xa438, 0x1b21 }, \
+ { 0xa438, 0xad37 }, \
+ { 0xa438, 0x341f }, \
+ { 0xa438, 0x44e0 }, \
+ { 0xa438, 0x858a }, \
+ { 0xa438, 0xe185 }, \
+ { 0xa438, 0x8bbf }, \
+ { 0xa438, 0x885d }, \
+ { 0xa438, 0x026e }, \
+ { 0xa438, 0x7de0 }, \
+ { 0xa438, 0x8590 }, \
+ { 0xa438, 0xe185 }, \
+ { 0xa438, 0x91bf }, \
+ { 0xa438, 0x8860 }, \
+ { 0xa438, 0x026e }, \
+ { 0xa438, 0x7de0 }, \
+ { 0xa438, 0x8596 }, \
+ { 0xa438, 0xe185 }, \
+ { 0xa438, 0x97bf }, \
+ { 0xa438, 0x8863 }, \
+ { 0xa438, 0x026e }, \
+ { 0xa438, 0x7de0 }, \
+ { 0xa438, 0x859c }, \
+ { 0xa438, 0xe185 }, \
+ { 0xa438, 0x9dbf }, \
+ { 0xa438, 0x8866 }, \
+ { 0xa438, 0x026e }, \
+ { 0xa438, 0x7dae }, \
+ { 0xa438, 0x401f }, \
+ { 0xa438, 0x44e0 }, \
+ { 0xa438, 0x858c }, \
+ { 0xa438, 0xe185 }, \
+ { 0xa438, 0x8dbf }, \
+ { 0xa438, 0x885d }, \
+ { 0xa438, 0x026e }, \
+ { 0xa438, 0x7de0 }, \
+ { 0xa438, 0x8592 }, \
+ { 0xa438, 0xe185 }, \
+ { 0xa438, 0x93bf }, \
+ { 0xa438, 0x8860 }, \
+ { 0xa438, 0x026e }, \
+ { 0xa438, 0x7de0 }, \
+ { 0xa438, 0x8598 }, \
+ { 0xa438, 0xe185 }, \
+ { 0xa438, 0x99bf }, \
+ { 0xa438, 0x8863 }, \
+ { 0xa438, 0x026e }, \
+ { 0xa438, 0x7de0 }, \
+ { 0xa438, 0x859e }, \
+ { 0xa438, 0xe185 }, \
+ { 0xa438, 0x9fbf }, \
+ { 0xa438, 0x8866 }, \
+ { 0xa438, 0x026e }, \
+ { 0xa438, 0x7dae }, \
+ { 0xa438, 0x0ce1 }, \
+ { 0xa438, 0x85b3 }, \
+ { 0xa438, 0x3904 }, \
+ { 0xa438, 0xac2f }, \
+ { 0xa438, 0x04ee }, \
+ { 0xa438, 0x85b3 }, \
+ { 0xa438, 0x00af }, \
+ { 0xa438, 0x39d9 }, \
+ { 0xa438, 0x22ac }, \
+ { 0xa438, 0xeaf0 }, \
+ { 0xa438, 0xacf6 }, \
+ { 0xa438, 0xf0ac }, \
+ { 0xa438, 0xfaf0 }, \
+ { 0xa438, 0xacf8 }, \
+ { 0xa438, 0xf0ac }, \
+ { 0xa438, 0xfcf0 }, \
+ { 0xa438, 0xad00 }, \
+ { 0xa438, 0xf0ac }, \
+ { 0xa438, 0xfef0 }, \
+ { 0xa438, 0xacf0 }, \
+ { 0xa438, 0xf0ac }, \
+ { 0xa438, 0xf4f0 }, \
+ { 0xa438, 0xacf2 }, \
+ { 0xa438, 0xf0ac }, \
+ { 0xa438, 0xb0f0 }, \
+ { 0xa438, 0xacae }, \
+ { 0xa438, 0xf0ac }, \
+ { 0xa438, 0xacf0 }, \
+ { 0xa438, 0xacaa }, \
+ { 0xa438, 0xa100 }, \
+ { 0xa438, 0x0ce1 }, \
+ { 0xa438, 0x8ff7 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x8402 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xaf26 }, \
+ { 0xa438, 0xe9e1 }, \
+ { 0xa438, 0x8ff6 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x8402 }, \
+ { 0xa438, 0x6e7d }, \
+ { 0xa438, 0xaf26 }, \
+ { 0xa438, 0xf520 }, \
+ { 0xa438, 0xac86 }, \
+ { 0xa438, 0xbf88 }, \
+ { 0xa438, 0x3f02 }, \
+ { 0xa438, 0x6e9c }, \
+ { 0xa438, 0xad28 }, \
+ { 0xa438, 0x03af }, \
+ { 0xa438, 0x3324 }, \
+ { 0xa438, 0xad38 }, \
+ { 0xa438, 0x03af }, \
+ { 0xa438, 0x32e6 }, \
+ { 0xa438, 0xaf32 }, \
+ { 0xa438, 0xfb00 }, \
+ { 0xa436, 0xb87c }, \
+ { 0xa438, 0x8ff6 }, \
+ { 0xa436, 0xb87e }, \
+ { 0xa438, 0x0705 }, \
+ { 0xa436, 0xb87c }, \
+ { 0xa438, 0x8ff8 }, \
+ { 0xa436, 0xb87e }, \
+ { 0xa438, 0x19cc }, \
+ { 0xa436, 0xb87c }, \
+ { 0xa438, 0x8ffa }, \
+ { 0xa436, 0xb87e }, \
+ { 0xa438, 0x28e3 }, \
+ { 0xa436, 0xb87c }, \
+ { 0xa438, 0x8ffc }, \
+ { 0xa436, 0xb87e }, \
+ { 0xa438, 0x1047 }, \
+ { 0xa436, 0xb87c }, \
+ { 0xa438, 0x8ffe }, \
+ { 0xa436, 0xb87e }, \
+ { 0xa438, 0x0a45 }, \
+ { 0xa436, 0xb85e }, \
+ { 0xa438, 0x271e }, \
+ { 0xa436, 0xb860 }, \
+ { 0xa438, 0x3846 }, \
+ { 0xa436, 0xb862 }, \
+ { 0xa438, 0x26e6 }, \
+ { 0xa436, 0xb864 }, \
+ { 0xa438, 0x32e3 }, \
+ { 0xa436, 0xb886 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xb888 }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xb88a }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xb88c }, \
+ { 0xa438, 0xffff }, \
+ { 0xa436, 0xb838 }, \
+ { 0xa438, 0x000f }, \
+ { 0xb820, 0x0010 }, \
+ { 0xa436, 0x0000 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa436, 0xb82e }, \
+ { 0xa438, 0x0000 }, \
+ { 0xa436, 0x8024 }, \
+ { 0xa438, 0x0000 }, \
+ { 0xb820, 0x0000 }, \
+ { 0xa436, 0x801e }, \
+ { 0xa438, 0x0016 }
