Module Name: src
Committed By: simonb
Date: Thu Mar 18 23:18:36 UTC 2021
Modified Files:
src/sys/arch/mips/include: ptrace.h
Log Message:
Add PTRACE_ILLEGAL_ASM using the MIPS32r6/MIPS64r6 backwards and
forwards compatible "sigrie" instruction to generate a Reserved
Instruction trap.
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/include/ptrace.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/ptrace.h
diff -u src/sys/arch/mips/include/ptrace.h:1.18 src/sys/arch/mips/include/ptrace.h:1.19
--- src/sys/arch/mips/include/ptrace.h:1.18 Sun Jul 26 08:08:41 2020
+++ src/sys/arch/mips/include/ptrace.h Thu Mar 18 23:18:36 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: ptrace.h,v 1.18 2020/07/26 08:08:41 simonb Exp $ */
+/* $NetBSD: ptrace.h,v 1.19 2021/03/18 23:18:36 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -67,6 +67,21 @@
#define PTRACE_REG_SP(r) (r)->r_regs[29]
#define PTRACE_REG_INTRV(r) (r)->r_regs[2]
+/*
+ * The sigrie is defined in the MIPS32r6 and MIPS64r6 specs to
+ * generate a Reserved Instruction trap but uses a previously
+ * reserved instruction encoding and is thus both backwards and
+ * forwards compatible.
+ */
+#define PTRACE_ILLEGAL_ASM do { \
+ asm volatile( \
+ ".set push; " \
+ ".set mips32r6; " \
+ "sigrie 0; " \
+ ".set pop; " \
+ ); \
+ } while (0);
+
#define PTRACE_BREAKPOINT ((const uint8_t[]) { 0x00, 0x00, 0x00, 0x0d })
#define PTRACE_BREAKPOINT_ASM __asm __volatile("break")
#define PTRACE_BREAKPOINT_SIZE 4
