Module Name: src
Committed By: skrll
Date: Sat May 1 07:09:55 UTC 2021
Modified Files:
src/sys/arch/riscv/include: sysreg.h
Log Message:
Provide riscvreg_satp_{read,write}
To generate a diff of this commit:
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/include/sysreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.12 src/sys/arch/riscv/include/sysreg.h:1.13
--- src/sys/arch/riscv/include/sysreg.h:1.12 Sat May 1 07:09:04 2021
+++ src/sys/arch/riscv/include/sysreg.h Sat May 1 07:09:55 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.12 2021/05/01 07:09:04 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.13 2021/05/01 07:09:55 skrll Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,6 +36,8 @@
#include <sys/param.h>
#endif
+#include <riscv/reg.h>
+
#define FCSR_FMASK 0 // no exception bits
#define FCSR_FRM __BITS(7,5)
#define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even
@@ -262,6 +264,20 @@ riscvreg_cycle_read(void)
#define SATP_PPN __BITS(21,0)
#endif
+static inline uintptr_t
+riscvreg_satp_read(void)
+{
+ uintptr_t satp;
+ __asm __volatile("csrr %0, satp" : "=r" (satp));
+ return satp;
+}
+
+static inline void
+riscvreg_satp_write(uintptr_t satp)
+{
+ __asm __volatile("csrw satp, %0" :: "r" (satp));
+}
+
static inline uint32_t
riscvreg_asid_read(void)
{
