Module Name: src
Committed By: andvar
Date: Sat Jul 31 14:36:33 UTC 2021
Modified Files:
src/common/lib/libc/hash/sha3: sha3.c
src/sys/arch/arm/ixp12x0: ixp12x0_clk.c
src/sys/arch/dreamcast/dev: pvr.c
src/sys/dev/ic: mb86950.c mb86960.c mb86960var.h
src/sys/dev/usb: umcs.h
Log Message:
fix more typos in style found one in file - check/fix them all.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/common/lib/libc/hash/sha3/sha3.c
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/arm/ixp12x0/ixp12x0_clk.c
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/dreamcast/dev/pvr.c
cvs rdiff -u -r1.34 -r1.35 src/sys/dev/ic/mb86950.c
cvs rdiff -u -r1.95 -r1.96 src/sys/dev/ic/mb86960.c
cvs rdiff -u -r1.40 -r1.41 src/sys/dev/ic/mb86960var.h
cvs rdiff -u -r1.2 -r1.3 src/sys/dev/usb/umcs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/hash/sha3/sha3.c
diff -u src/common/lib/libc/hash/sha3/sha3.c:1.2 src/common/lib/libc/hash/sha3/sha3.c:1.3
--- src/common/lib/libc/hash/sha3/sha3.c:1.2 Sat May 30 18:40:28 2020
+++ src/common/lib/libc/hash/sha3/sha3.c Sat Jul 31 14:36:33 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: sha3.c,v 1.2 2020/05/30 18:40:28 riastradh Exp $ */
+/* $NetBSD: sha3.c,v 1.3 2021/07/31 14:36:33 andvar Exp $ */
/*-
* Copyright (c) 2015 Taylor R. Campbell
@@ -27,7 +27,7 @@
*/
/*
- * SHA-3: FIPS-202, Permutation-Based Hash and Extendable-Ouptut Functions
+ * SHA-3: FIPS-202, Permutation-Based Hash and Extendable-Output Functions
*/
#if HAVE_NBTOOL_CONFIG_H
@@ -38,14 +38,14 @@
#if defined(_KERNEL) || defined(_STANDALONE)
-__KERNEL_RCSID(0, "$NetBSD: sha3.c,v 1.2 2020/05/30 18:40:28 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sha3.c,v 1.3 2021/07/31 14:36:33 andvar Exp $");
#include <lib/libkern/libkern.h>
#define SHA3_ASSERT KASSERT
#else
-__RCSID("$NetBSD: sha3.c,v 1.2 2020/05/30 18:40:28 riastradh Exp $");
+__RCSID("$NetBSD: sha3.c,v 1.3 2021/07/31 14:36:33 andvar Exp $");
#include "namespace.h"
Index: src/sys/arch/arm/ixp12x0/ixp12x0_clk.c
diff -u src/sys/arch/arm/ixp12x0/ixp12x0_clk.c:1.18 src/sys/arch/arm/ixp12x0/ixp12x0_clk.c:1.19
--- src/sys/arch/arm/ixp12x0/ixp12x0_clk.c:1.18 Fri May 29 12:30:39 2020
+++ src/sys/arch/arm/ixp12x0/ixp12x0_clk.c Sat Jul 31 14:36:33 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: ixp12x0_clk.c,v 1.18 2020/05/29 12:30:39 rin Exp $ */
+/* $NetBSD: ixp12x0_clk.c,v 1.19 2021/07/31 14:36:33 andvar Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
@@ -38,7 +38,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ixp12x0_clk.c,v 1.18 2020/05/29 12:30:39 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ixp12x0_clk.c,v 1.19 2021/07/31 14:36:33 andvar Exp $");
#include <sys/types.h>
#include <sys/param.h>
@@ -314,7 +314,7 @@ delay(unsigned int usecs)
if (ixpclk_sc == NULL) {
#ifdef DEBUG
- printf("delay: called befor start ixpclk\n");
+ printf("delay: called before start ixpclk\n");
#endif
csec = usecs / 10000;
Index: src/sys/arch/dreamcast/dev/pvr.c
diff -u src/sys/arch/dreamcast/dev/pvr.c:1.37 src/sys/arch/dreamcast/dev/pvr.c:1.38
--- src/sys/arch/dreamcast/dev/pvr.c:1.37 Sat Apr 24 23:36:31 2021
+++ src/sys/arch/dreamcast/dev/pvr.c Sat Jul 31 14:36:33 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: pvr.c,v 1.37 2021/04/24 23:36:31 thorpej Exp $ */
+/* $NetBSD: pvr.c,v 1.38 2021/07/31 14:36:33 andvar Exp $ */
/*-
* Copyright (c) 2001 Marcus Comstedt.
@@ -35,7 +35,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: pvr.c,v 1.37 2021/04/24 23:36:31 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pvr.c,v 1.38 2021/07/31 14:36:33 andvar Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -377,7 +377,7 @@ pvrmmap(void *v, void *vs, off_t offset,
/*
* XXX This should be easy to support -- just need to define
- * XXX offsets for the contol regs, etc.
+ * XXX offsets for the control regs, etc.
*/
struct pvr_softc *sc = v;
Index: src/sys/dev/ic/mb86950.c
diff -u src/sys/dev/ic/mb86950.c:1.34 src/sys/dev/ic/mb86950.c:1.35
--- src/sys/dev/ic/mb86950.c:1.34 Tue Feb 4 05:25:39 2020
+++ src/sys/dev/ic/mb86950.c Sat Jul 31 14:36:33 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: mb86950.c,v 1.34 2020/02/04 05:25:39 thorpej Exp $ */
+/* $NetBSD: mb86950.c,v 1.35 2021/07/31 14:36:33 andvar Exp $ */
/*
* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
@@ -67,7 +67,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mb86950.c,v 1.34 2020/02/04 05:25:39 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mb86950.c,v 1.35 2021/07/31 14:36:33 andvar Exp $");
/*
* Device driver for Fujitsu mb86950 based Ethernet cards.
@@ -795,13 +795,13 @@ mb86950_rint(struct mb86950_softc *sc, u
* We just loop checking the flag to pull out all received
* packets.
*
- * We limit the number of iterrations to avoid infinite loop.
+ * We limit the number of iterations to avoid infinite loop.
* It can be caused by a very slow CPU (some broken
* peripheral may insert incredible number of wait cycles)
* or, worse, by a broken mb86950 chip.
*/
for (i = 0; i < sc->rxb_num_pkt; i++) {
- /* Stop the iterration if 86950 indicates no packets. */
+ /* Stop the iteration if 86950 indicates no packets. */
if (bus_space_read_1(bst, bsh, DLCR_RX_MODE) & RX_BUF_EMTY)
break;
Index: src/sys/dev/ic/mb86960.c
diff -u src/sys/dev/ic/mb86960.c:1.95 src/sys/dev/ic/mb86960.c:1.96
--- src/sys/dev/ic/mb86960.c:1.95 Tue Feb 4 05:25:39 2020
+++ src/sys/dev/ic/mb86960.c Sat Jul 31 14:36:33 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: mb86960.c,v 1.95 2020/02/04 05:25:39 thorpej Exp $ */
+/* $NetBSD: mb86960.c,v 1.96 2021/07/31 14:36:33 andvar Exp $ */
/*
* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
@@ -32,7 +32,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mb86960.c,v 1.95 2020/02/04 05:25:39 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mb86960.c,v 1.96 2021/07/31 14:36:33 andvar Exp $");
/*
* Device driver for Fujitsu MB86960A/MB86965A based Ethernet cards.
@@ -582,7 +582,7 @@ mb86960_init(struct mb86960_softc *sc)
ifp->if_flags |= IFF_RUNNING;
/*
- * At this point, the interface is runnung properly,
+ * At this point, the interface is running properly,
* except that it receives *no* packets. we then call
* mb86960_setmode() to tell the chip what packets to be
* received, based on the if_flags and multicast group
@@ -696,7 +696,7 @@ mb86960_start(struct ifnet *ifp)
/*
* Stop accepting more transmission packets temporarily, when
* a filter change request is delayed. Updating the MARs on
- * 86960 flushes the transmisstion buffer, so it is delayed
+ * 86960 flushes the transmission buffer, so it is delayed
* until all buffered transmission packets have been sent
* out.
*/
@@ -860,7 +860,7 @@ mb86960_tint(struct mb86960_softc *sc, u
* 86960 has a design flow on collision count on multiple
* packet transmission. When we send two or more packets
* with one start command (that's what we do when the
- * transmission queue is clauded), 86960 informs us number
+ * transmission queue is crowded), 86960 informs us number
* of collisions occurred on the last packet on the
* transmission only. Number of collisions on previous
* packets are lost. I have told that the fact is clearly
@@ -958,7 +958,7 @@ mb86960_rint(struct mb86960_softc *sc, u
* We just loop checking the flag to pull out all received
* packets.
*
- * We limit the number of iterrations to avoid infinite loop.
+ * We limit the number of iterations to avoid infinite loop.
* It can be caused by a very slow CPU (some broken
* peripheral may insert incredible number of wait cycles)
* or, worse, by a broken MB86960 chip.
@@ -1660,7 +1660,7 @@ mb86960_setmode(struct mb86960_softc *sc
* DLC trashes all packets in both transmission and receive
* buffers when stopped.
*
- * ... Are the above sentenses correct? I have to check the
+ * ... Are the above sentences correct? I have to check the
* manual of the MB86960A. FIXME.
*
* To reduce the packet lossage, we delay the filter update
@@ -1689,7 +1689,7 @@ mb86960_setmode(struct mb86960_softc *sc
/*
* Load a new multicast address filter into MARs.
*
- * The caller must have splnet'ed befor mb86960_loadmar.
+ * The caller must have splnet'ed before mb86960_loadmar.
* This function starts the DLC upon return. So it can be called only
* when the chip is working, i.e., from the driver's point of view, when
* a device is RUNNING. (I mistook the point in previous versions.)
Index: src/sys/dev/ic/mb86960var.h
diff -u src/sys/dev/ic/mb86960var.h:1.40 src/sys/dev/ic/mb86960var.h:1.41
--- src/sys/dev/ic/mb86960var.h:1.40 Mon Apr 13 16:33:24 2015
+++ src/sys/dev/ic/mb86960var.h Sat Jul 31 14:36:33 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: mb86960var.h,v 1.40 2015/04/13 16:33:24 riastradh Exp $ */
+/* $NetBSD: mb86960var.h,v 1.41 2021/07/31 14:36:33 andvar Exp $ */
/*
* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
@@ -130,7 +130,7 @@ struct mb86960_softc {
/* Set by probe() and not modified in later phases. */
uint32_t sc_flags; /* controller quirks */
-#define FE_FLAGS_MB86960 0x0001 /* DLCR7 is differnt on MB86960 */
+#define FE_FLAGS_MB86960 0x0001 /* DLCR7 is different on MB86960 */
#define FE_FLAGS_SBW_BYTE 0x0002 /* byte access mode for system bus */
#define FE_FLAGS_SRAM_150ns 0x0004 /* The board has slow SRAM */
@@ -179,7 +179,7 @@ struct mb86960_softc {
#define FE_RMASK (FE_D3_OVRFLO | FE_D3_CRCERR | \
FE_D3_ALGERR | FE_D3_SRTPKT | FE_D3_PKTRDY)
-/* Maximum number of iterrations for a receive interrupt. */
+/* Maximum number of iterations for a receive interrupt. */
#define FE_MAX_RECV_COUNT ((65536 - 2048 * 2) / 64)
/* Maximum size of SRAM is 65536,
* minimum size of transmission buffer in fe is 2x2KB,
Index: src/sys/dev/usb/umcs.h
diff -u src/sys/dev/usb/umcs.h:1.2 src/sys/dev/usb/umcs.h:1.3
--- src/sys/dev/usb/umcs.h:1.2 Tue Jun 4 10:15:22 2019
+++ src/sys/dev/usb/umcs.h Sat Jul 31 14:36:33 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: umcs.h,v 1.2 2019/06/04 10:15:22 msaitoh Exp $ */
+/* $NetBSD: umcs.h,v 1.3 2021/07/31 14:36:33 andvar Exp $ */
/* $FreeBSD: head/sys/dev/usb/serial/umcs.h 252123 2013-06-23 20:19:51Z thomas $ */
/*-
@@ -34,7 +34,7 @@
#define UMCS7840_READ_LENGTH 1 /* bytes */
#define UMCS7840_CTRL_TIMEOUT 500 /* ms */
-/* Read/Wrtire registers vendor commands */
+/* Read/Write registers vendor commands */
#define MCS7840_RDREQ 0x0d
#define MCS7840_WRREQ 0x0e
@@ -56,16 +56,16 @@
#define MCS7840_DEV_REG_GPIO 0x07 /* GPIO_0 and GPIO_1 bits,
* undocumented, see notes
* below R/W */
-#define MCS7840_DEV_REG_SP2 0x08 /* Options for for UART 2, R/W */
+#define MCS7840_DEV_REG_SP2 0x08 /* Options for UART 2, R/W */
#define MCS7840_DEV_REG_CONTROL2 0x09 /* Control bits for UART 2,
* R/W */
-#define MCS7840_DEV_REG_SP3 0x0a /* Options for for UART 3, R/W */
+#define MCS7840_DEV_REG_SP3 0x0a /* Options for UART 3, R/W */
#define MCS7840_DEV_REG_CONTROL3 0x0b /* Control bits for UART 3,
* R/W */
-#define MCS7840_DEV_REG_SP4 0x0c /* Options for for UART 4, R/W */
+#define MCS7840_DEV_REG_SP4 0x0c /* Options for UART 4, R/W */
#define MCS7840_DEV_REG_CONTROL4 0x0d /* Control bits for UART 4,
* R/W */
-#define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */
+#define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-divider for PLL, R/W */
#define MCS7840_DEV_REG_UNKNOWN1 0x0f /* NOT MENTIONED AND NOT USED */
#define MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */
#define MCS7840_DEV_REG_CLOCK_MUX 0x12 /* PLL input clock & Interrupt
@@ -109,28 +109,28 @@
* 4, R/W */
#define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port
* 1, contains number of
- * availiable bytes, R/Only */
+ * available bytes, R/Only */
#define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port
* 1, contains number of
- * availiable bytes, R/Only */
+ * available bytes, R/Only */
#define MCS7840_DEV_REG_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port
* 2, contains number of
- * availiable bytes, R/Only */
+ * available bytes, R/Only */
#define MCS7840_DEV_REG_BO_FIFO_STAT2 0x35 /* Bulk-out FIFO Stat for Port
* 2, contains number of
- * availiable bytes, R/Only */
+ * available bytes, R/Only */
#define MCS7840_DEV_REG_BI_FIFO_STAT3 0x36 /* Bulk-In FIFO Stat for Port
* 3, contains number of
- * availiable bytes, R/Only */
+ * available bytes, R/Only */
#define MCS7840_DEV_REG_BO_FIFO_STAT3 0x37 /* Bulk-out FIFO Stat for Port
* 3, contains number of
- * availiable bytes, R/Only */
+ * available bytes, R/Only */
#define MCS7840_DEV_REG_BI_FIFO_STAT4 0x38 /* Bulk-In FIFO Stat for Port
* 4, contains number of
- * availiable bytes, R/Only */
+ * available bytes, R/Only */
#define MCS7840_DEV_REG_BO_FIFO_STAT4 0x39 /* Bulk-out FIFO Stat for Port
* 4, contains number of
- * availiable bytes, R/Only */
+ * available bytes, R/Only */
#define MCS7840_DEV_REG_ZERO_PERIOD1 0x3a /* Period between zero out
* frames for Port 1, R/W */
#define MCS7840_DEV_REG_ZERO_PERIOD2 0x3b /* Period between zero out
@@ -141,28 +141,28 @@
* frames for Port 1, R/W */
#define MCS7840_DEV_REG_ZERO_ENABLE 0x3e /* Enable/disable of zero out
* frames, R/W */
-#define MCS7840_DEV_REG_THR_VAL_LOW1 0x3f /* Low 8 bits of threshhold
+#define MCS7840_DEV_REG_THR_VAL_LOW1 0x3f /* Low 8 bits of threshold
* value for Bulk-Out for Port
* 1, R/W */
-#define MCS7840_DEV_REG_THR_VAL_HIGH1 0x40 /* High 1 bit of threshhold
+#define MCS7840_DEV_REG_THR_VAL_HIGH1 0x40 /* High 1 bit of threshold
* value for Bulk-Out and
* enable flag for Port 1, R/W */
-#define MCS7840_DEV_REG_THR_VAL_LOW2 0x41 /* Low 8 bits of threshhold
+#define MCS7840_DEV_REG_THR_VAL_LOW2 0x41 /* Low 8 bits of threshold
* value for Bulk-Out for Port
* 2, R/W */
-#define MCS7840_DEV_REG_THR_VAL_HIGH2 0x42 /* High 1 bit of threshhold
+#define MCS7840_DEV_REG_THR_VAL_HIGH2 0x42 /* High 1 bit of threshold
* value for Bulk-Out and
* enable flag for Port 2, R/W */
-#define MCS7840_DEV_REG_THR_VAL_LOW3 0x43 /* Low 8 bits of threshhold
+#define MCS7840_DEV_REG_THR_VAL_LOW3 0x43 /* Low 8 bits of threshold
* value for Bulk-Out for Port
* 3, R/W */
-#define MCS7840_DEV_REG_THR_VAL_HIGH3 0x44 /* High 1 bit of threshhold
+#define MCS7840_DEV_REG_THR_VAL_HIGH3 0x44 /* High 1 bit of threshold
* value for Bulk-Out and
* enable flag for Port 3, R/W */
#define MCS7840_DEV_REG_THR_VAL_LOW4 0x45 /* Low 8 bits of threshhold
* value for Bulk-Out for Port
* 4, R/W */
-#define MCS7840_DEV_REG_THR_VAL_HIGH4 0x46 /* High 1 bit of threshhold
+#define MCS7840_DEV_REG_THR_VAL_HIGH4 0x46 /* High 1 bit of threshold
* value for Bulk-Out and
* enable flag for Port 4, R/W */
@@ -229,7 +229,7 @@
* Bits for PINPONGx registers
* These registers control how often two input buffers
* for Bulk-In FIFOs are swapped. One of buffers is used
- * for USB trnasfer, other for receiving data from UART.
+ * for USB transfer, other for receiving data from UART.
* Exact meaning of 15 bit value in these registers is unknown
*/
#define MCS7840_DEV_PINPONGHIGH_MULT 128 /* Only 7 bits in PINPONGLOW
@@ -251,7 +251,7 @@
/*
* Constants for PLL dividers
- * Ouptut frequency of PLL is:
+ * Output frequency of PLL is:
* Fout = (N/M) * Fin.
* Default PLL input frequency Fin is 12Mhz (on-chip).
*/
@@ -316,7 +316,7 @@
#define MCS7840_DEV_CLOCK_SELECT_PLL 0x04 /* PLL output (see for M and N
* dividers) */
#define MCS7840_DEV_CLOCK_SELECT_EXT 0x05 /* External clock input
- * (device-dependend) */
+ * (device-dependent) */
#define MCS7840_DEV_CLOCK_SELECT_RES1 0x06 /* Unused */
#define MCS7840_DEV_CLOCK_SELECT_RES2 0x07 /* Unused */
@@ -374,7 +374,7 @@
/* Bits for ZERO_PERIODx */
#define MCS7840_DEV_ZERO_PERIODx_DEF 20 /* Number of Bulk-in requests
- * befor sending zero-sized
+ * before sending zero-sized
* reply */
/* Bits for ZERO_ENABLE */
@@ -398,33 +398,33 @@
#define MCS7840_DEV_THR_VAL_HIGH_ENABLE 0x80 /* Enable threshold */
/* These are documented in "public" datasheet */
-#define MCS7840_DEV_REG_DCR0_1 0x04 /* Device contol register 0 for Port
+#define MCS7840_DEV_REG_DCR0_1 0x04 /* Device control register 0 for Port
* 1, R/W */
-#define MCS7840_DEV_REG_DCR1_1 0x05 /* Device contol register 1 for Port
+#define MCS7840_DEV_REG_DCR1_1 0x05 /* Device control register 1 for Port
* 1, R/W */
-#define MCS7840_DEV_REG_DCR2_1 0x06 /* Device contol register 2 for Port
+#define MCS7840_DEV_REG_DCR2_1 0x06 /* Device control register 2 for Port
* 1, R/W */
-#define MCS7840_DEV_REG_DCR0_2 0x16 /* Device contol register 0 for Port
+#define MCS7840_DEV_REG_DCR0_2 0x16 /* Device control register 0 for Port
* 2, R/W */
-#define MCS7840_DEV_REG_DCR1_2 0x17 /* Device contol register 1 for Port
+#define MCS7840_DEV_REG_DCR1_2 0x17 /* Device control register 1 for Port
* 2, R/W */
-#define MCS7840_DEV_REG_DCR2_2 0x18 /* Device contol register 2 for Port
+#define MCS7840_DEV_REG_DCR2_2 0x18 /* Device control register 2 for Port
* 2, R/W */
-#define MCS7840_DEV_REG_DCR0_3 0x19 /* Device contol register 0 for Port
+#define MCS7840_DEV_REG_DCR0_3 0x19 /* Device control register 0 for Port
* 3, R/W */
-#define MCS7840_DEV_REG_DCR1_3 0x1a /* Device contol register 1 for Port
+#define MCS7840_DEV_REG_DCR1_3 0x1a /* Device control register 1 for Port
* 3, R/W */
-#define MCS7840_DEV_REG_DCR2_3 0x1b /* Device contol register 2 for Port
+#define MCS7840_DEV_REG_DCR2_3 0x1b /* Device control register 2 for Port
* 3, R/W */
-#define MCS7840_DEV_REG_DCR0_4 0x1c /* Device contol register 0 for Port
+#define MCS7840_DEV_REG_DCR0_4 0x1c /* Device control register 0 for Port
* 4, R/W */
-#define MCS7840_DEV_REG_DCR1_4 0x1d /* Device contol register 1 for Port
+#define MCS7840_DEV_REG_DCR1_4 0x1d /* Device control register 1 for Port
* 4, R/W */
-#define MCS7840_DEV_REG_DCR2_4 0x1e /* Device contol register 2 for Port
+#define MCS7840_DEV_REG_DCR2_4 0x1e /* Device control register 2 for Port
* 4, R/W */
/* Bits of DCR0 registers, documented in datasheet */
-#define MCS7840_DEV_DCR0_PWRSAVE 0x01 /* Shutdown transiver
+#define MCS7840_DEV_DCR0_PWRSAVE 0x01 /* Shutdown transceiver
* when USB Suspend is
* engaged, default = 1 */
#define MCS7840_DEV_DCR0_RESERVED1 0x02 /* Unused */
@@ -508,7 +508,7 @@
/* Interrupt endpoint bytes & bits */
#define MCS7840_IEP_FIFO_STATUS_INDEX 5
/*
- * Thesse can be calculated as "1 << portnumber" for Bulk-out and
+ * These can be calculated as "1 << portnumber" for Bulk-out and
* "1 << (portnumber+1)" for Bulk-in
*/
#define MCS7840_IEP_BO_PORT1_HASDATA 0x01
@@ -529,7 +529,7 @@
* R/W */
#define MCS7840_UART_REG_FCR 0x02 /* FIFO Control register -
* W/Only */
-#define MCS7840_UART_REG_ISR 0x02 /* Interrupt Status Registter
+#define MCS7840_UART_REG_ISR 0x02 /* Interrupt Status Register
* R/Only */
#define MCS7840_UART_REG_LCR 0x03 /* Line control register R/W */
#define MCS7840_UART_REG_MCR 0x04 /* Modem control register R/W */
@@ -542,11 +542,11 @@
#define MCS7840_UART_REG_DLM 0x01 /* High bits of BAUD divider */
/* IER bits */
-#define MCS7840_UART_IER_RXREADY 0x01 /* RX Ready interrumpt mask */
-#define MCS7840_UART_IER_TXREADY 0x02 /* TX Ready interrumpt mask */
-#define MCS7840_UART_IER_RXSTAT 0x04 /* RX Status interrumpt mask */
+#define MCS7840_UART_IER_RXREADY 0x01 /* RX Ready interrupt mask */
+#define MCS7840_UART_IER_TXREADY 0x02 /* TX Ready interrupt mask */
+#define MCS7840_UART_IER_RXSTAT 0x04 /* RX Status interrupt mask */
#define MCS7840_UART_IER_MODEM 0x08 /* Modem status change
- * interrumpt mask */
+ * interrupt mask */
#define MCS7840_UART_IER_SLEEP 0x10 /* SLEEP enable */
/* FCR bits */
