Module Name: src
Committed By: andvar
Date: Tue Aug 3 23:12:14 UTC 2021
Modified Files:
src/sys/arch/mips/cavium: octeon_cpunode.c
src/sys/arch/powerpc/include/booke: spr.h
src/sys/arch/riscv/riscv: fpu.c locore.S
src/sys/arch/vax/include: ka48.h
src/sys/dev/i2c: ds1307.c
src/sys/sys: evcnt.h
Log Message:
Fix various typos in comments. Also add missing NetBSD RCS Id in some of these
files.
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/mips/cavium/octeon_cpunode.c
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/powerpc/include/booke/spr.h
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/riscv/fpu.c
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/riscv/riscv/locore.S
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/vax/include/ka48.h
cvs rdiff -u -r1.38 -r1.39 src/sys/dev/i2c/ds1307.c
cvs rdiff -u -r1.9 -r1.10 src/sys/sys/evcnt.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/cavium/octeon_cpunode.c
diff -u src/sys/arch/mips/cavium/octeon_cpunode.c:1.19 src/sys/arch/mips/cavium/octeon_cpunode.c:1.20
--- src/sys/arch/mips/cavium/octeon_cpunode.c:1.19 Sat Apr 24 23:36:42 2021
+++ src/sys/arch/mips/cavium/octeon_cpunode.c Tue Aug 3 23:12:14 2021
@@ -1,3 +1,5 @@
+/* $NetBSD: octeon_cpunode.c,v 1.20 2021/08/03 23:12:14 andvar Exp $ */
+
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -29,7 +31,7 @@
#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_cpunode.c,v 1.19 2021/04/24 23:36:42 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_cpunode.c,v 1.20 2021/08/03 23:12:14 andvar Exp $");
#include "locators.h"
#include "cpunode.h"
@@ -214,7 +216,7 @@ octeon_cpu_init(struct cpu_info *ci)
(*mips64r2_locore_vec.ljv_tlb_invalidate_all)();
mips3_cp0_wired_write(pmap_tlb0_info.ti_wired);
- // First thing is setup the execption vectors for this cpu.
+ // First thing is setup the exception vectors for this cpu.
mips64r2_vector_init(&mips_splsw);
// Next rewrite those exceptions to use this cpu's cpu_info.
Index: src/sys/arch/powerpc/include/booke/spr.h
diff -u src/sys/arch/powerpc/include/booke/spr.h:1.13 src/sys/arch/powerpc/include/booke/spr.h:1.14
--- src/sys/arch/powerpc/include/booke/spr.h:1.13 Sat Dec 27 12:36:48 2014
+++ src/sys/arch/powerpc/include/booke/spr.h Tue Aug 3 23:12:14 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: spr.h,v 1.13 2014/12/27 12:36:48 nonaka Exp $ */
+/* $NetBSD: spr.h,v 1.14 2021/08/03 23:12:14 andvar Exp $ */
/*-
* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -280,7 +280,7 @@
#define TSR_ENW 0x80000000 /* Enable Next Watchdog (W1C) */
#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status (W1C) */
#define TSR_WRS 0x30000000 /* Watchdog Reset Status (W1C) */
-#define TSR_DIS 0x08000000 /* Decementer Interrupt Status (W1C) */
+#define TSR_DIS 0x08000000 /* Decrementer Interrupt Status (W1C) */
#define TSR_FIS 0x04000000 /* Fixed-interval Interrupt Status (W1C) */
#define SPR_TCR 340 /* E... Timer Control Register */
#define TCR_WP 0xc0000000 /* Watchdog Period */
@@ -290,7 +290,7 @@
#define TCR_WRC 0x30000000 /* Watchdog Timer Reset Control */
#define TCR_WRC_RESET 0x20000000
#define TCR_WIE 0x08000000 /* Watchdog Time Interrupt Enable */
-#define TCR_DIE 0x04000000 /* Decremnter Interrupt Enable */
+#define TCR_DIE 0x04000000 /* Decrementer Interrupt Enable */
#define TCR_FP 0x03000000 /* Fixed-interval Timer Period */
#define TCR_FP_2_N(n) ((((64 - (n)) & 0x30) << 20) | (((64 - (n)) & 0xf) << 13))
#define TCR_FP_2_64 0x00000000
@@ -337,8 +337,8 @@
#define SPEFSCR_FDBZ 0x00000400 /* 21: Embedded Floating-Point Divide By Zero Error */
#define SPEFSCR_FUNF 0x00000200 /* 22: Embedded Floating-Point Underflow Error */
#define SPEFSCR_FOVF 0x00000100 /* 23: Embedded Floating-Point Overflow Error */
-#define SPEFSCR_FINXE 0x00000040 /* 25: Embedded Floating-Point Inexact Execption Enable */
-#define SPEFSCR_FINVE 0x00000020 /* 26: Embedded Floating-Point Invalid Operation/Input Error Execption Enable */
+#define SPEFSCR_FINXE 0x00000040 /* 25: Embedded Floating-Point Inexact Exception Enable */
+#define SPEFSCR_FINVE 0x00000020 /* 26: Embedded Floating-Point Invalid Operation/Input Error Exception Enable */
#define SPEFSCR_FDBZE 0x00000010 /* 27: Embedded Floating-Point Divide By Zero Exception Enable */
#define SPEFSCR_FUNFE 0x00000008 /* 28: Embedded Floating-Point Underflow Exception Enable */
#define SPEFSCR_FOVFE 0x00000004 /* 29: Embedded Floating-Point Overflow Exception Enable */
@@ -347,8 +347,8 @@
#define SPEFSCR_FRMC_UPWARD 0x00000002 /* Round toward +infinity */
#define SPEFSCR_FRMC_TOWARDZERO 0x00000001 /* Round toward zero */
#define SPEFSCR_FRMC_TONEAREST 0x00000000 /* Round to nearest */
-#define SPR_BBEAR 513 /* E... Brach buffer entry addr register */
-#define SPR_BBTAR 514 /* E... Brach buffer target addr register */
+#define SPR_BBEAR 513 /* E... Branch buffer entry addr register */
+#define SPR_BBTAR 514 /* E... Branch buffer target addr register */
#define SPR_L1CFG0 515 /* E... L1 Cache Configuration Register 0 */
#define SPR_L1CFG1 516 /* E... L1 Cache Configuration Register 1 */
#define L1CFG_CARCH_GET(n) (((n) >> 30) & 3)
@@ -436,7 +436,7 @@
#define MAS2_W 0x00000010 /* Write-through */
#define MAS2_I 0x00000008 /* cache-Inhibited */
#define MAS2_M 0x00000004 /* Memory coherency required */
-#define MAS2_G 0x00000002 /* Gaurded */
+#define MAS2_G 0x00000002 /* Guarded */
#define MAS2_E 0x00000001 /* [little] Endianness */
#define SPR_MAS3 627 /* E... MAS Register 3 */
#define MAS3_RPN 0xfffff000 /* Real Page Number */
@@ -472,7 +472,7 @@
#define MAS4_WD 0x00000010 /* default Write-through */
#define MAS4_ID 0x00000008 /* default Cache-inhibited */
#define MAS4_MD 0x00000004 /* default Memory coherency req. */
-#define MAS4_GD 0x00000002 /* default Gaurded */
+#define MAS4_GD 0x00000002 /* default Guarded */
#define MAS4_ED 0x00000001 /* default [little] Endianness */
#define SPR_MAS6 630 /* E... MAS Register 6 (TLB Seach CTX) */
#define MAS6_SPID0 0x0fff0000 /* PID used with tlbsx */
Index: src/sys/arch/riscv/riscv/fpu.c
diff -u src/sys/arch/riscv/riscv/fpu.c:1.1 src/sys/arch/riscv/riscv/fpu.c:1.2
--- src/sys/arch/riscv/riscv/fpu.c:1.1 Sat Mar 28 16:13:56 2015
+++ src/sys/arch/riscv/riscv/fpu.c Tue Aug 3 23:12:14 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu.c,v 1.1 2015/03/28 16:13:56 matt Exp $ */
+/* $NetBSD: fpu.c,v 1.2 2021/08/03 23:12:14 andvar Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.1 2015/03/28 16:13:56 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.2 2021/08/03 23:12:14 andvar Exp $");
#include "opt_multiprocessor.h"
@@ -133,7 +133,7 @@ fpu_state_load(lwp_t *l, u_int flags)
// Enable the FP when this lwp return to userspace.
tf->tf_sr |= SR_EF;
- // If this is a simple reeanble, set the FPU enable flag and return
+ // If this is a simple reenable, set the FPU enable flag and return
if (flags & PCU_REENABLE) {
curcpu()->ci_ev_fpu_reenables.ev_count++;
return;
Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.22 src/sys/arch/riscv/riscv/locore.S:1.23
--- src/sys/arch/riscv/riscv/locore.S:1.22 Sun May 16 09:02:04 2021
+++ src/sys/arch/riscv/riscv/locore.S Tue Aug 3 23:12:14 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.22 2021/05/16 09:02:04 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.23 2021/08/03 23:12:14 andvar Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -274,7 +274,7 @@ ENTRY_NP(cpu_fast_switchto)
PTR_L t1, L_CPU(tp) // get curcpu() again
mv tp, s0 // return to pinned lwp
PTR_S tp, CI_CURLWP(t1) // restore curlwp
- csrw sstatus, t0 // reeanble interrupts
+ csrw sstatus, t0 // reenable interrupts
mv sp, s1 // restore stack pointer
REG_L ra, (TF_RA + CALLFRAME_RA)(sp) // get return address
@@ -291,7 +291,7 @@ ENTRY_NP(cpu_exception_handler)
csrrw tp, sscratch, tp // swap scratch and thread pointer
beqz tp, .Lexception_kernel // tp == 0, already on kernel stack
//
- // The execption happened while user code was executing. We need to
+ // The exception happened while user code was executing. We need to
// get the pointer to the user trapframe from the LWP md area. Then we
// save t1 and tp so we have a register to work with and to get curlwp
// into tp. We also save the saved SP into the trapframe.
@@ -345,7 +345,7 @@ ENTRY_NP(cpu_exception_handler)
// Now we get the
mv a0, sp // trapframe pointer
- csrr a1, sepc // get execption pc
+ csrr a1, sepc // get exception pc
csrr a2, sstatus // get status
csrr a3, scause // get cause
@@ -387,10 +387,10 @@ exception_kernexit:
REG_L t5, TF_T3(sp) // restore t5
REG_L t6, TF_T4(sp) // restore t6
- REG_L t0, TF_PC(sp) // fetch execption PC
+ REG_L t0, TF_PC(sp) // fetch exception PC
REG_L t1, TF_SR(sp) // fetch status
- csrw sepc, t0 // restore execption PC
+ csrw sepc, t0 // restore exception PC
csrw sstatus, t1 // restore status
REG_L t0, TF_T0(sp) // restore t0
Index: src/sys/arch/vax/include/ka48.h
diff -u src/sys/arch/vax/include/ka48.h:1.4 src/sys/arch/vax/include/ka48.h:1.5
--- src/sys/arch/vax/include/ka48.h:1.4 Mon May 22 17:12:11 2017
+++ src/sys/arch/vax/include/ka48.h Tue Aug 3 23:12:14 2021
@@ -1,3 +1,4 @@
+/* $NetBSD: ka48.h,v 1.5 2021/08/03 23:12:14 andvar Exp $ */
/*
* Copyright (c) 1998 Ludd, University of Lule}, Sweden.
* All rights reserved.
@@ -51,7 +52,7 @@
/* From OpenVMS $IO440DEF & $KA440DEF */
#define KA48_PARCTL 0x20080014
-#define KA48_PARCTL_CPEN 0x00000001 /* CPU Parity Eanble? */
+#define KA48_PARCTL_CPEN 0x00000001 /* CPU Parity Enable? */
#define KA48_PARCTL_NPEN 0x00000100 /* ?? Parity Enable */
#define KA48_PARCTL_INVENA 0x01000000 /* Invalid ? Enable */
#define KA48_PARCTL_AGS 0x02000000 /* ??? */
Index: src/sys/dev/i2c/ds1307.c
diff -u src/sys/dev/i2c/ds1307.c:1.38 src/sys/dev/i2c/ds1307.c:1.39
--- src/sys/dev/i2c/ds1307.c:1.38 Wed Jan 27 02:29:48 2021
+++ src/sys/dev/i2c/ds1307.c Tue Aug 3 23:12:14 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: ds1307.c,v 1.38 2021/01/27 02:29:48 thorpej Exp $ */
+/* $NetBSD: ds1307.c,v 1.39 2021/08/03 23:12:14 andvar Exp $ */
/*
* Copyright (c) 2003 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.38 2021/01/27 02:29:48 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ds1307.c,v 1.39 2021/08/03 23:12:14 andvar Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -669,7 +669,7 @@ dsrtc_clock_write_ymdhms(struct dsrtc_so
}
/*
* If the clock hold register isn't the same register as seconds,
- * we need to reeanble the clock.
+ * we need to reenable the clock.
*/
if (op != I2C_OP_WRITE_WITH_STOP) {
cmdbuf[0] = dm->dm_ch_reg;
Index: src/sys/sys/evcnt.h
diff -u src/sys/sys/evcnt.h:1.9 src/sys/sys/evcnt.h:1.10
--- src/sys/sys/evcnt.h:1.9 Thu Apr 1 04:41:38 2021
+++ src/sys/sys/evcnt.h Tue Aug 3 23:12:14 2021
@@ -1,4 +1,4 @@
-/* $NetBSD: evcnt.h,v 1.9 2021/04/01 04:41:38 simonb Exp $ */
+/* $NetBSD: evcnt.h,v 1.10 2021/08/03 23:12:14 andvar Exp $ */
/*
* Copyright (c) 1996, 2000 Christopher G. Demetriou
@@ -102,7 +102,7 @@ TAILQ_HEAD(evcntlist, evcnt);
#define EVCNT_TYPE_ANY -1 /* for sysctl */
#define EVCNT_TYPE_MISC 0 /* miscellaneous; catch all */
#define EVCNT_TYPE_INTR 1 /* interrupt; count with vmstat -i */
-#define EVCNT_TYPE_TRAP 2 /* processor trap/execption */
+#define EVCNT_TYPE_TRAP 2 /* processor trap/exception */
#ifdef __HAVE_LEGACY_INTRCNT
void evcnt_attach_legacy_intrcnt(void);
