Module Name: src
Committed By: jruoho
Date: Wed Apr 14 08:47:19 UTC 2010
Modified Files:
src/lib/libc/atomic: atomic_ops.3
Log Message:
Use subtitles instead of a list.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/lib/libc/atomic/atomic_ops.3
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/lib/libc/atomic/atomic_ops.3
diff -u src/lib/libc/atomic/atomic_ops.3:1.3 src/lib/libc/atomic/atomic_ops.3:1.4
--- src/lib/libc/atomic/atomic_ops.3:1.3 Mon May 18 12:40:21 2009
+++ src/lib/libc/atomic/atomic_ops.3 Wed Apr 14 08:47:19 2010
@@ -1,4 +1,4 @@
-.\" $NetBSD: atomic_ops.3,v 1.3 2009/05/18 12:40:21 wiz Exp $
+.\" $NetBSD: atomic_ops.3,v 1.4 2010/04/14 08:47:19 jruoho Exp $
.\"
.\" Copyright (c) 2007, 2008 The NetBSD Foundation, Inc.
.\" All rights reserved.
@@ -43,7 +43,7 @@
family of functions provide atomic memory operations.
There are 7 classes of atomic memory operations available:
.Pp
-.Bl -tag -width "atomic_swap(3)"
+.Bl -tag -width "atomic_swap(3)" -offset indent
.It Xr atomic_add 3
These functions perform atomic addition.
.It Xr atomic_and 3
@@ -61,9 +61,7 @@
.It Xr atomic_swap 3
These functions perform atomic swap.
.El
-.Pp
-.Bl -tag -width aa
-.It Synchronization mechanisms
+.Ss Synchronization Mechanisms
Where the architecture does not provide hardware support for atomic compare
and swap (CAS), atomicity is provided by a restartable sequence or by a
spinlock.
@@ -71,7 +69,7 @@
of the interface.
The following architectures can be assumed to provide CAS in hardware:
alpha, amd64, i386, powerpc, powerpc64, sparc64.
-.It Scope and restrictions
+.Ss Scope and Restrictions
If hardware CAS is available, the atomic operations are globally atomic:
operations within a memory region shared between processes are
guaranteed to be performed atomically.
@@ -93,7 +91,7 @@
some other synchronization mechanism.
Intermixing of atomic operations with other synchronization mechanisms
for the same memory location results in undefined behavior.
-.It Visibility and ordering of memory accesses
+.Ss Visibility and Ordering of Memory Accesses
If hardware CAS is available, stores to the target memory location by an
atomic operation will reach global visibility before the operation
completes.
@@ -110,12 +108,11 @@
to an atomic operation must use memory barriers.
See
.Xr membar_ops 3 .
-.It Performance
+.Ss Performance
Because atomic memory operations require expensive synchronization at the
hardware level, applications should take care to minimize their use.
In certain cases, it may be more appropriate to use a mutex, especially
if more than one memory location will be modified.
-.El
.Sh SEE ALSO
.Xr atomic_add 3 ,
.Xr atomic_and 3 ,
