Module Name: src Committed By: kiyohara Date: Sat Apr 24 09:39:57 UTC 2010
Modified Files: src/sys/arch/bebox/include: intr.h src/sys/arch/ibmnws/include: intr.h src/sys/arch/mvmeppc/include: intr.h src/sys/arch/ofppc/include: intr.h src/sys/arch/powerpc/include: cpu.h src/sys/arch/powerpc/pic: intr.c picvar.h src/sys/arch/powerpc/powerpc: clock.c src/sys/arch/prep/include: intr.h src/sys/arch/sandpoint/include: intr.h Log Message: Support 64-bit imask for powerpc/pic. To generate a diff of this commit: cvs rdiff -u -r1.28 -r1.29 src/sys/arch/bebox/include/intr.h cvs rdiff -u -r1.12 -r1.13 src/sys/arch/ibmnws/include/intr.h cvs rdiff -u -r1.13 -r1.14 src/sys/arch/mvmeppc/include/intr.h cvs rdiff -u -r1.12 -r1.13 src/sys/arch/ofppc/include/intr.h cvs rdiff -u -r1.69 -r1.70 src/sys/arch/powerpc/include/cpu.h cvs rdiff -u -r1.7 -r1.8 src/sys/arch/powerpc/pic/intr.c cvs rdiff -u -r1.6 -r1.7 src/sys/arch/powerpc/pic/picvar.h cvs rdiff -u -r1.7 -r1.8 src/sys/arch/powerpc/powerpc/clock.c cvs rdiff -u -r1.31 -r1.32 src/sys/arch/prep/include/intr.h cvs rdiff -u -r1.16 -r1.17 src/sys/arch/sandpoint/include/intr.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/bebox/include/intr.h diff -u src/sys/arch/bebox/include/intr.h:1.28 src/sys/arch/bebox/include/intr.h:1.29 --- src/sys/arch/bebox/include/intr.h:1.28 Mon Apr 28 20:23:15 2008 +++ src/sys/arch/bebox/include/intr.h Sat Apr 24 09:39:56 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: intr.h,v 1.28 2008/04/28 20:23:15 martin Exp $ */ +/* $NetBSD: intr.h,v 1.29 2010/04/24 09:39:56 kiyohara Exp $ */ /*- * Copyright (c) 1998 The NetBSD Foundation, Inc. @@ -40,7 +40,6 @@ void enable_intr(void); void disable_intr(void); -extern int imask[]; extern paddr_t bebox_mb_reg; #define ICU_LEN 32 Index: src/sys/arch/ibmnws/include/intr.h diff -u src/sys/arch/ibmnws/include/intr.h:1.12 src/sys/arch/ibmnws/include/intr.h:1.13 --- src/sys/arch/ibmnws/include/intr.h:1.12 Mon Apr 28 20:23:26 2008 +++ src/sys/arch/ibmnws/include/intr.h Sat Apr 24 09:39:57 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: intr.h,v 1.12 2008/04/28 20:23:26 martin Exp $ */ +/* $NetBSD: intr.h,v 1.13 2010/04/24 09:39:57 kiyohara Exp $ */ /*- * Copyright (c) 1998 The NetBSD Foundation, Inc. @@ -44,7 +44,6 @@ void enable_intr(void); void disable_intr(void); -extern int imask[]; extern vaddr_t prep_intr_reg; extern uint32_t prep_intr_reg_off; Index: src/sys/arch/mvmeppc/include/intr.h diff -u src/sys/arch/mvmeppc/include/intr.h:1.13 src/sys/arch/mvmeppc/include/intr.h:1.14 --- src/sys/arch/mvmeppc/include/intr.h:1.13 Mon Apr 28 20:23:29 2008 +++ src/sys/arch/mvmeppc/include/intr.h Sat Apr 24 09:39:57 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: intr.h,v 1.13 2008/04/28 20:23:29 martin Exp $ */ +/* $NetBSD: intr.h,v 1.14 2010/04/24 09:39:57 kiyohara Exp $ */ /*- * Copyright (c) 1998 The NetBSD Foundation, Inc. @@ -39,7 +39,6 @@ void enable_intr(void); void disable_intr(void); -extern int imask[]; extern vaddr_t mvmeppc_intr_reg; #define ICU_LEN 32 Index: src/sys/arch/ofppc/include/intr.h diff -u src/sys/arch/ofppc/include/intr.h:1.12 src/sys/arch/ofppc/include/intr.h:1.13 --- src/sys/arch/ofppc/include/intr.h:1.12 Mon Apr 28 20:23:30 2008 +++ src/sys/arch/ofppc/include/intr.h Sat Apr 24 09:39:57 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: intr.h,v 1.12 2008/04/28 20:23:30 martin Exp $ */ +/* $NetBSD: intr.h,v 1.13 2010/04/24 09:39:57 kiyohara Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -40,7 +40,6 @@ #define ICU_LEN 32 #define IRQ_SLAVE 2 -extern int imask[]; #endif Index: src/sys/arch/powerpc/include/cpu.h diff -u src/sys/arch/powerpc/include/cpu.h:1.69 src/sys/arch/powerpc/include/cpu.h:1.70 --- src/sys/arch/powerpc/include/cpu.h:1.69 Thu Mar 18 13:47:05 2010 +++ src/sys/arch/powerpc/include/cpu.h Sat Apr 24 09:39:57 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: cpu.h,v 1.69 2010/03/18 13:47:05 kiyohara Exp $ */ +/* $NetBSD: cpu.h,v 1.70 2010/04/24 09:39:57 kiyohara Exp $ */ /* * Copyright (C) 1999 Wolfgang Solfrank. @@ -74,7 +74,7 @@ volatile int ci_cpl; volatile int ci_iactive; volatile int ci_idepth; - volatile int ci_ipending; + volatile imask_t ci_ipending; int ci_intrdepth; int ci_mtx_oldspl; int ci_mtx_count; Index: src/sys/arch/powerpc/pic/intr.c diff -u src/sys/arch/powerpc/pic/intr.c:1.7 src/sys/arch/powerpc/pic/intr.c:1.8 --- src/sys/arch/powerpc/pic/intr.c:1.7 Wed Mar 10 18:28:30 2010 +++ src/sys/arch/powerpc/pic/intr.c Sat Apr 24 09:39:57 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: intr.c,v 1.7 2010/03/10 18:28:30 kiyohara Exp $ */ +/* $NetBSD: intr.c,v 1.8 2010/04/24 09:39:57 kiyohara Exp $ */ /*- * Copyright (c) 2007 Michael Lorenz @@ -27,7 +27,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.7 2010/03/10 18:28:30 kiyohara Exp $"); +__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.8 2010/04/24 09:39:57 kiyohara Exp $"); #include "opt_multiprocessor.h" @@ -51,11 +51,6 @@ #define MAX_PICS 8 /* 8 PICs ought to be enough for everyone */ -#define NVIRQ 32 /* 32 virtual IRQs */ -#define NIRQ 128 /* up to 128 HW IRQs */ - -#define HWIRQ_MAX (NVIRQ - 4 - 1) -#define HWIRQ_MASK 0x0fffffff #define LEGAL_VIRQ(x) ((x) >= 0 && (x) < NVIRQ) struct pic_ops *pics[MAX_PICS]; @@ -63,7 +58,7 @@ int max_base = 0; uint8_t virq[NIRQ]; int virq_max = 0; -int imask[NIPL]; +imask_t imask[NIPL]; int primary_pic = 0; static int fakeintr(void *); @@ -352,10 +347,10 @@ /* Then figure out which IRQs use each level. */ for (level = 0; level < NIPL; level++) { - register int irqs = 0; + register imask_t irqs = 0; for (irq = 0, is = intrsources; irq < NVIRQ; irq++, is++) if (is->is_level & (1 << level)) - irqs |= 1 << irq; + irqs |= 1ULL << irq; imask[level] = irqs; } @@ -363,14 +358,14 @@ * IPL_CLOCK should mask clock interrupt even if interrupt handler * is not registered. */ - imask[IPL_CLOCK] |= 1 << SPL_CLOCK; + imask[IPL_CLOCK] |= 1ULL << SPL_CLOCK; /* * Initialize soft interrupt masks to block themselves. */ - imask[IPL_SOFTCLOCK] = 1 << SIR_CLOCK; - imask[IPL_SOFTNET] = 1 << SIR_NET; - imask[IPL_SOFTSERIAL] = 1 << SIR_SERIAL; + imask[IPL_SOFTCLOCK] = 1ULL << SIR_CLOCK; + imask[IPL_SOFTNET] = 1ULL << SIR_NET; + imask[IPL_SOFTSERIAL] = 1ULL << SIR_SERIAL; /* * IPL_NONE is used for hardware interrupts that are never blocked, @@ -419,7 +414,7 @@ /* And eventually calculate the complete masks. */ for (irq = 0, is = intrsources; irq < NVIRQ; irq++, is++) { - register int irqs = 1 << irq; + register imask_t irqs = 1ULL << irq; for (q = is->is_hand; q; q = q->ih_next) irqs |= imask[q->ih_level]; is->is_mask = irqs; @@ -463,7 +458,7 @@ msr = mfmsr(); mtmsr(msr & ~PSL_EE); - ci->ci_ipending |= 1 << v; + ci->ci_ipending |= 1ULL << v; mtmsr(msr); } @@ -476,7 +471,7 @@ struct pic_ops *pic; int irq; int pcpl; - int hwpend; + imask_t hwpend; int emsr, dmsr; if (ci->ci_iactive) @@ -496,9 +491,10 @@ /* Do now unmasked pendings */ ci->ci_idepth++; while ((hwpend = (ci->ci_ipending & ~pcpl & HWIRQ_MASK)) != 0) { - irq = 31 - cntlzw(hwpend); + /* Get most significant pending bit */ + irq = MS_PENDING(hwpend); KASSERT(irq <= virq_max); - ci->ci_ipending &= ~(1 << irq); + ci->ci_ipending &= ~(1ULL << irq); if (irq == 0) { printf("VIRQ0"); continue; @@ -536,8 +532,8 @@ ci->ci_idepth--; #ifdef __HAVE_FAST_SOFTINTS - if ((ci->ci_ipending & ~pcpl) & (1 << SIR_SERIAL)) { - ci->ci_ipending &= ~(1 << SIR_SERIAL); + if ((ci->ci_ipending & ~pcpl) & (1ULL << SIR_SERIAL)) { + ci->ci_ipending &= ~(1ULL << SIR_SERIAL); splsoftserial(); mtmsr(emsr); softintr__run(IPL_SOFTSERIAL); @@ -546,8 +542,8 @@ ci->ci_ev_softserial.ev_count++; goto again; } - if ((ci->ci_ipending & ~pcpl) & (1 << SIR_NET)) { - ci->ci_ipending &= ~(1 << SIR_NET); + if ((ci->ci_ipending & ~pcpl) & (1ULL << SIR_NET)) { + ci->ci_ipending &= ~(1ULL << SIR_NET); splsoftnet(); mtmsr(emsr); softintr__run(IPL_SOFTNET); @@ -556,8 +552,8 @@ ci->ci_ev_softnet.ev_count++; goto again; } - if ((ci->ci_ipending & ~pcpl) & (1 << SIR_CLOCK)) { - ci->ci_ipending &= ~(1 << SIR_CLOCK); + if ((ci->ci_ipending & ~pcpl) & (1ULL << SIR_CLOCK)) { + ci->ci_ipending &= ~(1ULL << SIR_CLOCK); splsoftclock(); mtmsr(emsr); softintr__run(IPL_SOFTCLOCK); @@ -581,7 +577,8 @@ struct intr_source *is; struct intrhand *ih; int irq, realirq; - int pcpl, msr, r_imen, bail; + int pcpl, msr, bail; + imask_t r_imen; realirq = pic->pic_get_irq(pic, PIC_GET_IRQ); if (realirq == 255) @@ -612,7 +609,7 @@ } #endif /* PIC_DEBUG */ KASSERT(realirq < pic->pic_numintrs); - r_imen = 1 << irq; + r_imen = 1ULL << irq; is = &intrsources[irq]; if ((pcpl & r_imen) != 0) { @@ -685,7 +682,7 @@ __asm volatile("sync; eieio"); /* don't reorder.... */ ocpl = ci->ci_cpl; - ci->ci_cpl = ocpl | ncpl; + ci->ci_cpl = ncpl; __asm volatile("sync; eieio"); /* reorder protect */ return ocpl; } @@ -726,7 +723,7 @@ msrsave = mfmsr(); mtmsr(msrsave & ~PSL_EE); - curcpu()->ci_ipending |= 1 << ipl; + curcpu()->ci_ipending |= 1ULL << ipl; mtmsr(msrsave); } @@ -734,9 +731,9 @@ genppc_cpu_configure(void) { aprint_normal("biomask %x netmask %x ttymask %x\n", - imask[IPL_BIO] & 0x1fffffff, - imask[IPL_NET] & 0x1fffffff, - imask[IPL_TTY] & 0x1fffffff); + (u_int)imask[IPL_BIO] & 0x1fffffff, + (u_int)imask[IPL_NET] & 0x1fffffff, + (u_int)imask[IPL_TTY] & 0x1fffffff); spl0(); } Index: src/sys/arch/powerpc/pic/picvar.h diff -u src/sys/arch/powerpc/pic/picvar.h:1.6 src/sys/arch/powerpc/pic/picvar.h:1.7 --- src/sys/arch/powerpc/pic/picvar.h:1.6 Wed Aug 19 06:22:54 2009 +++ src/sys/arch/powerpc/pic/picvar.h Sat Apr 24 09:39:57 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: picvar.h,v 1.6 2009/08/19 06:22:54 nisimura Exp $ */ +/* $NetBSD: picvar.h,v 1.7 2010/04/24 09:39:57 kiyohara Exp $ */ /*- * Copyright (c) 2007 Michael Lorenz @@ -27,7 +27,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: picvar.h,v 1.6 2009/08/19 06:22:54 nisimura Exp $"); +__KERNEL_RCSID(0, "$NetBSD: picvar.h,v 1.7 2010/04/24 09:39:57 kiyohara Exp $"); #ifndef PIC_VAR_H #define PIC_VAR_H @@ -58,7 +58,7 @@ int is_type; int is_level; int is_hwirq; - int is_mask; + imask_t is_mask; struct intrhand *is_hand; struct pic_ops *is_pic; struct evcnt is_ev; Index: src/sys/arch/powerpc/powerpc/clock.c diff -u src/sys/arch/powerpc/powerpc/clock.c:1.7 src/sys/arch/powerpc/powerpc/clock.c:1.8 --- src/sys/arch/powerpc/powerpc/clock.c:1.7 Thu Feb 25 23:31:48 2010 +++ src/sys/arch/powerpc/powerpc/clock.c Sat Apr 24 09:39:57 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: clock.c,v 1.7 2010/02/25 23:31:48 matt Exp $ */ +/* $NetBSD: clock.c,v 1.8 2010/04/24 09:39:57 kiyohara Exp $ */ /* $OpenBSD: clock.c,v 1.3 1997/10/13 13:42:53 pefo Exp $ */ /* @@ -33,7 +33,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.7 2010/02/25 23:31:48 matt Exp $"); +__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.8 2010/04/24 09:39:57 kiyohara Exp $"); #include <sys/param.h> #include <sys/kernel.h> @@ -171,7 +171,7 @@ * Do standard timer interrupt stuff. * Do softclock stuff only on the last iteration. */ - frame->pri = pri | (1 << SIR_CLOCK); + frame->pri = pri | (1ULL << SIR_CLOCK); while (--nticks > 0) hardclock(frame); frame->pri = pri; Index: src/sys/arch/prep/include/intr.h diff -u src/sys/arch/prep/include/intr.h:1.31 src/sys/arch/prep/include/intr.h:1.32 --- src/sys/arch/prep/include/intr.h:1.31 Mon Apr 28 20:23:33 2008 +++ src/sys/arch/prep/include/intr.h Sat Apr 24 09:39:57 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: intr.h,v 1.31 2008/04/28 20:23:33 martin Exp $ */ +/* $NetBSD: intr.h,v 1.32 2010/04/24 09:39:57 kiyohara Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -44,7 +44,6 @@ void enable_intr(void); void disable_intr(void); -extern int imask[]; extern vaddr_t prep_intr_reg; extern uint32_t prep_intr_reg_off; Index: src/sys/arch/sandpoint/include/intr.h diff -u src/sys/arch/sandpoint/include/intr.h:1.16 src/sys/arch/sandpoint/include/intr.h:1.17 --- src/sys/arch/sandpoint/include/intr.h:1.16 Mon Apr 28 20:23:34 2008 +++ src/sys/arch/sandpoint/include/intr.h Sat Apr 24 09:39:57 2010 @@ -1,4 +1,4 @@ -/* $NetBSD: intr.h,v 1.16 2008/04/28 20:23:34 martin Exp $ */ +/* $NetBSD: intr.h,v 1.17 2010/04/24 09:39:57 kiyohara Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -41,8 +41,6 @@ void enable_intr(void); void disable_intr(void); -extern int imask[]; - #define ICU_LEN 64 #define IRQ_SLAVE 2