Module Name: src
Committed By: cliff
Date: Tue Apr 27 05:44:30 UTC 2010
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: cpuregs.h
Log Message:
seperate RMI CPU revision codes from RMI CPU processor codes
and improve comment
To generate a diff of this commit:
cvs rdiff -u -r1.74.28.17 -r1.74.28.18 src/sys/arch/mips/include/cpuregs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.74.28.17 src/sys/arch/mips/include/cpuregs.h:1.74.28.18
--- src/sys/arch/mips/include/cpuregs.h:1.74.28.17 Mon Mar 29 23:33:00 2010
+++ src/sys/arch/mips/include/cpuregs.h Tue Apr 27 05:44:30 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.74.28.17 2010/03/29 23:33:00 cliff Exp $ */
+/* $NetBSD: cpuregs.h,v 1.74.28.18 2010/04/27 05:44:30 cliff Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -871,12 +871,15 @@
#define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */
/*
- * CPU processor revision IDs for company ID == 12 (RMI)
- * note: the XLR Pid value meaning depends on
- * the Rev value (Stepping B2 or C4)
+ * CPU revision IDs for company ID == 12 (RMI)
+ * note: unlisted Rev values may indicate pre-production silicon
+ */
+#define MIPS_XLR_B2 0x04 /* RMI XLR Production Rev B2 */
+#define MIPS_XLR_C4 0x91 /* RMI XLR Production Rev C4 */
+
+/*
+ * CPU processor IDs for company ID == 12 (RMI)
*/
-#define MIPS_XLR_B2 0x04 /* RMI XLR Rev B2 */
-#define MIPS_XLR_C4 0x91 /* RMI XLR Rev C4 */
#define MIPS_XLR308B 0x06 /* RMI XLR308-B ISA 64 */
#define MIPS_XLR508B 0x07 /* RMI XLR508-B ISA 64 */
#define MIPS_XLR516B 0x08 /* RMI XLR516-B ISA 64 */
