Module Name:    src
Committed By:   hans
Date:           Sun May  9 22:29:26 UTC 2010

Modified Files:
        src/sys/dev/dec: dz.c

Log Message:
The interrupt handler uses the softc, so it's probably a good idea to
initialize it before causing interrupts. Prevents a panic on VAXstation
4000/9x with SPX console.


To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/dev/dec/dz.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/dev/dec/dz.c
diff -u src/sys/dev/dec/dz.c:1.38 src/sys/dev/dec/dz.c:1.39
--- src/sys/dev/dec/dz.c:1.38	Mon Sep  8 23:36:54 2008
+++ src/sys/dev/dec/dz.c	Sun May  9 22:29:26 2010
@@ -1,4 +1,4 @@
-/*	$NetBSD: dz.c,v 1.38 2008/09/08 23:36:54 gmcgarry Exp $	*/
+/*	$NetBSD: dz.c,v 1.39 2010/05/09 22:29:26 hans Exp $	*/
 /*
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -67,7 +67,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dz.c,v 1.38 2008/09/08 23:36:54 gmcgarry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dz.c,v 1.39 2010/05/09 22:29:26 hans Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -204,16 +204,7 @@
 {
 	int n;
 
-	sc->sc_rxint = sc->sc_brk = 0;
-	sc->sc_consline = consline;
-
-	sc->sc_dr.dr_tcrw = sc->sc_dr.dr_tcr;
-	dz_write2(sc, sc->sc_dr.dr_csr, DZ_CSR_MSE | DZ_CSR_RXIE | DZ_CSR_TXIE);
-	dz_write1(sc, sc->sc_dr.dr_dtr, 0);
-	dz_write1(sc, sc->sc_dr.dr_break, 0);
-	DELAY(10000);
-
-	/* Initialize our softc structure. Should be done in open? */
+	/* Initialize our softc structure. */
 
 	for (n = 0; n < sc->sc_type; n++) {
 		sc->sc_dz[n].dz_sc = sc;
@@ -231,6 +222,15 @@
 	cn_set_magic("\047\001"); /* default magic is BREAK */
 				  /* VAX will change it in MD code */
 
+	sc->sc_rxint = sc->sc_brk = 0;
+	sc->sc_consline = consline;
+
+	sc->sc_dr.dr_tcrw = sc->sc_dr.dr_tcr;
+	dz_write2(sc, sc->sc_dr.dr_csr, DZ_CSR_MSE | DZ_CSR_RXIE | DZ_CSR_TXIE);
+	dz_write1(sc, sc->sc_dr.dr_dtr, 0);
+	dz_write1(sc, sc->sc_dr.dr_break, 0);
+	DELAY(10000);
+
 	/* Alas no interrupt on modem bit changes, so we manually scan */
 	if (dz_timer == 0) {
 		dz_timer = 1;

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