Module Name: src
Committed By: cliff
Date: Fri May 28 22:14:53 UTC 2010
Modified Files:
src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_intr.c rmixl_spl.S
Log Message:
rmixl_spl.S:
- where possible, stop using CP0 STATUS to disable all interrupts,zero EIMR
instead. more efficient since less meddling with CP0.
assume STATUS[IE] is normally set.
- add rmixl_spl_init_cpu(), to initialize cp0 interrupt control for this cpu
rmixl_intr.c:
- rmixl_intr_init_cpu() calls rmixl_spl_init_cpu()
to set up CP0 interrupt controls for this cpu
To generate a diff of this commit:
cvs rdiff -u -r1.1.2.20 -r1.1.2.21 src/sys/arch/mips/rmi/rmixl_intr.c
cvs rdiff -u -r1.1.2.3 -r1.1.2.4 src/sys/arch/mips/rmi/rmixl_spl.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/rmi/rmixl_intr.c
diff -u src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.20 src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.21
--- src/sys/arch/mips/rmi/rmixl_intr.c:1.1.2.20 Fri May 21 23:35:42 2010
+++ src/sys/arch/mips/rmi/rmixl_intr.c Fri May 28 22:14:53 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_intr.c,v 1.1.2.20 2010/05/21 23:35:42 cliff Exp $ */
+/* $NetBSD: rmixl_intr.c,v 1.1.2.21 2010/05/28 22:14:53 cliff Exp $ */
/*-
* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
@@ -64,7 +64,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.20 2010/05/21 23:35:42 cliff Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.1.2.21 2010/05/28 22:14:53 cliff Exp $");
#include "opt_ddb.h"
#define __INTR_PRIVATE
@@ -474,13 +474,11 @@
rmixl_intr_init_cpu(struct cpu_info *ci)
{
struct rmixl_cpu_softc *sc = (void *)ci->ci_softc;
+ extern void rmixl_spl_init_cpu(void);
+
KASSERT(sc != NULL);
- /* ack any pending in the EIRR, zeroing CAUSE[8..15] */
- uint64_t eirr;
- asm volatile("dmfc0 %0, $9, 6;" : "=r"(eirr));
- eirr &= ~0xff;
- asm volatile("dmtc0 %0, $9, 6;" :: "r"(eirr));
+ rmixl_spl_init_cpu();
for (int vec=0; vec < NINTRVECS; vec++)
evcnt_attach_dynamic(&sc->sc_vec_evcnts[vec],
Index: src/sys/arch/mips/rmi/rmixl_spl.S
diff -u src/sys/arch/mips/rmi/rmixl_spl.S:1.1.2.3 src/sys/arch/mips/rmi/rmixl_spl.S:1.1.2.4
--- src/sys/arch/mips/rmi/rmixl_spl.S:1.1.2.3 Fri May 21 23:35:21 2010
+++ src/sys/arch/mips/rmi/rmixl_spl.S Fri May 28 22:14:53 2010
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_spl.S,v 1.1.2.3 2010/05/21 23:35:21 cliff Exp $ */
+/* $NetBSD: rmixl_spl.S,v 1.1.2.4 2010/05/28 22:14:53 cliff Exp $ */
/*-
* Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
@@ -37,7 +37,7 @@
#include <mips/asm.h>
#include <mips/cpuregs.h>
-RCSID("$NetBSD: rmixl_spl.S,v 1.1.2.3 2010/05/21 23:35:21 cliff Exp $");
+RCSID("$NetBSD: rmixl_spl.S,v 1.1.2.4 2010/05/28 22:14:53 cliff Exp $");
#include "assym.h"
@@ -71,6 +71,29 @@
.dword 0 /* IPL_HIGH */
.text
+
+/*
+ * initialize cp0 interrupt control for this cpu
+ * - set STATUS[IE]
+ * - clear EIRR and EIMR
+ * on return, all interrupts are disabled by EIMR
+ *
+ * henceforth STATUS[IE] is expected to remain normally set
+ * but may be cleared and restored for temporary interrupt disablement
+ *
+ * call before the first call to spl0 on this cpu
+ */
+LEAF_NOPROFILE(rmixl_spl_init_cpu)
+ mfc0 t0, MIPS_COP_0_STATUS # get STATUS
+ ori t0, MIPS_SR_INT_IE # set IE
+ mtc0 zero, MIPS_COP_0_STATUS ## disable all ints in STATUS
+ dmtc0 zero, RMIXL_COP_0_EIMR ## " " " " EIMR
+ dmtc0 zero, RMIXL_COP_0_EIRR ## clear EIRR
+ mtc0 t0, MIPS_COP_0_STATUS ## set STATUS | IE
+ j ra
+ nop
+END(rmixl_spl_init_cpu)
+
/*
* RMIXL processor interrupt control
*
@@ -86,15 +109,10 @@
INT_L v0, CPU_INFO_CPL(a3) # get current IPL from cpu_info
sltu v1, a1, v0 # newipl < curipl
bnez v1, 2f # yes, don't change.
- mfc0 a2, MIPS_COP_0_STATUS # load STATUS
- and a2, ~MIPS_INT_MASK # clear STATUS[IM]
- sll v1, a0, 8 # EIMR[7:0] to STATUS[15:8]
- and v1, MIPS_INT_MASK # " " "
- or v1, a2 # new STATUS value
- mtc0 zero, MIPS_COP_0_STATUS ## disable all ints in STATUS
+ nop
+ dmtc0 zero, RMIXL_COP_0_EIMR ## disable all interrupts
INT_S a1, CPU_INFO_CPL(a3) ## save IPL in cpu_info
dmtc0 a0, RMIXL_COP_0_EIMR ## set new EIMR
- mtc0 v1, MIPS_COP_0_STATUS ## set new STATUS
#ifdef PARANOIA
j ra
nop
@@ -118,22 +136,14 @@
99: beqz v0, 99b # loop forever if false
nop
#endif /* PARANOIA */
- #move a1, zero # avoid lookup on splx(IPL_NONE)
- #beq a0, zero, 1f # skip load
PTR_LA v1, _C_LABEL(ipl_eimr_map) # get address of table
sll a2, a0, MAP_SCALESHIFT # convert IPL to array offset
PTR_ADDU v1, a2 # add to table addr
REG_L v1, (v1) # load EIMR bits for this IPL
1:
- dmfc0 a2, MIPS_COP_0_STATUS # load STATUS
- and a2, ~MIPS_INT_MASK # clear STATUS[IM]
- sll v0, v1, 8 # EIMR[7:0] to STATUS[15:8]
- and v0, MIPS_INT_MASK # " " "
- or v0, a2 # new STATUS value
dmtc0 zero, RMIXL_COP_0_EIMR ## disable all interrupts
- INT_S a0, CPU_INFO_CPL(a3) ## save IPL in cpu_info (KSEG0)
+ INT_S a0, CPU_INFO_CPL(a3) ## save IPL in cpu_info
dmtc0 v1, RMIXL_COP_0_EIMR ## set new EIMR
- mtc0 v0, MIPS_COP_0_STATUS ## set new STATUS
#ifdef PARANOIA
j ra
nop
@@ -155,23 +165,13 @@
STATIC_LEAF(_splsw_spl0)
REG_L v1, _C_LABEL(ipl_eimr_map) + 8*IPL_NONE
PTR_L a3, L_CPU(MIPS_CURLWP)
- mtc0 zero, MIPS_COP_0_CAUSE # clear SOFT_INT bits
- dmfc0 a2, MIPS_COP_0_STATUS # load STATUS
- and a2, ~MIPS_INT_MASK # clear STATUS[IM]
- sll v0, v1, 8 # EIMR[7:0] to STATUS[15:8]
- and v0, MIPS_INT_MASK # " " "
- or v0, MIPS_SR_INT_IE # set STATUS[IE]
- or v0, a2 # new STATUS value
- mtc0 zero, MIPS_COP_0_STATUS ## disable all interrupts
+ dmtc0 zero, RMIXL_COP_0_EIMR ## disable all interrupts
#if IPL_NONE == 0
INT_S zero, CPU_INFO_CPL(a3) ## set ipl to 0
#else
#error IPL_NONE != 0
#endif
dmtc0 v1, RMIXL_COP_0_EIMR ## set new EIMR
- mtc0 v0, MIPS_COP_0_STATUS ## set new STATUS
- nop
- nop
j ra
nop
END(_splsw_spl0)
@@ -186,31 +186,26 @@
END(rmixl_spln)
STATIC_LEAF(_splsw_setsoftintr)
- mfc0 v1, MIPS_COP_0_STATUS # save status register
- mtc0 zero, MIPS_COP_0_STATUS ## disable interrupts (2 cycles)
- nop
- nop
+ dmfc0 v1, RMIXL_COP_0_EIMR # save EIMR register
+ dmtc0 zero, RMIXL_COP_0_EIMR ## disable all interrupts
mfc0 v0, MIPS_COP_0_CAUSE ## load cause register
- nop
or v0, v0, a0 ## set soft intr. bits
mtc0 v0, MIPS_COP_0_CAUSE ## store back
- mtc0 v1, MIPS_COP_0_STATUS ## enable interrupts
+ dmtc0 v1, RMIXL_COP_0_EIMR ## restore EIMR
j ra
- nop
+ nop
END(_splsw_setsoftintr)
STATIC_LEAF(_splsw_clrsoftintr)
- mfc0 v1, MIPS_COP_0_STATUS # save status register
- mtc0 zero, MIPS_COP_0_STATUS ## disable interrupts (2 cycles)
- nop
- nop
+ dmfc0 v1, RMIXL_COP_0_EIMR # save EIMR register
+ dmtc0 zero, RMIXL_COP_0_EIMR ## disable all interrupts
mfc0 v0, MIPS_COP_0_CAUSE ## load cause register
nor a0, zero, a0 ## bitwise inverse of A0
and v0, v0, a0 ## clear soft intr. bits
mtc0 v0, MIPS_COP_0_CAUSE ## store back
- mtc0 v1, MIPS_COP_0_STATUS ## enable interrupts
+ dmtc0 v1, RMIXL_COP_0_EIMR ## enable EIMR
j ra
- nop
+ nop
END(_splsw_clrsoftintr)
STATIC_LEAF(_splsw_splraise)
@@ -229,15 +224,10 @@
INT_L v0, CPU_INFO_CPL(a3) # get current IPL from cpu_info
li a1, IPL_HIGH #
beq v0, a1, 1f # don't do anything if IPL_HIGH
- mfc0 v1, MIPS_COP_0_STATUS # load STATUS
- move a2, zero # clear for EIMR
- and a0, v1, MIPS_INT_MASK # select all interrupts
- xor a0, v1 # clear STATUS[IM]
- mtc0 zero, MIPS_COP_0_STATUS ## disable all interrupts
+ nop
+ dmtc0 zero, RMIXL_COP_0_EIMR ## disable all interrupts
INT_S a1, CPU_INFO_CPL(a3) ## save IPL in cpu_info
- dmtc0 a2, RMIXL_COP_0_EIMR ## set new EIMR
- mtc0 a0, MIPS_COP_0_STATUS ## set new STATUS
- nop # XXXXX
+ ## interrupts remain disabled!
#ifdef PARANOIA
j ra # return
nop
@@ -323,6 +313,7 @@
addiu v0, 1 # ipl++
move v1, ta2 # update highest pending
b 1b # loop
+ nop
2:
/*
